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Journal articles on the topic 'Asynchronous circuit design (clockless)'

Author: Grafiati

Published: 28 May 2022

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1

Aguénounon, Enagnon, Safa Razavinejad, Jean-Baptiste Schell, Mohammadreza Dolatpoor Lakeh, Wassim Khaddour, Foudil Dadouche, Jean-Baptiste Kammerer, Laurent Fesquet, and Wilfried Uhring. "Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout." Sensors 21, no. 12 (June 8, 2021): 3949. http://dx.doi.org/10.3390/s21123949.

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The usage of single-photon avalanche diode arrays is becoming increasingly common in various domains such as medical imaging, automotive vision systems, and optical communications. Nowadays, thanks to the development of microelectronics technologies, the SPAD arrays designed for these applications has been drastically well-facilitated, allowing for the manufacturing of large matrices. However, there are growing challenges for the design of readout circuits with the needs of reducing their energy consumption (linked to the usage cost) and data rate. Indeed, the design of the readout circuit for the SPAD array is generally based on synchronous logic; the latter requires synchronization that may increase the dead time of the SPADs and clock trees management that are known to increase power consumption. With these limitations, the long-neglected asynchronous (clockless) logic proved to be a better alternative because of its ability to operate without a clock. In this paper, we presented the design of a 16-to-1 fixed-priority tree arbiter readout circuit for a SPAD array based on asynchronous logic principles. The design of this circuit was explained in detail and supported by simulation results. The manufactured chip was tested, and the experimental results showed that it is possible to record up to 333 million events per second; no reading errors were detected during the data extraction test.

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Shin, Ziho, Myeong-Hoon Oh, Jeong-Gun Lee, Hag Young Kim, and Young Woo Kim. "Design of a clockless MSP430 core using mixed asynchronous design flow." IEICE Electronics Express 14, no. 8 (2017): 20170162. http://dx.doi.org/10.1587/elex.14.20170162.

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3

SAITO, Hiroshi. "Techniques for Asynchronous Circuit Design." IEICE ESS FUNDAMENTALS REVIEW 3, no. 3 (2009): 64–70. http://dx.doi.org/10.1587/essfr.3.3_64.

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4

Oh, Myeong-Hoon. "Architectural Design Issues in a Clockless 32 Bit Processor Using an Asynchronous HDL." ETRI Journal 35, no. 3 (June 1, 2013): 480–90. http://dx.doi.org/10.4218/etrij.13.0112.0598.

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5

Harris, M. S. "Asynchronous circuit design for VLSI signal processing." Microelectronics Journal 25, no. 7 (October 1994): 604. http://dx.doi.org/10.1016/0026-2692(94)90050-7.

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6

Zhou, Liang, Scott Smith, and Jia Di. "Radiation Hardened NULL Convention Logic Asynchronous Circuit Design." Journal of Low Power Electronics and Applications 5, no. 4 (October 20, 2015): 216–33. http://dx.doi.org/10.3390/jlpea5040216.

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7

Ghavami, Behnam, and Hossein Pedram. "Low power asynchronous circuit back-end design flow." Microelectronics Journal 42, no. 2 (February 2011): 462–71. http://dx.doi.org/10.1016/j.mejo.2010.12.001.

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8

Shiroie, Masoud, and Karim Mohammadi. "Optimized Asynchronous Circuit Design based on Evolutionary Algorithm." International Journal of Computer Applications 40, no. 4 (February 29, 2012): 1–6. http://dx.doi.org/10.5120/5029-7177.

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9

Kim, Kyung Ki. "Asynchronous Circuit Design Combined with Power Switch Structure." Journal of the Korea Industrial Information Systems Research 21, no. 1 (February 29, 2016): 17–25. http://dx.doi.org/10.9723/jksiis.2016.21.1.017.

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Di, Jia, Brent A. Bell, William Bouillon, John Brady, Thao Le, Chien-Wei Lo, Liang Men, Spencer Nelson, Francis Sabado, and Andrew Suchanek. "Recent Advances in Low Power Asynchronous Circuit Design." Journal of Low Power Electronics 13, no. 3 (September 1, 2017): 280–97. http://dx.doi.org/10.1166/jolpe.2017.1494.

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11

Bansal, V., A. Nandy, and K. T. Lau. "Design of an asynchronous least common multiple circuit." Microelectronics International 24, no. 1 (January 2, 2007): 4–7. http://dx.doi.org/10.1108/13565360710725874.

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12

Thanh, Toi Le, Lac Truong Tri, and Trang Hoang. "Low power circuit design using NCL based asynchronous method." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 3 (June 1, 2021): 1284. http://dx.doi.org/10.11591/ijeecs.v22.i3.pp1284-1294.

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The null convention logic (NCL) based circuit design methodology eliminates the problems related to noise, clock tree, electromagnetic interference and also reduces significant power consumption. In this paper, we would like to demonstrate the advantage of low power consumption of the NCL based asynchronous circuit design on a large design scale, thus we used the advanced encryption standard (AES) encryption design as an illustrative example. In addition, we also proposed two pipelined AES encryption models using the synchronous circuit design technique and the asynchronous circuit design technique based on NCL. Besides, these two models were realized by using version control system (VCS) tool to simulate and Design Compiler tool to synthesize parameters in power consumption, processing speed and area. The synthesis results of these two models indicated that power consumption of the NCL based asynchronous AES encryption model had a decrease of 71% compared with the synchronous AES encryption model. Moreover, we show the outstanding advantage of the power consumption of the NCL based asynchronous design model (a decrease of 91.12% and 93,23%) compared to the synchronous design model using clock gating technique and without using clock gating technique respectively.

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13

Wu, Rui Zhen, Yin Tang Yang, and Xu Guang Guan. "A Synthesizable Asynchronous Wrapper with Standard Cells." Applied Mechanics and Materials 48-49 (February 2011): 127–30. http://dx.doi.org/10.4028/www.scientific.net/amm.48-49.127.

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A new asynchronous wrapper circuit is proposed based on standard cells for the realization of point to point high speed seamless data transmission. The wrapper is realized from the Signal Transition Graph (STG) by Petrify based on the fundamental GALS system structure. The asynchronous circuit includes the design of synchronous/asynchronous interface and local clock which can be suspended. The traditional EDA tools are merged together with asynchronous circuit design, and the wrapper only has standard cells but not special asynchronous logic gates. The simulation and verification were made by Modelsim and Quartus respectively, and the results have shown that the GALS system works properly and has a preferable performance.

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14

Ghavami, Behnam. "Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 37, no. 3 (May 8, 2018): 1189–203. http://dx.doi.org/10.1108/compel-03-2016-0118.

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Purpose Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits. Design/methodology/approach In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment. Findings Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits. Originality/value The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

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15

YANG, Jung-Lin, Shin-Nung LU, and Pei-Hsuan YU. "Asynchronous Circuit Design on Field Programmable Gate Array Devices." IEICE Transactions on Electronics E95-C, no. 4 (2012): 516–22. http://dx.doi.org/10.1587/transele.e95.c.516.

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16

Yoneda, Tomohiro, Atsufumi Shibayama, and Takashi Nanya. "Verification of asynchronous logic circuit design using process algebra." Systems and Computers in Japan 28, no. 8 (August 1997): 33–43. http://dx.doi.org/10.1002/(sici)1520-684x(199708)28:8<33::aid-scj5>3.0.co;2-m.

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17

Kantabutra, V., and A. G. Andreou. "A state assignment approach to asynchronous CMOS circuit design." IEEE Transactions on Computers 43, no. 4 (April 1994): 460–69. http://dx.doi.org/10.1109/12.278483.

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18

Bailey, Andrew, Ahmad Al Zahrani, Guoyuan Fu, Jia Di, and Scott Smith. "Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power." Journal of Low Power Electronics 4, no. 3 (December 1, 2008): 337–48. http://dx.doi.org/10.1166/jolpe.2008.181.

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19

Lizeth, Gonzalez-Carabarin, Tetsuya Asai, and Masato Motomura. "Asynchronous Digital Circuit Design using Noise-Driven Stochastic Gates." IEICE Proceeding Series 2 (March 17, 2014): 507–10. http://dx.doi.org/10.15248/proc.2.507.

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20

Dinh, Vu Duc Anh. "PAID – A NOVEL FRAMEWORK FOR DESIGN AND SIMULATION OF ASYNCHRONOUS CIRCUITS." Science and Technology Development Journal 14, no. 2 (June 30, 2011): 37–45. http://dx.doi.org/10.32508/stdj.v14i2.1907.

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Contrary to the synchronous circuits, the asynchronous circuits operate with a mechanism of local synchronization (without clock signal). For many years, they showed their relevance with respect to the synchronous circuits thanks to their properties of robustness, low power, low noise and modularity. However, the lack of design methods and associated tools prevents them from being widely spread. This paper deals with a new design methodology for integrated asynchronous circuits and EDA tools. The suggested design method allows on one hand to model circuits in a highlevel language, and on the other hand to generate circuits using only elementary logical gates and Muller gates. This method was prototyped by the development of an EDA design tool for asynchronous circuits. The combination of design methodologies and supporting tools creates a design framework for asynchronous circuits, namely PAiD ("Project of Asynchronous Circuit Design"). This framework allows compilation and synthesis of circuits, described by high-level language ADL ("Asynchronous Description Language"), to generate asynchronous circuits. The result of the synthesizer is a functional netlist of the circuits. This netlist can be then mapped to a specific-technology gate library for asynchronous circuits. During the design process, the circuit can be tested through the simulation process in different levels of abstraction.

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21

Thanh, Toi Le, Lac Truong Tri, and Hoang Trang. "Power Consumption Improvements in AES Decryption Based on Null Convention Logic." International Journal of Circuits, Systems and Signal Processing 15 (April 7, 2021): 254–64. http://dx.doi.org/10.46300/9106.2021.15.29.

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In this paper, we propose a new asynchronous method based on a Null Convention Logic (NCL) to improve power consumption for low power integrated circuits. The reason is because the NCL based designs do not use a clock, it eliminates the problems related to the clock and its power consumption reduces significantly. To show the advantages of the selected method, we propose two design models using the synchronous circuit design method, and the NCL based asynchronous circuit design method. To test these two design models conveniently, we also propose an extra automatic test model. In this study, the AES decryption is used as an example to illustrate both methods. The two above proposed AES decryption models are simulated and synthesized at the various corners by VCS and Design Compiler tool using TSMC standard cell libraries in 65nm technology. The synthesis results of the two above mentioned models indicated that the power consumption of the NCL based asynchronous circuit model is 3 times lower than that of the synchronous circuit model, and significantly improves (from 94% to 98%) compared with the results of the other authors. The processing speed of the NCL based asynchronous circuit paradigm is able to achieve a maximum speed.

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22

Ahn, Jihyuk, and Kyung Ki Kim. "Low Power Reliable Asynchronous Digital Circuit Design for Sensor System." Journal of Sensor Science and Technology 26, no. 3 (May 31, 2017): 209–13. http://dx.doi.org/10.5369/jsst.2017.26.3.209.

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23

LEE, Jeong-Gun. "A Low EMI Circuit Design with Asynchronous Multi-Frequency Clocking." IEICE Transactions on Electronics E97.C, no. 12 (2014): 1158–61. http://dx.doi.org/10.1587/transele.e97.c.1158.

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24

Madalinski, A., A. Bystrov, V. Khomenko, and A. Yakovlev. "Visualisation and resolution of encoding conflicts in asynchronous circuit design." IEE Proceedings - Computers and Digital Techniques 150, no. 5 (2003): 285. http://dx.doi.org/10.1049/ip-cdt:20030831.

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25

Calazans, Ney Laert Vilar, Taciano Ares Rodolfo, and Marcos L. L. Sartori. "Robust and Energy-Efficient Hardware: The Case for Asynchronous Design." Journal of Integrated Circuits and Systems 16, no. 2 (August 19, 2021): 1–11. http://dx.doi.org/10.29292/jics.v16i2.518.

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The current technologies behind the design of semiconductor integrated circuits allow embedding billions of components in a singe silicon die, enabling the construction of very complex circuits in a tiny space, dissipating little energy and producing huge amounts of useful computational work. However, the current levels of integration for electronic components in silicon and similar materials are not easily managed, as parameter variations grow steadily, making the design tasks increasingly challenging. Synchronous techniques have dominated the digital system design landscape for many decades, but their costs are increasingly hard to cope with. Asynchronous design and particularly quasi-delay insensitive design promises to deal with the same challenges more gracefully in current advanced nodes, and possibly irrevocably in future technology nodes. This article proposes a review of the state of the art in using asynchronous circuit design techniques to achieve energy-efficient and robust digital circuit and system design. In particular, the definition of a robust digital circuit comprises addressing several aspects to which a digital system design is expected to be robust to, including: (1) voltage variations; (2) process variations; (3) temperature variations; (4) circuit aging. Besides addressing energy-efficiency and all the mentioned robustness aspects, this work also approaches some of the state-of-the-art tools available to deal with asynchronous design, and points to desirable research development to be conducted in these subjects in the future.

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Lin, Hai Yan, Hai Liu, and Yin Zhao Wang. "Design of Hardware Based on Control Circuit of APF." Applied Mechanics and Materials 148-149 (December 2011): 353–56. http://dx.doi.org/10.4028/www.scientific.net/amm.148-149.353.

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In this paper, we focus on the hardware design of control circuit based on shunt active power filter (APF). It described the AD transformation module, DSP data processing module, CPLD logic control module, man-machine interaction module and asynchronous communication module. As the core controller, TMS320C5416 digital signal processor (DSP) controls this peripheral assistant circuit to complete data acquisition, harmonic detection and output of control signal. Finally, we design the layout and routing of the control circuit.

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Park, Gijin, Jaeduk Han, and Woorham Bae. "Design and Analysis of Asynchronous Sampling Duty Cycle Corrector." Electronics 10, no. 21 (October 24, 2021): 2594. http://dx.doi.org/10.3390/electronics10212594.

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This paper presents a duty cycle correction scheme based on asynchronous sampling and associated settling analysis. The proposed duty cycle corrector circuit consumes less power and area compared to other corrector circuits due to the low-frequency operation of asynchronous sampling. However, the settling behavior of an asynchronous sampling duty cycle corrector is limited in some operation conditions, which degrades its robustness and performance. This paper, therefore, performs analysis on the settling behavior of the asynchronous sampling in various operating conditions and proposes a control scheme to avoid the lagged settling. To verify the proposed duty cycle corrector and its analysis, a prototype design is implemented in a 40-nm CMOS process and its performance is verified by post-layout simulations. The proposed duty cycle corrector achieved very small duty cycle errors (less than 0.8%) and consumed 540 uW per one DCC unit.

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28

Nath, Sagnik, Kurt English, Alexander Derrickson, Andrew Haslam, and John F. McDonald. "An Automatic Placement and Routing Methodology for Asynchronous SFQ Circuit Design." IEEE Transactions on Applied Superconductivity 30, no. 3 (April 2020): 1–10. http://dx.doi.org/10.1109/tasc.2019.2942263.

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KARAKI, N., T. NANMOTO, and S. INOUE. "An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor." IEICE Transactions on Electronics E91-C, no. 5 (May 1, 2008): 721–30. http://dx.doi.org/10.1093/ietele/e91-c.5.721.

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30

Oliveira, Duarte L., Marius Strum, and Sandro S. Sato. "Burst-Mode Asynchronous Controllers on FPGA." International Journal of Reconfigurable Computing 2008 (2008): 1–10. http://dx.doi.org/10.1155/2008/926851.

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FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

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Yang, Hong Cai, and Ming Qing Wu. "NC Processing Network Platform RS-232-C Interface Circuit Design." Advanced Materials Research 529 (June 2012): 29–32. http://dx.doi.org/10.4028/www.scientific.net/amr.529.29.

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RS-232-C and a modem together, the interface can connect all kinds of different types of micro computer, so that they can direct communication. Nowadays more popular FANUC series CNC system, and the machine is equipped with a 25 injection of RS-232-C asynchronous serial communication interface standards, connect the computer and programmer and peripherals. With MAX232 chip design of interface circuit DB9.

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32

Kishore Kumar, A., D. Somasundareswari, V. Duraisamy, and T. Shunbaga Pradeepa. "Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL." VLSI Design 2013 (March 21, 2013): 1–9. http://dx.doi.org/10.1155/2013/157872.

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Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL) is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL) is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

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33

Ryu, Jeong Tak, Won Kee Hong, Byung Ho Kang, and Kyung Ki Kim. "A new interfacing circuit for low power asynchronous design in sensor systems." Journal of the Korea Industrial Information Systems Research 19, no. 1 (February 28, 2014): 61–67. http://dx.doi.org/10.9723/jksiis.2014.19.1.061.

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34

Kim, Kyung Ki. "Delay Insensitive Asynchronous Circuit Design Based on New High-Speed NCL Cells." Journal of the Korea Industrial Information Systems Research 19, no. 6 (December 30, 2014): 1–6. http://dx.doi.org/10.9723/jksiis.2014.19.6.001.

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35

Ghavami, Behnam, Mohsen Raji, Hossein Pedram, and Mehdi B. Tahoori. "Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit." ACM Journal on Emerging Technologies in Computing Systems 9, no. 1 (February 2013): 1–27. http://dx.doi.org/10.1145/2422094.2422098.

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36

Kumawat, Mahesh, Mohit Singh Choudhary, Ravi Kumar, Gaurav Singh, and Santosh Kumar Vishvakarma. "A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application." Journal of Circuits, Systems and Computers 29, no. 07 (September 6, 2019): 2050110. http://dx.doi.org/10.1142/s0218126620501108.

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In the present technology development billions of transistors are fabricated on a single chip, which improves the performance of circuits in terms of high data transmission speed and power consumption. This requirement of data transmission speed is achieved with the help of high-speed transceivers. In this paper, we present a high-speed asynchronous wave-pipelined serializer and deserializer (SerDes) transceiver implemented using current-mode logic (CML). This asynchronous transceiver circuit does not require a clock and therefore it saves large amount of power which is consumed in the phase locked loop (PLL) and frequency synthesizer circuits. Further, the proposed design is built using CML which saves more power. CML circuit operates at relatively higher speed as compared to CMOS circuits which helps the circuit to operate at higher data rate. Compared to conventional CML latch, a novel CML latch is proposed in our design to increase the speed. The circuit is implemented in standard CMOS 65-nm technology. The total power consumed by the serializer and deserializer is 9.32[Formula: see text]mW, which is very less as compared to published related works. The proposed asynchronous SerDes transceiver operates at 18.1-Gbps data transmission rate with low power dissipation.

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37

Shen, Yun, Jian Bo Cao, Xiu Hui Zhu, Xiao Jie Lei, Qiu Ling Ye, Meng Jia Yan, Kang Chen, and Zhao Gao. "Design of Experimental Apparatus for Asynchronous Motor Principle." Key Engineering Materials 620 (August 2014): 341–46. http://dx.doi.org/10.4028/www.scientific.net/kem.620.341.

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Current domestic and international for the experimental apparatus been associated asynchronous motor design generally used hand horseshoe magnet rotates to drive the rotor rotates, While it is possible to achieve, the apparatus is too simple, and the effect is not in great satisfaction. To further improve the experimental results, a new type of asynchronous motor experimental device is designed, whose working mechanism is a DC motor as a driving source, driven by a reduction gear mechanism to produce a rotating magnetic field, the control circuit can be achieved by utilizing the rotational speed and adjust direction. By apparatus of the stator, rotor apparatus, the related motor control and display device design can make the operation more stable, more easily observed. The experimental apparatus can enhance students' awareness and understanding of asynchronous motor, so that the original abstract theory becomes boring incomprehensible gusto, to stimulate students' desire for knowledge, strengthen students' practical knowledge and ability, with higher practical significance. The apparatus simple shaped, with simple and safe operation, is able to facilitate teaching, with better promote the use of value.

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Majidov, Abdullo Sh, and Yury P. Gusev. "METHOD OF ASYNCHRONOUS ENGINES EQUIVALENCY FOR CALCULATING SHORT CIRCUIT CURRENT IN A SYSTEM OF BALANCE-OF-PLANT NEEDS." Vestnik Chuvashskogo universiteta, no. 3 (August 25, 2020): 102–15. http://dx.doi.org/10.47026/1810-1909-2020-3-102-115.

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In short-circuiting in power plants of balance-of-power plant needs three-phase asynchronous motors with a short-closed rotor have a significant influence on the nature of the process and the magnitude of the short circuit current. In the system of balance-of-plant needs it is necessary to take into account the components of short circuit current from asynchronous motors when selecting and checking switches, as well as when selecting and checking current-carrying parts (cables, complete current wires, etc.) not only at the initial moment of the short circuit, but at the time of its shutdown as well. The methods for calculating short circuit current taking into account the influence of asynchronous motors continue to be improved; there is a search for new methods that simplify calculations as much as possible while maintaining the credibility of the results. In doing so, some issues require further study and research, such as the possibility of asynchronous motors equivalency. Power plants have to take into account the components of the short circuit current from a large number of asynchronous engines, which is not only time-consuming, but sometimes impossible due to the absence of full information on engines and mechanisms of balance-of-plant needs. To improve the efficiency and accuracy of calculations for power plant design tasks, it is advisable to replace asynchronous engine groups with equivalents. The relevance of improving the method of equivalency of asynchronous engines at power plants increases along with increasing requirements to enhance the reliability of electrical installations of balance-of-power plant needs and to reduce the costs of technical inventory due to calculation errors. The article considers the method for equivalencing the group of low-voltage asynchronous motors on the example of the balance-of-plant needs system at TPP № 1 located in the town of Dushanbe of the Republic of Tajikistan. Modeling the electromechanical processes caused by short circuits of different electrical remoteness was carried out using ETAP software complex (OTI, USA).

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Xuguang, Guan, Zhou Duan, and Yang Yintang. "Optimization design of a full asynchronous pipeline circuit based on null convention logic." Journal of Semiconductors 30, no. 7 (July 2009): 075010. http://dx.doi.org/10.1088/1674-4926/30/7/075010.

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40

Zhao, Xue Mei. "Realization of Serial Port Expansion Circuit." Applied Mechanics and Materials 271-272 (December 2012): 1597–601. http://dx.doi.org/10.4028/www.scientific.net/amm.271-272.1597.

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This article describes the design of a interface chip with serial port expansion circuit of computer in industrial applications. It is used to connect with 422 and RS232 interfaces. Circuits involved several major chip such as the interface of 422 and RS232 and UART(Universal Asynchronous Receiver Transmitter)16C550 Inside the computer. Paper describes the composition of the hardware circuit, theory and implementation and initialization programming of URAT interface chip. We use interface chip with the FIFO to the circuit, It improves the efficiency of the application software, And it solves the problem of insufficient of computer serial port.

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41

Chen, Jingwen, and Hongshe Dang. "A Novel Two-phase Soft Starter Used for Three-phase Asynchronous Motors." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 13, no. 8 (December 3, 2020): 1175–82. http://dx.doi.org/10.2174/2352096513999200423122430.

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Background: Traditional thyristor-based three-phase soft starters of induction motor often suffer from high starting current and heavy harmonics. Moreover, both the trigger pulse generation and driving circuit design are usually complicated. Methods: To address these issues, we propose a novel soft starter structure using fully controlled IGBTs in this paper. Compared to approaches of traditional design, this structure only uses twophase as the input, and each phase is controlled by a power module that is composed of one IGBT and four diodes. Results: Consequently, both driving circuit and control design are greatly simplified due to the requirement of fewer controlled power semiconductor switches, which leads to the reduction of the total cost. Conclusion: Both Matlab/Simulink simulation results and experimental results on a prototype demonstrate that the proposed soft starter can achieve better performances than traditional thyristorbased soft starters for Starting Current (RMS) and harmonics.

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42

Kıvrak, Sinan, Tolga Özer, and Yüksel Oğuz. "Design and implementation of dspic33fj32mc204 microcontroller–based asynchronous motor voltage/frequency speed control circuit for the ventilation systems of vehicles." Measurement and Control 52, no. 7-8 (July 17, 2019): 1039–47. http://dx.doi.org/10.1177/0020294019858097.

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Direct current motors are used for blower fans as well as for many other systems in vehicles. In this study, it was suggested to use an asynchronous motor instead of the direct current motor for the blower fan. Therefore, an induction motor driver was designed. The purpose of designing this driver was to allow the use of asynchronous motors instead of the brushed direct current motors utilized in automotive ventilation systems. Power and control circuits were designed. A three-phase variable frequency voltage was obtained using an inverter circuit designed with metal-oxide-semiconductor field-effect transistor semiconductor elements from the direct voltage. The voltage/frequency control method was applied to the induction motor. The power circuit was designed using three npn-type and three pnp-type metal-oxide-semiconductor field-effect transistors, in order to reduce the number of independent sources. The direct current motors generally used in automotive ventilation systems have 12 V operating voltage, so the driver was designed to be used in the 12–18 V range. In this study, the alternating current driver was used for a 90 W asynchronous motor and drive at 12 V and 18 V variable input voltage values. The dsPIC33fj32mc204 microcontroller was used to achieve variable frequency and speed control.

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Boldyrev, Alexander. "Energy-efficient inverter circuit for the low-voltage asynchronous driver controller with autonomous power supply." E3S Web of Conferences 279 (2021): 01004. http://dx.doi.org/10.1051/e3sconf/202127901004.

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The design of the energy-efficient inverter circuit for the asynchronous frequency-controlled three-phase electric driver with autonomous low-voltage DC power supply. The components analysis of the electric drive, the main components selection approach: microcontroller, three-phase driver and power transistors. R&D prototype of the energy-efficient inverter circuit was created, characterized by an average consumption current reduced by 5%. Reducing energy losses is achieved by reducing dynamic losses in the power circuits of a low-voltage inverter and using several circuit solutions.

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Zhou, Liang, Ravi Parameswaran, Farhad Parsan, Scott Smith, and Jia Di. "Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology." Journal of Low Power Electronics and Applications 5, no. 2 (May 18, 2015): 81–100. http://dx.doi.org/10.3390/jlpea5020081.

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Almeida, Tiago da Silva, and André Luiz Gomes de Freitas. "Evaluation of Clause-Column Table method to design of MIC hazard-free in asynchronous finite state machines." Academic Journal on Computing, Engineering and Applied Mathematics 1, no. 2 (June 10, 2020): 1–8. http://dx.doi.org/10.20873/uft.2675-3588.2020.v1n2.p1-8.

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Asynchronous finite state machines are of great interest because they use fewer transistors to manufacture them. However, find the minimum resources in logic modeling is an NP-Problem, since the search space increase exponentially. Although this problem is studied for some time, there is still space for newer researches. Mostly, in new computational methods to improve performance in solving logical optimization in finite state machines. Thus, this paper presents a study and evaluation of heuristic algorithms for the optimization of asynchronous finite state machines, to obtain the smallest possible circuit. Thus, the Clause-Column Table and Quine-McCluskey algorithms are combined in order to propose an algorithm capable of minimizing asynchronous sequential circuits. Tests and results show that it is possible to synthesize circuits in a reasonable time, but with some logical errors. It may be concluded that it still needs research, even though it is not such a recent line of research.

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Poudel, Bikash, Arslan Munir, Joonho Kong, and Muazzam A. Khan. "Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem." Journal of Low Power Electronics and Applications 11, no. 4 (November 12, 2021): 43. http://dx.doi.org/10.3390/jlpea11040043.

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The elliptic curve cryptosystem (ECC) has been proven to be vulnerable to non-invasive side-channel analysis attacks, such as timing, power, visible light, electromagnetic emanation, and acoustic analysis attacks. In ECC, the scalar multiplication component is considered to be highly susceptible to side-channel attacks (SCAs) because it consumes the most power and leaks the most information. In this work, we design a robust asynchronous circuit for scalar multiplication that is resistant to state-of-the-art timing, power, and fault analysis attacks. We leverage the genetic algorithm with multi-objective fitness function to generate a standard Boolean logic-based combinational circuit for scalar multiplication. We transform this circuit into a multi-threshold dual-spacer dual-rail delay-insensitive logic (MTD3L) circuit. We then design point-addition and point-doubling circuits using the same procedure. Finally, we integrate these components together into a complete secure and dependable ECC processor. We design and validate the ECC processor using Xilinx ISE 14.7 and implement it in a Xilinx Kintex-7 field-programmable gate array (FPGA).

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Bouesse, Fraidy, M. Renaudin, and Fabien Germain. "Asynchronous AES Crypto-Processor Including Secured and Optimized Blocks." Journal of Integrated Circuits and Systems 1, no. 1 (November 16, 2004): 5–13. http://dx.doi.org/10.29292/jics.v1i1.249.

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This paper presents the first study of an asynchronous AES architecture compliant with the NIST standard. It exploits the fundamental properties of quasi delay insensitive asynchronous circuits. First, 1 to N encoding is extensively used in order to minimize hardware cost, thus optimizing area and speed. Most importantly, it is shown how the quasi delay insensitive logic style gives the opportunity to design balanced architectures, particularly well suited to improve differential power analysis resistance. Indeed, the proposed design methodology enables the generation of logic circuits which always involve a constant number of logical transitions, independently of data values processed by the circuit. Based on a 32-bit data-path, a balanced and optimized QDI asynchronous architecture of the AES is described. In addition, several architecture trade-offs are considered, and their area and speed estimated. Simulation results show that with the proposed design approach, throughputs ranging from 36 Mbit/s to more than 569 Mbit/s can be achieved, well suited to target smart-card applications.

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Y. N., Sharath Kumar, and Dinesha P. "TFI-FTS: An efficient transient fault injection and fault-tolerant system for asynchronous circuits on FPGA platform." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 3 (June 1, 2021): 2704. http://dx.doi.org/10.11591/ijece.v11i3.pp2704-2710.

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Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the faults based on BMA based LFSR with faulty logic insertion and one hot encoded register. The BMA based LFSR reduces the hardware complexity with less power consumption on-chip than standard LFSR method. The FTS uses triple mode redundancy (TMR) based majority voter logic (MVL) to tolerant the faults for asynchronous circuits. The benchmarked 74X-series circuits are considered as an asynchronous circuit for TMR logic. The TFI-FTS module is modeled using Verilog-HDL on Xilinx-ISE and synthesized on hardware platform. The Performance parameters are tabulated for TFI-FTS based asynchronous circuits. The performance of TFI-FTS Module is analyzed with 100% fault coverage. The fault coverage is validated using functional simulation of each asynchronous circuit with fault injection in TFI-FTS Module.

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Jiang, Xiang Ju, and Er Lin Liu. "Design of Matrix Converter Vector Control System Based on DSP and CPLD." Advanced Materials Research 413 (December 2011): 184–89. http://dx.doi.org/10.4028/www.scientific.net/amr.413.184.

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Matrix converter is a kind of power electric converter by AC-AC transformation with its excellent input and output characteristics.After analysis of matrix converter system structure in the paper,a digital signal processor based on DSP and CPLD is designed. The design includes the hardware structure and the program flowsheet.DSP and CPLD is the core of the matrix converter - Asynchronous motor vector control system, including system main circuit, other peripheral hardware circuit, control and protection circuits, software design process and so on. The hardware control strategy and software realization scheme of the system are discussed in detail. The experimental results verify that the control strategy of the system is valid and the design of the software and hardware are reasonable.

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Zhou, Shao Qing, Cong Li Mei, Guo Hai Liu, Wen Tao Huang, and Dong Xin Shu. "ARM-Based Speed Regulating System for Asynchronous Motor." Advanced Materials Research 852 (January 2014): 686–91. http://dx.doi.org/10.4028/www.scientific.net/amr.852.686.

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Owing to their simple structure and stability, AC induction motors have been widely used in many fields. With the development of electronic devices, variable-frequency speed regulation system of the induction motor is widely used. This paper introduces an ARM chip controller LM3S818 from Texas Instruments in detail as a microprocessor of the variable frequency speed regulation system for asynchronous motor. The main circuit of AC-DC-AC Variable frequency way is adopted and the control system is based on Space Vector Pulse Width Module. The hardware structure and the design of software both are presented. And experimental results show the good performance in different frequency.

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