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Dissertations / Theses on the topic 'Background calibration'
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Crasso, Anthony. "Background Calibration of a 6-Bit 1Gsps Split-Flash ADC." Digital WPI, 2013. https://digitalcommons.wpi.edu/etd-theses/54.
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In this MS thesis, a redundant flash analog-to-digital converter (ADC) using a ``Split-ADC' calibration structure and lookup-table-based correction is presented. ADC input capacitance is minimized through use of small, power efficient comparators; redundancy is used to tolerate the resulting large offset voltages. Correction of errors and estimation of calibration parameters are performed continuously in the background in the digital domain. The proposed flash ADC has an effective-number-of-bits (ENOB) of 6-bits and is designed for a target sampling rate of 1Gs/s in 180nm CMOS. The calibration algorithm described has been simulated in MATLAB and an FPGA implementation has been investigated.
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Kalousis, Leonidas. "Calibration of the Double Chooz detector and cosmic background studies." Phd thesis, Université de Strasbourg, 2012. http://tel.archives-ouvertes.fr/tel-00979573.
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Double Chooz is a short-baseline experiment, located at the Chooz power plant, designed to observe the neutrino oscillation signal controlled by the θ13 mixing angle. Part of my scientific research, as a graduate student, was directed towards the development of the software needed for the calibration of the Double Chooz Inner Veto and the analysis of the data associated with this task. I was responsible for the quality tests performed in every photomultiplier prior to its installation. I completed all the necessary measurements and analysed the data, extracting the first set of gains and determining the nominal high voltage values needed to be applied in all photomultipliers. All this information served as valuable input to the detector configuration. I was also responsible for the Inner Veto photomultiplier gain analysis during the first months of data taking. I was also very actively involved in data analysis and the estimations of the various sources of background. I initiated a number of methods to isolate and study the cosmic muon events that activate the detector. Additionally I worked on the estimation of the fast neutron rate registered in the detector. The techniques I put forward played a key role and were used in the first Double Chooz publication. Finally, I developed a set of algorithms to identify and reject an instrumental background, relevant for the Double Chooz detector using topological information of the deposited charge.
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Chang, Albert Hsu Ting. "Low-power high-performance SAR ADC with redundancy and digital background calibration." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/82177.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (p. 195-199).
As technology scales, the improved speed and energy eciency make the successive- approximation-register (SAR) architecture an attractive alternative for applications that require high-speed and high-accuracy analog-to-digital converters (ADCs). In SAR ADCs, the key linearity and speed limiting factors are capacitor mismatch and incomplete digital-to-analog converter (DAC)/reference voltage settling. In this the- sis, a sub-radix-2 SAR ADC is presented with several new contributions. The main contributions include investigation of using digital error correction (redundancy) in SAR ADCs for dynamic error correction and speed improvement, development of two new calibration algorithms to digitally correct for manufacturing mismatches, design of new architecture to incorporate redundancy within the architecture itself while achieving 94% better energy eciency compared to conventional switching algorithm, development of a new capacitor DAC structure to improve the SNR by four times with improved matching, joint design of the analog and digital circuits to create an asynchronous platform in order to reach the targeted performance, and analysis of key circuit blocks to enable the design to meet noise, power and timing requirements. The design is fabricated in standard 1P9M 65nm CMOS technology with 1.2V supply. The active die area is 0.083mm² with full rail-to-rail input swing of 2.4V p-p . A 67.4dB SNDR, 78.1dB SFDR, +1.0/-0.9 LSB₁₂ INL and +0.5/-0.7 LSB₁₂ DNL are achieved at 50MS/s at Nyquist rate. The total power consumption, including the estimated calibration and reference power, is 2.1mW, corresponding to 21.9fJ/conv.- step FoM. This ADC achieves the best FoM of any ADCs with greater than 10b ENOB and 10MS/s sampling rate.
by Albert Hsu Ting Chang.
Ph.D.
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Li, Sulin. "A Highly Digital VCO-Based ADC With Lookup-Table-Based Background Calibration." Digital WPI, 2019. https://digitalcommons.wpi.edu/etd-dissertations/556.
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CMOS technology scaling has enabled dramatic improvement for digital circuits both in terms of speed and power efficiency. However, most traditional analog-to-digital converter (ADC) architectures are challenged by ever-decreasing supply voltage. The improvement in time resolution enabled by increased digital speeds drives design towards time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The main challenge in VCO-based ADC design is mitigating the nonlinearity of VCO Voltage-to-frequency (V-to-f) characteristics. Achieving signal-to-noise ratio (SNR) performance better than 40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. This dissertation proposes a highly digital, reconfigurable VCO-based ADC with lookup-table (LUT) based background calibration based on "split ADC" architecture. Each of the two split channels, ADC "A" and "B", contains two VCOs in a differential configuration. This helps alleviate even-order distortions as well as increase the dynamic range. A digital controller on chip can reconfigure the ADCs' sampling rates and resolutions to adapt to various application scenarios. Different types of input signals can be used to train the ADC’s LUT parameters through the simple, anti-aliasing continuous-time input to achieve target resolution. The chip is fabricated in a 180 nm CMOS process, and the active area of analog and digital circuits is 0.09 and 0.16mm^2, respectively. Power consumption of the core ADC function is 25 mW. Measured results for this prototype design with 12-b resolution show ENOB improves from uncorrected 5-b to 11.5-b with calibration time within 200 ms (780K conversions at 5 MSps sample rate).
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Delic-Ibukic, Alma. "Digital Background Calibration Techniques for High-Resolution, Wide Bandwidth Analog-to-Digital Converters." Fogler Library, University of Maine, 2008. http://www.library.umaine.edu/theses/pdf/Delic-IbukicA2008.pdf.
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Shu, Yun-Shiang. "Background digital calibration techniques for high-speed, high resolution analog-to-digital data converters." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2008. http://wwwlib.umi.com/cr/ucsd/fullcit?p3289085.
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Thesis (Ph. D.)--University of California, San Diego, 2008.Title from first page of PDF file (viewed Feb. 5, 2008). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 106-111).
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David, Christopher Leonidas. "All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-dissertations/194.
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The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
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Bauermeister, Boris [Verfasser]. "Studies of calibration and electron recoil background modelling for the XENON100 dark matter experiment / Boris Bauermeister." Mainz : Universitätsbibliothek Mainz, 2017. http://d-nb.info/1122763220/34.
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Edelstein, Andrea. "Background substraction methods for online calibration of baseline received signal strength in radio frequency sensing networks." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106414.
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Radio frequency (RF) sensing networks are a class of wireless sensor networks (WSNs) which use RF signals to carry out tasks such as tomographic imaging, tomographic target tracking and node localization. While a wide variety of such algorithms exist, they often assume access to measurements of the baseline received signal strength (RSS) on each link, i.e, to measurements taken during some offline calibration period when no temporary obstructions are located near the nodes which form the network. However, in many cases, WSNs are designed to be deployed and used on the fly, and it can be impossible to ensure the network is empty of obstructions long enough to obtain the required calibration data. For instance, an RF sensing network could be set up around a burning building to image its interior and determine if people are trapped inside. There is no way to ask these people to first leave the area while the baseline RSS values are collected. Thus far, no research has addressed the question of whether it is possible to estimate baseline RSS values without access to a calibration period. We propose adapting background subtraction methods from the fields of computer vision and image processing in order to estimate baseline RSS values from measurements taken while the system is online and obstructions may be present in the network. This is done by forming an analogy between the intensity of a background pixel in an image and the baseline RSS value of a link in a WSN. We also translate the concepts of temporal similarity, spatial similarity and spatial ergodicity which underlie three specific background subtraction algorithms--background subtraction with temporal background modelling, foreground-adaptive background subtraction and foreground-adaptive background subtraction with Markov modelling of change labels--to the domain of WSNs in order to use these algorithms to determine the baseline RSS. By applying these techniques to experimental data, we show that they are capable of accurately estimating baseline RSS values in a range of different environments. We also show that these estimates are close enough to the actual values of the baseline RSS to allow for RF tomographic tracking to be carried out without the need to resort to a calibration period.Les réseaux de capteurs à radiofréquences sont une classe de réseau de capteurs sans fil qui utilisent des signaux radioélectriques pour accomplir de nombreuses tâches comme l'imagerie tomographique, la poursuite tomographique de cibles, la localisation des noeuds, etc. Même s'il existe une grande variété de ces algorithmes, la plupart assument que des niveaux de référence pour la force du signal entre deux noeuds peuvent être obtenus pendant une période d'étalonnage différée, c'est-à-dire quand il n'y a aucun obstacle temporaire près des noeuds du réseau. Toutefois, les réseaux de capteurs sans fil sont conçus pour être déployés et utilisés de façon ad hoc, ce qui rend parfois impossible l'évacuation des obstacles pour que ces niveaux de référence puissent être mesurés. Par exemple, un réseau de capteurs à radiofréquence peut être installé autour d'un bâtiment en feu, et l'imagerie tomographique peut être utilisée pour déterminer si quelqu'un est piégé à l'intérieur. Évidemment, il est irréaliste de demander aux personnes de quitter la région en premier lieu pendant qu'on établit les niveaux de référence. Jusqu'à présent, la recherche existante ne s'est pas penchée sur la possibilité d'estimer ces niveaux de référence sans période d'étalonnage. Nous proposons d'adapter la méthode de soustraction de l'arrière-plan -- algorithme créé à l'origine pour la vision artificielle et pour le traitement des images -- pour estimer les niveaux de référence pour la force du signal en utilisant des mesures prises quand le système est en ligne et quand on retrouve possiblement des obstacles dans les environs du réseau. Cette adaptation consiste, entre autres, à former une relation entre l'intensité d'un pixel arrière-plan et le niveau de référence de la force du signal sur une liaison d'un réseau de capteurs sans fil. Nous adaptons aussi les concepts de la similarité temporelle, de la similarité spatiale et de l'ergodicité spatiale qui sous-tendent trois méthodes de soustraction de l'arrière-plan en vue de les utiliser pour trouver les niveaux de référence de la force du signal. Avec ces techniques, nous montrons que nous sommes capables d'estimer les niveaux de référence de la force du signal dans plusieurs environnements différents. Nous montrons aussi que ces estimations sont assez précises pour que la poursuite tomographique de cible puisse être effectuée sans avoir besoin d'une période d'étalonnage.
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Keane, John Patrick. "Background digital calibration for interstage gain errors and memory effects in pipelined analog-to-digital converters /." For electronic version search Digital dissertations database. Restricted to UC campuses. Access is free to UC campus dissertations, 2004. http://uclibs.org/PID/11984.
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Noncolela, Sive Professor. "Calibration of a NaI (Tl) detector for low level counting of naturally occurring radionuclides in soil." University of the Western Cape, 2011. http://hdl.handle.net/11394/5426.
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>Magister Scientiae - MScThe Physics Department at the University of the Western Cape and the Environmental Physics group at iThemba labs have been conducting radiometric studies on both land and water. In this study a 7.5 cm X 7.5 cm NaI (Tl) detector was used to study activity concentrations of primordial radionuclides in soil and sand samples. The detector and the sample were placed inside a lead castle to reduce background in the laboratory from the surroundings such as the wall and the floor. The samples were placed inside a 1 L Marinelli beaker which surrounds the detector for better relative efficiency as almost the whole sample is exposed to the detector. Additional lead bricks were placed below the detector to further reduce the background by 20%. The NaI detector is known to be prone to spectral drift caused by temperature differences inside and around the detector. The spectral drift was investigated by using a ¹³⁷Cs source to monitor the movements in the 662 keV peak. The maximum centroid shift was about 4 keV (for a period of 24 hours) which is enough to cause disturbances in spectral fitting. There was no correlation between the centroid shift and small room temperature fluctuations of 1.56 ºC. A Full Spectrum Analysis (FSA) method was used to extract the activity concentrations of ²³⁸U, ²³²Th and ⁴⁰K from the measured data. The FSA method is different from the usual Windows Analysis (WA) as it uses the whole spectrum instead of only putting a ‘window’ around the region of interest to measure the counts around a certain energy peak. The FSA method uses standard spectra corresponding to the radionuclides being investigated, and is expected to have an advantage when low-activity samples are measured. The standard spectra are multiplied by the activity concentrations and then added to fit the measured spectrum. Accurate concentrations are then extracted using a chi-squared (χ²) minimization procedure. Eight samples were measured in the laboratory using the NaI detector and analyzed using the FSA method. The samples were measured for about 24 hours for good statistics. Microsoft Excel and MATLAB were used to calculate the activity concentrations. The ²³⁸U activity concentration values varied from 14 ± 1 Bq/kg (iThemba soil, HS6) to 256 ± 10 Bq/kg (Kloof sample). The ²³²Th activity concentration values varied from 7 ± 1 Bq/kg (Anstip beach sand) to 53 ± 3 Bq/kg (Rawsonville soil #B31). The ⁴⁰K activity concentration values varied from 60 ± 20 Bq/kg (iThemba soil, HS6) to 190 ± 20 Bq/kg (Kloof sample). The χ² values also varied from sample to sample with the lowest being 12 (Anstip beach sand) and the highest (for samples without contamination of anthropogenic nuclei) being 357 (Rawsonville soil #B28). A high χ² value usually represents incomplete gain drift corrections, improper set of fitting functions, proper inclusion of coincidence summing or the presence of anthropogenic (man made) radionuclei in the source [Hen03]. Activity concentrations of ⁴⁰K, ²³²Th and ²³⁸U were measured at four stationary points on the Kloof mine dump. The fifth stationary point was located on the Southdeep mine dump. These measurements were analysed using the FSA method and fitting by "eye" the standard spectra to the measured spectra using Microsoft Excel. These values were then compared to values obtained using an automated minimization procedure in MATLAB. There was a good correlation between these results except for ²³²Th which had higher concentrations when MATLAB was used, where 16 Bq/kg was the average value in Excel and 24 Bq/kg was the average value in MATLAB.
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Pham, Long. "Lookup-Table-Based Background Linearization for VCO-Based ADCs." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-theses/586.
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Scaling of CMOS to nanometer dimensions has enabled dramatic improvement in digital power efficiency, with lower VDD supply voltage and decreased power consumption for logic functions. However, most traditionally prevalent ADC architectures are not well suited to the lower VDD environment. The improvement in time resolution enabled by increased digital speeds naturally drives design toward time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The major obstacle in the VCO-based technique is linearizing the VCO voltage-to-frequency characteristic. Achieving signal-to-noise (SNR) performance better than -40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. A further challenge is implementing calibration without degrading energy efficiency performance. This thesis project discusses a complete design of a 10 bit three stage ring VCO-based ADC. A lookup-table (LUT) digital correction technique enabled by the "Split ADC" calibration approach is presented suitable for linearization of the ADC. An improvement in the calibration algorithm is introduced to ensure LUT continuity. Measured results for a 10 bit 48.8-kSps ADC show INL improvement of 10X after calibration convergence.
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Hasterok, Constanze [Verfasser], and Manfred [Akademischer Betreuer] Lindner. "Gas Purity Analytics, Calibration Studies, and Background Predictions towards the First Results of XENON1T / Constanze Hasterok ; Betreuer: Manfred Lindner." Heidelberg : Universitätsbibliothek Heidelberg, 2017. http://d-nb.info/1177688727/34.
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Bravo, Berguno David. "Precision Background Stability and Response Calibration in Borexino: Prospects for Wideband, Precision Solar Neutrino Spectroscopy and BSM Neutrino Oscillometry Through a Deeper Detector Understanding." Diss., Virginia Tech, 2016. http://hdl.handle.net/10919/73581.
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This work sets out to be a description of the initiatives utilizing the Borexino liquid scintillator neutrino observatory to perform the first direct, high-precision, wideband solar neutrino spectroscopy measurement of the the solar neutrino spectrum's main components, as well as its next-generation short-baseline source program (SOX). Its original scope revolved around the creation of a O(MCi) ⁵¹Cr source to be inserted under the detector, intended to explore the small region of the anomaly-favored sin²θ₁₄/Δm₁₄² phase space where sterile neutrinos may lie -or otherwise unambiguously measure or disprove signs of anomalous oscillatory behavior in low L/E electron-neutrinos and antineutrinos. Investigating the feasibility and optimization of producing such a large amount of ⁵¹Cr for the source, by irradiating chromium material in a high-flux reactor, required extensive simulative work with the MCNP-5 neutronics code.
With the switch of pace toward a ¹⁴Ce-¹⁴⁴Pr electron-antineutrino source, this work was re-oriented toward the efforts to re-calibrate the detector after the 2009-10 campaign, improving and expanding upon it by the introduction of new source fabrication techniques, a source positioning LED device, and a re-evaluation of the objectives sought after, fitting the needs of Borexino's Phase 2 priorities. Indeed, the detector's unprecedented and record-setting background levels are tightening its requirement for background stability. Aiming to reduce fluctuations in 210Po levels that remain problematic in Borexino's quest to lower the upper limit of the solar CNO neutrino flux (or even measure it), among other components, a new Temperature Monitoring and Management System was deployed and associated tools necessary to fully utilize it were developed as part of the present work. Computational Fluid Dynamics (CFD) simulations in 2D and 3D, conductive and fully convective, were also developed in collaboration with Dr Riccardo Mereu of Milan's Polytechnic Institute in order to model, characterize and ultimately predict the subtle fluid currents (around 10⁻⁷) m/s) that may be of concern for the required background stability. A brief discussion of the recent >5sigma measurement of geo-neutrinos by Borexino, a complementary part of the work for this thesis, is presented as well.Ph. D.
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Gendreau, Keith Charles. "X-ray CCDs for space applications : calibration, radiation hardness, and use for measuring the spectrum of the cosmic X-ray background." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/38053.
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Filliard, Clement. "Etude de la calibration et de la reconstruction des cartes du ciel avec les données Planck-HFI." Thesis, Paris 11, 2012. http://www.theses.fr/2012PA112126.
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Shaikh, Nabila. "Energy Calibration of the Tile L1Calo and Data Driven Estimation of Non-prompt $e$, $\mu$ and $\tau$ Background Using Data From the ATLAS Detector." Licentiate thesis, Stockholms universitet, Fysikum, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:su:diva-156377.
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Pestel, Valentin. "Détection de neutrinos auprès du réacteur BR2 : analyse des premières données de l'expérience SoLid." Thesis, Normandie, 2019. http://www.theses.fr/2019NORMC238.
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L'expérience SoLid (Search for Oscillations with a Lithium-6 detector) mesure le flux d'anti-neutrino à proximité d'un réacteur de recherche (BR2, SCK-CEN, Belgique). Le premier objectif est de sonder l'anomalie "réacteur" et de tester l'hypothèse de l'existence de neutrino(s) stérile(s) "léger(s)" (Delta m2~1eV2). En second lieu, la mesure du spectre en énergie des neutrinos induit par la fission de l'uranium 235 offrira de nouvelles contraintes. Le détecteur d'une masse de 1,6 tonne, segmenté en 12800 cubes de détection de 5x5x5 cm3, repose sur une nouvelle technologie basée sur l'utilisation de deux scintillateurs (PVT et ZnS) luent par des MPPCs.Après une mise en contexte de l'expérience et une description détaillée du détecteur, ce manuscrit décrit la procédure mise en place pour caractériser ce dernier lors de sa construction. La reconstruction des données et l'identification des interactions seront ensuite présentées. La partie suivante décrit les procédures de calibration du détecteur, se focalisant tout particulièrement sur l'évaluation de l'efficacité de détection neutron. Enfin sera décrit une première analyse permettant de valider la compréhension du bruit de fond et d'extraire le signal anti-neutrinoSoLid (Search for Oscillations with a Lithium-6 detector) is a very short baseline (≺10 m) "reactor anti-neutrino" experiment which takes data at the BR2 nuclear reactor (SCK-CEN, Belgium). The first goal is to probe the "reactor" anomaly and to test the hypothesis of the existence of "light" sterile neutrino(s) (Delta m2 ~ 1eV2). Secondarily, the measurement of the neutrino energy spectrum induced by the fission of 235U will provide new constraints. The 1.6 ton detector, segmented into 12800 detection cells of 5x5x5 cm3, is based on a new technology using two scintillators (PVT and ZnS) read by MPPCs. After contextualizing the experiment and describing the detector, this manuscript describes the procedure to characterize the detector during its construction.Than, data reconstruction and events identification will be presented. The following part describes the calibration procedures, focusing on the evaluation of neutron detection efficiency. Finally, a first analysis will validate the understanding of backgrounds and will extract the anti-neutrino signal
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Vinsonneau, Emile. "La qualité d'image dans le contexte de la numérisation de livres anciens." Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0057/document.
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L'objectif de cette thèse est de proposer des méthodes ou des outils de calibration permettant d'améliorer la qualité d'image dans le cadre de la numérisation de livres anciens.Le premier chapitre concerne la mise en oeuvre d'un "scanner sans éclairage". Ce scanner est matriciel et il ne contrôle pas la lumière via un éclairage artificiel. L'objectif du projet est de pouvoir corriger, par calibration ou par la mise en place d'un traitement d'image les défauts d'éclairage apparaissant sur le document. Nous verrons dans un premier chapitre les solutions possibles pour y répondre. Nous y proposerons également un moyen de segmenter le fond du document en se basant sur des pixels caractérisants le fond du document. Ce résultat permettra de reconstruire le fond puis de corriger les non-uniformités.Le deuxième chapitre concerne la mise en place d'un contrôle qualité de numérisation de livres anciens. Effectivement, la manipulation du matériel dans le contexte de la numérisation industrielle engendre des erreurs possibles de réglage. De ce fait, nous obtenons une numérisation de moindres qualités. Le contrôle se focalisera sur le flou de focus qui est le défaut le plus présent. Nous proposons dans ce chapitre de combiner différentes approches du problème permettant de le quantifier. Nous verrons que la combinaison de ces informations permet d'estimer avec précision la qualité de netteté de l'image.Le troisième chapitre évoque les problématiques de la gestion de la couleur. Pour avoir une homogénéité colorimétrique entre tous les appareils, il est indispensable que la calibration soit inférieure à un seuil visuel. Les contraintes industrielles ont de nombreux critères et il est difficile de tous les respecter. L'objectif de ce chapitre est de récapituler comment mettre en place un système permettant de calibrer la couleur avec toutes ces contraintes. Puis, il s'agit de comprendre comment créer une transformation entre l'espace de couleur de l'appareil et l'espace de couleur de connexion (l'espace L*a*b*). Nous verrons que la solution de ce problème se résout par une régression polynomiale dont le degré du polynôme varie en fonction du nombre de mesures faite sur la mire colorimétriqueThe goal of this thesis is to add some tools in order to upgrade image quality when scanning with book digitization.First Chapter talks about image scanner whitout lighting control. This problem focuses to document camera. The goal is to correct lighting. We will see some corrections and we will suggest our method. For this part, we detect pixel's background document and we will rebuild the background of the image by them. With this information, we can correct lighting.Second chapter presents some way to do quality control after digitization, specially out of focus problem. We will enumerate different point of view to analyse and to estimate this information. To validate descriptors, we suggest to blur any picture and to compute blur estimation in order to evaluate precision. After that, we propose to combinate descriptors by machine learning.Third chapter mentions color management problem. Every image devices need to be calibrated. This chapter will expose how to calibrate scanner and explain it. We will see that L*a*b* color space is the connection profil space. To calibrate color, we must transform scanner color space to L*a*b*. We will see, in order to convert information, solution depends color chart used but we show a link between the function and thenumber of patch
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Milward, Stephen Richard. "XUV calibrations and electron background reduction for the ROSAT Wide Field Camera." Thesis, University of Leicester, 1986. http://hdl.handle.net/2381/35732.
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The ROSAT Wide Field Camera (WFC) is an imaging experiment, conducted by a consortium of UK groups, intended to perform the first all sky survey in the XUV wavelength band (6-30nm). As part of the development and flight programmes, XUV calibration and background simulation work has been undertaken at Leicester. Here, the commissioning and development of an XUV line source and monochromator is described and their use to produce a laboratory detector standcird is reported. Subsequent efficiency calibration of a Csl coated prototype WFC MicroChannel plate detector is reported and the results shown to be in substantial agreement with a published model of photocathode behaviour. The results fill a gap in the published data between 11.2 and 25.6nm. Reflectivity measurements on the Wolter-Schwtirzschild Type 1 grazing incidence mirrors are reported and compared with the predictions of theory and with published measurements on test flats. Differences between theoretical reflectivities and the empirical results of up to 15% axe shown to be consistent with either: low density reflective gold coating, hydrocarbon contamination, or errors in the optical constants assumed for gold. Measurements were found to be broadly in agreement with published results. In addition to experimental work, the impact of the orbital low energy electron background is assessed on WFC performance and shown to be limiting due to the inclination of the spacecraft orbit. Reduction of this background is shown, by computer simulation, to be feasible by the introduction of a magnetic screen. Preliminary electron beam tests support this view.
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Fan, Jen-Lin, and 范振麟. "Digital Background Calibration of Pipelined ADCs." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/93826889242428702709.
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博士國立交通大學
電子工程系所
97
Following the progress of advanced technology, the channel length of MOS transistor is smaller and the parasitic is also reduced. These characteristics make the transistor be able to be operated in higher frequency and lower power dissipation. However, the output impedance of MOS transistor reduces with the channel length. In addition to the output impedance, the thickness of gate oxide also becomes thinner than a long channel device. For device reliability issue, supply voltage scales down with channel length. The reduced output impedance and supply voltage make analog circuits can not be designed with high gain and large dynamic range. These features make the design of high performance analog circuits more difficult.\\ Voltage-mode switched-capacitor (SC) pipelined ADC is widely used. This circuit is operated with high gain operation amp (opamp) and configures in negative feedback. The negative feedback circuit can achieve high linearity and high accuracy at the same time. However, with capacitor mismatch and finite opamp's dc gain, the output of a pipelined ADC may contain servere nonlinearity. The capacitor matching with present CMOS technology can be used to design a pipelined ADC with 10-12 bit resolution. But it's hard to design a high gain opamp with high unit-gain frequency in deep-submicron technology. The main purpose of this thesis is to design a high performance pipelined ADC in deep-submicron technology.\\ This thesis presents a background calibration scheme for pipelined analog-to-digital converters (ADCs) that is robust. For a SC pipeline stage, by splitting its input sampling capacitor, a random sequence can be injected into the ADC's signal path, and then calibration data can be extracted from the ADC's digital output without interrupting its normal conversion operation. Using an input-dependent scheme to generate the calibration random sequence, no additional signal range is required to accommodate the extra calibration signal.\\ A 32-mW 12-bit 80-MS/s pipelined ADC was fabricated using a 65~nm CMOS technology. The ADC demonstrates a new digital background technique, which corrects pipeline stage nonlinearity as well as gain and sub-DAC errors. The proposed technique is robust and immune to device mismatches, and does not need extra signal range. Since the accuracy and linearity requirements are mitigated, analog circuits with less complexity and power can be used. The ADC achieves 67~dB SNDR and 81~dB SFDR at 80~MS/s sampling rate with a 2~MHz sinewave input. \\ In addition, a split-channel ADC architecture is proposed to reduce the calibration time. The split-channel ADC consists of two A/D channels that receive the same analog input but employ different random sequences for calibration. The calibration time can be greatly reduced by comparing the digital outputs from both channels and then removing the embedded perturbations before extracting the calibration data. The proposed calibration techniques are analyzed by using both theoretical formulation and system-level simulation.
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Liu, Hung Chih, and 劉鴻志. "Background Calibration Techniques for Pipelined Analog-to-Digital Converters." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/93715028452376668231.
Full textAbstract:
博士國立交通大學
電子工程系所
94
The rapid growth of DSP-based signal processing equipments prompted a need for a analog-to-digital converter (ADC) with higher conversion rates and higher resolutions. Since quantization of continuous amplitude information requires analog operations, ADCs often limit the throughput of DSP based systems. Pipelined ADCs have been shown to work at very high speeds but their resolution is limited by component mismatches, operational amplifier (opamp) finite gain, offsets, charge injection errors and component non-linearity. Self calibration and background calibration techniques have been developed to correct for these non-linearities. Digital self-calibration is a very promising technique to improve the accuracy of switched capacitor based pipeline ADCs. The most attractive feature of digital self-calibration is the minimum extra analog circuit involved. Thus, analog precision problems are translated into the complexity of digital signal processing circuits, allowing this approach to benefit from CMOS device scaling. Digital self-calibration has the advantage of low complexity and high accuracy, most implementations need reconfiguration of the pipeline stages, which inevitably disrupt the normal A/D operation. To diminish this deficiency, several background calibration schemes have been developed to enable ADCs to continuously calibrate their internal pipeline stages to track environmental changes while simultaneously performing the normal A/D conversions. The cost of background calibration is decreasing rapidly because the required digital circuits occupy less and less area in scaled technologies. This thesis presents a 15-b 40 MS/s switched-capacitor CMOS pipelined ADC. High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25um 1P5M CMOS technology. Operating at a 40 MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio (SNDR) of 73.5 dB and a maximum spurious-free-dynamic-range (SFDR) of 93.3 dB. The chip occupies an area of 3.8x 3.6 mm^2, and the power consumption is 370 mW with a single 2.5 V supply.
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Wu, Meng-Shuan, and 吳孟軒. "A Novel Digital Background Calibration Scheme for Multistage ADCs." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/91248295789246884495.
Full textAbstract:
碩士國立交通大學
電機與控制工程系所
94
As the trend for the CMOS process scaling continues advancing, the design of analog circuits such as the residue amplifier in the pipelined ADCs has become a much challenging work due to the lowed intrinsic gain and the voltage swing. The signal amplification by the residue amplifier is no longer linear but has distortions. This thesis presents a novel digital background calibration that accurately estimate and correct the linear and the nonlinear gain errors arising from the residue amplifier. The proposed estimation technique, called the multi-correlation estimation (MCE) technique, estimates residue gain errors by injecting random sequence alternatively, allowing extractions of linear and nonlinear gain errors orthogonally. In addition, the circuits enabling background estimation is largely simplified. This thesis also discusses the relationship between the recovered ADC resolution and the correction parameters associated with the calibration function. Therefore, a design strategy related to the practical implementation as well as the design consideration is built in this thesis. Employing the proposed scheme, the simulation result shows that a 12-bit 200MSample/s pipelined ADC before calibration only has an effective number of bit (ENOB) of 6 bits, an SNDR of 38.4 dB, a DNL of 2.55/ − 0.75 LSB, and an INL of 27/ − 27 LSB. After calibration, its ENOB and SNDR are improved to be 11.7 bits and 72.3 dB respectively, and its DNL and INL are 0.43/−1 and 0.66/-0.6 LSB respectively. These results verify the proposed technique does work well.
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Chou, Shih-Chin, and 周士欽. "Digital Background Calibration Techniques for Cyclic Analog-to-Digital Converters." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/21565921588445754449.
Full textAbstract:
碩士臺灣大學
電機工程學研究所
96
The rapid growth of DSP techniques makes it easier to design the digital system. More and more analog circuits have been replaced by digital systems. Hence, this thesis is targeted at incorporating DSP technique into cyclic ADC to improve circuit performance. The accuracy of a cyclic ADC architecture is susceptible to circuits imperfections, such as offset voltages, gain errors, non-linearity of operational trans-conductance amplifier (OTA), capacitors mismatch and comparator offset and so on. This thesis presents a 10-bit switched-capacitor cyclic ADC with a digital background calibration technique. The chip has been implemented with standard 0.35-µm double-poly four-metal CMOS process and occupies an area of 1800 um × 1800 um , and the power consumption is 240mW with a single 3.3V supply. The digital algorithm which can estimate the gain of ADC to reduce the capacitors mismatch and comparator offset has been demonstrated with better performance and implemented by FPGA.
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Sung, Chih-Kuo, and 宋治國. "A 6-bit 1GSPS Flash ADC with Background Offset Calibration." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/24460788734903512727.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
96
Offset calibration is a technique which detects the offset and adjusts the circuit configuration accordingly. However, foreground calibration only processes once which is not easy to prevent offset variations caused by temperature and supply voltage. In this thesis, the offset calibration circuit is proposed to make the circuit of the preamplifier and the comparator-latch match. It means that the offset voltages of the preamplifier and the comparator-latch are calibrated. Since the offset calibration circuit is based on the switch-capacitor circuit, the requirement of the power is less. The switch-capacitor circuit does not located at the connection of the conversion circuits, which does not affect the operating rate of the conversion. With the new switch network, the background offset calibration technique is implemented to prevent the offset variation. A 6-bit 1GSample/s flash ADC is implemented by TSMC 0.13um 1P8M CMOS process. After calibration, the simulation results show that SNDR is 36dB with 480MHz input frequency at 1GHz sample rate. The power consumption is 13.2mW where output buffers are not included. FoM of this ADC is 259fJ/conversion-step. Other comparable designs have FOMs between 0.5 to 10 pJ.
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Chuang, Shu-Chin, and 莊書瑾. "An All-Digital Fractional-N Frequency Synthesizer with Background Calibration." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/09152482221822750833.
Full textAbstract:
碩士國立交通大學
電子研究所
100
Phase noise is an important factor, which is used to estimate the performance of phase locked loop, and the choice of the bandwidth could also affect the phase noise directly. In an analog phase-locked loop, the bandwidth depends on the current of charge pump, the passive components in the loop filter and the gain of voltage control oscillator (VCO). Unfortunately, they would differ from the designed values because of the process, voltage and temperature (PVT) variation. However, in an all-digital phase-locked loop, the bandwidth is composed of some well-known parameters and the gain of digital control oscillator (DCO), but only the gain of DCO is unpredictable because of the PVT variation. An all-digital fractional-N frequency synthesizer with background calibration is presented. The background calibration method of the DCO gain could relieve the PVT variation on the DCO gain without affecting the operation of the communication system at the same time. Adding a digital code at the input of the DCO, so that the output of loop filter would generate an opposite signal,able to be recorded to formulate the estimation of the DCO gain. The background calibration method of the DCO gain could restore the loop bandwidth without changing other loop parameters. Besides, jitter performance is another important factor, which is used to estimate the performance of phase-locked loop. But it is difficult to measure the output clock jitter of the high speed phase-locked loop circuit directly. In addition, using external measuring equipment takes the high cost. For the reasons, the on-chip jitter measurement method, which dumps the frequency tuning word from the input of DCO, could estimate the jitter performance by lower frequency. Since the measured frequency changes from output frequency to reference frequency level, the on-chip jitter measurement methodcould release the cost of equipment. Implemented in TSMC-40nm CMOS technology, the total area included PAD is 1.330 x 1.195mm2. The measured output frequency of proposed ADPLL is 8GHz, where the RMS jitter is 3.4251ps in integer-N architecture and 13.019ps in fractional-N architecture.
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Chiou, Ming-Chi, and 邱銘吉. "A 6-bit 1GSPS Flash ADC with Step-Shifted Background Calibration." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/96974104278031857942.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
98
In this thesis, a 6-bit 1GSPS Flash ADC is implemented, and a background offset calibration circuit is proposed to calibrate the offset of the preamplifier and the latch due to mismatch. By using the switches for resistor ladder, the 1LSB step-shifted voltage from its reference voltage is generated. The probability of the input signal hitting into the same thermometer code would be not be the same in differential step-shifted. According to the output thermometer code and use the DAC with the ripple counter circuit to calibrate the offset. The two-level step-shifted method is proposed for higher resolution. A 6-bit 1G Sample/s flash ADC is implemented by TSMC 0.13um 1P8M CMOS process. Simulation results show that SNDR is 37dB with 441MHz input frequency at 1GHz sample rate. The power consumption is 13.2mW with a 1.2-V supply where output buffers are excluded.
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Liau, Jiun-Jie, and 廖俊杰. "A 4-Bit 1GSPS Flash ADC with Step-Shifted Background Calibration." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/85125639040706939529.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
96
A 4-bit flash ADC with step-shifted background calibration method is proposed in this thesis. This system would increase one comparator, switches for resistor ladder and use the random phase generator to generate shifted and non-shifted states. For the same comparator, its reference voltage would shift 1LSB in the two states. Because of the offset due to device mismatch, the probability of the input signal hitting into the same thermometer in shifted and non-shifted states would not be the same. Then, the system calculates the probability of the two states by ripple counter and applies the DAC circuit to cancel the offset. The counter would only work where the input signal hits in the thermometer code. Therefore, all of the counters wouldn’t work at the same time. Finally, the performance of the system would improve and keep after some calibration periods. This ADC is fabricated in a 0.13μm 1P8M CMOS process. The active area is only 0.027mm2. The ADC achieves a measured ENOB of 3.83b for a 435MHz input at 1GS/s. The power consumption (including clock buffer and resistor ladder) is 5mW at 1GS/s.
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Hsieh, Yi-Cheng, and 謝易成. "12-bit SAR ADC with Mixed Switching and Background Offset Calibration." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/ngq679.
Full textAbstract:
碩士國立交通大學
電機工程學系
106
This thesis presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with mixed switching and offset calibration in TSMC 0.18-µm process. To reduce the switching energy and save the total capacitance, a mixed switching procedure is applied. The mixed switching procedure combines the merged capacitor switching with monotonic switching. Beside, two dynamic comparators with charge pump and adaptive capacitor calibration to achieve lower offset are used. For the SAR ADC with charge pump at 1.8V supply voltage and 10MHz sampling rate, simulation results achieve 66.73dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 10.79 effective number of bits (ENOB) at 1.975MHz input frequency. Its power consumption is 736.23µW and figure-of-merit (FOM) is 41.58 fJ/conversion-step. For the SAR ADC with adaptive capacitor at 1.8V supply voltage and 50KHz sampling rate, simulation results achieve 72.56dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 11.76 effective number of bits (ENOB) at 9.876KHz input frequency. Its power consumption is 18.31µW and figure-of-merit (FOM) is 105.59 fJ/conversion-step. For the SAR ADC with charge pump at 1.8V supply voltage and 1MHz sampling rate, measurement results achieve 39.50dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 6.27 effective number of bits (ENOB) at 12.3444KHz input frequency. Its power consumption is 186.3762µW.
30
Lee, Yueh-Ru, and 李岳儒. "Design of 12-bit SAR ADCs with Analog Background Calibration Technique." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/5gjh23.
Full textAbstract:
碩士國立交通大學
電機工程學系
107
In this thesis, the design consideration of low-speed, mid/high resolution successive approximation register analog-to-digital converters (SAR ADCs) is discussed in depth. The three mentioned ADCs are all designed for biomedical applications, such as the external signal receiver of bone-guided cochlear implants. All the ICs were fabricated by using 0.18-μm 1P6M TSMC CMOS process. The first IC is a 10-bit 47KS/s SAR ADC which adopts monotonic switching technique. Due to the layout simplicity of the digital blocks, the power consumption is as low as 2.6μW. At normal sampling rate and provided with a 1.8VPP input signal, the measured ENOB, SNDR and SFDR are 9.77-bit, 60.55dB, and 82.18dB, respectively. It occupies an area of 598μm×786μm and the FOM is 63 fJ/conv.step. The second one is a 12-bit 62KS/s calibration-free SAR ADC which adopts VCM-based switching technique and includes redundant capacitors to counter comparator offset and reference voltage error. At normal sampling rate and provided with a 1.8VPP input signal, after measuring 8 ICs, the average ENOB, SNDR, SFDR, input referred noise, and power consumption are 11-bit, 68dB, 83dB, 209μV, and 6.7μW, respectively. It occupies an area of 587μm×599μm and the FOM is 53 fJ/conv.step. The third one is also a 12-bit 62KS/s SAR ADC, but with analog background calibration circuit, which quantizes and calibrates the capacitor mismatch error according to the comparator output while certain codes in the register are detected. While disabling the calibration feature and provided with a 1.8VPP input signal, after measuring 8 ICs, the average ENOB, SNDR, SFDR, input referred noise, and power consumption are 10.4-bit, 64.4dB, 73dB, 193μV, and 7.4μW, respectively. While enabling the calibration feature and under the same circumstance, after measuring 8 ICs, the average ENOB, SNDR, SFDR, input referred noise, and power consumption are 10.8-bit, 66.6dB, 79dB, 235μV, and 9μW, respectively. It occupies an area of 560μm×350μm and the FOM is 83 fJ/conv.step.
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Lu, Ing-June, and 盧盈君. "Realization of a Cyclic ADC with Split Architecture and Digital Background Calibration." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/20988434305200037572.
Full textAbstract:
碩士臺灣大學
電機工程學研究所
96
This thesis realizes a cyclic analog-to-digital converter with background digital calibration according to the split-ADC architecture proposed by McNeill in 2005. The purpose is to establish an experimental platform on which the A/D converter and digital calibration circuit can be integrated. The calibration algorithm adopted does not require extra calibration signal to be injected in to the converter’s signal path, and therefore minimizes its effect on the input signal. Also, with the help of digital calibration, the overhead of implementing the split-ADC architecture is reduced. It only increases two extra comparators compared with the traditional architecture. The underlying calibration principle assumes the average of two adjacent A/D converters as the ideal conversion result. The converter then may be taken as an unknown system whose characteristics can be probed with an adaptive filter. Using the assumed ideal conversion results and the real conversion output, one may apply the least-mean-square method. In this way, the actual parameters of the individual ADCs is found, completing the digital calibration procedure. The chip has been fabricated using 0.35 um CMOS process, occupying area of 1.5x1.5 mm2. Measurement results show that the split-ADCs exhibit resolution of 45.70 dB and 45.78 dB, equivalent to ENOB of 7.3 bits and 7.3 bits, respectively. The maximum DNL of the converters are 1.34 LSB and 1.15 LSB, and the maximum INL are 4.91 LSB and 4.89 LSB, respectively. (LSB unit is calculated assuming 10-bit resolution) Digital calibration circuit is realized on FPGA, with maximum achievable operating frequency of 30.44 MHz. After integration, the system improves the resolution from 45.94 dB to 54.43 dB, which equivalently improves ENOB from 7.33 to 8.74. Maximum DNL are 1.16 LSB and 1.15 LSB before and after calibration, respectively, and maximum INL drops from 4.38 LSB to 1.77 LSB.
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Lai, Bing-Wen, and 賴炳文. "A 10-bit 50MS/s Pipelined ADC With Background Gain Error Calibration." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/3re278.
Full textAbstract:
碩士國立中正大學
電機工程研究所
102
This work presents a 10bit 50MS/s pipelined analog-to-digital (ADC) with background gain error calibration. This pipelined ADC is implemented in a 0.18-um CMOS process technology. This circuit is to calibration gain error. Although there are many papers presented before the calibration of the gain error, but earlier gain error calibration usually requires three phases. This will affect the sampling rate. This paper requires only two phases, we can achieve gain error calibration circuit. And does not require additional circuit. An 10bit 50MS/s prototype pipelined ADC has been fabricated in 0.18-um CMOS. The overall power dissipation is 19.2mW from a 1.8V supply. With a 24.56MHz input frequency. This pipelined ADC SNDR is 57.22dB, and ENOB 9.21bit.
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Lin, Li-Wei, and 林莉惟. "Design of 10-bit SAR ADC with Background Calibration of Comparator Offset." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/bvh4gu.
Full textAbstract:
碩士國立交通大學
電機工程學系
106
This thesis presents a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with background calibration of comparator offset. A pre-amplifier is used as the first stage of the comparator. As there is mismatch between input differential pair, it would cause input offset. A background calibration approach of the offset is in this thesis. Under the 500 times of Monte Carlo simulations, he offset with calibration is 0.97mV as compared with the offset of 18.47mV without calibration, This SAR ADC design is applied to the microelerctronic system of cochlear implant with 1.8V supply voltage. The sampling rate is 48KHz with 24KHz signal bandwidth. The simulation results show 56.7dB signal-to-noise-and-distortion-ratios (SNDR) which leads to 9.62 effective number of bits (ENOB) at 6046.875Hz input frequency. Its power consumption is 121.2uW and the chip area is 0.953 x 1.502 mm.
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Lee, Andrew, and 李念祖. "A 14-bit Analog-to-Digital Converter with Background Nonlinearity Calibration Technique." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/35313270623162048899.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
105
The thesis focuses on designing a high-performance Analog-to-Digital converter (ADC) in CMOS fabrication. In addition, the ADC needs to achieve a high-resolution requirement in order to apply communication and graphic system. Accordingly, we design a 14-bit 100MS/s pipelined-SAR ADC. Furthermore, using background calibration to improve linearity and be compatible with the system’s requirement. In early works, pipelined ADC was the major architecture that had been researched and designed for many years. The reason is that pipelined ADC has an advantage of speed. However, its drawback is that it consumes a lot of power to achieve high-speed. In recent years, researches and papers dedicated to invent low power architecture. More and more people studied successive approximation register ADC (SAR ADC) for its advantage of energy efficiency. The architecture of SAR ADC contains comparator, amplifier, sample and hold circuit, capacitor array, and digital logics. SAR ADC uses binary searching method to convert analog signals into digital codes. Thus, comparing the speed to pipelined ADC, SAR ADC has a little bit slower than pipelined ADC. In this thesis, we introduce a pipelined-SAR ADC. It is based on SAR ADC architecture in order to achieve energy efficiency. Considering to the speed, pipelined-SAR consists the conversion method of pipelined ADC. It uses two stages to do the evaluation. While one stage is sampling, the other is converting. Therefore, with pipelined ADC operation style, pipelined-SAR ADC is able to wisely use a full cycle of time and accelerate the speed. The nonlinearity gain error of residue amplifier may influence pipelined-SAR ADC's resolution. We apply a digital calibration system to correct linearity and nonlinearity errors. After nonlinearity is removed, the residue amplifier is approximately to be a linear amplifier.
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Tzuyi, Tang, and 湯子儀. "A Background Timing Mismatch Calibration in Time-interleaved ADCs Based on Interchannel Correlation." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/80476409389971043326.
Full textAbstract:
碩士國立中正大學
電機工程研究所
101
A digital background timing mismatch calibration scheme for the two-channel time-interleaved analog-to-digital converter (ADC) is designed and implemented. The non-ideal effects among the time-interleaved ADCs, such as offset and timing mismatches, degrade the overall signal-to-noise ratio (SNR) of the ADCs. Background calibration is a well-known technique to overcome timing error. Correlation between adjacent channels based on zero-crossing detection is utilized. Adaptive least mean square (LMS) algorithm is utilized in the digital calibration. The proposed calibration technique does not require any extra reference signal. A 5 bit, 1.25GS/s flash ADC has been fabricated in a 90 nm CMOS process. Moreover, a folding flash architecture is employed to save the conversion power. To alleviate random offsets caused by process variation, a digital calibration technique is adopted. Post layout simulation shows that the power consumption is 3.53mW, where input frequency is 600MHz and the sampling rate is 1.25GS/s.
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Zeng, Jhao-Wei, and 曾昭瑋. "A Background Timing-Skew Calibration Technique Using Channel Correlation for Time-Interleaved ADCs." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/kgy69u.
Full textAbstract:
碩士國立中正大學
電機工程研究所
102
Time-interleaved analog-to-digital converters (TIADCs) are essential in wide-band communication systems for providing high-speed data conversion. However, TIADCs are sensitive to the sample time mismatch, which results in significantly degraded performance. In there, we proposed a background compensation technique for sample-time error in time-interleaved ADCs. Our approach is based on the correlation between the probability of zero-crossing and the timing skew. The correlation among adjacent ADC channels was analyzed and used to correct the timing skew. Least-Mean Square (LMS) algorithm was employed to minimize the timing skew by digitally controlled delay cells. The proposed calibration technique does not require any extra reference signal. A 5 bit, 1GS/s flash ADC has been fabricated in a 90 nm CMOS process. Moreover, a folding flash architecture is employed to save the conversion power. To alleviate random offsets caused by process variation, a digital calibration technique is adopted. Post layout simulation shows that the power consumption is 2.4mW, ENOB is 4.54 bit, where input is close to Nyquist frequency and the sampling rate is 1GS/s.
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Lei, Kin-Man, and 李健文. "A 12-bit 25MS/s Asynchronous SAR ADC With All Digital Background Calibration." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/07793099824693147628.
Full textAbstract:
碩士國立交通大學
電控工程研究所
100
The resolution of a SAR ADC is mainly limited by the accuracy of capacitor ratios. Foreground and background calibration schemes [1][2][3][4][5] have been proposed to calibrate the capacitor weight errors. However, both kinds of calibration schemes may suffer from power and speed penalties. The foreground calibration schemes using charge redistribution have the advantage of simple implementation but the continuous variations of environmental parameters may cause it failed. The background calibration schemes can address the variation problems but its hardware is very complicated due to the implementation of complex mathematical equations. This thesis proposes a calibration scheme that keeps the advantages of the foreground and background calibration schemes and improve the performance of the SAR ADC in power and speed. We also adopted a suitable bit-cycling scheme to simplify the comparator design and thus to enhance its performance. Post-layout simulation results show that the calibrated SAR ADC achieves a SNDR improvement from 47.4dB to 63.9dB at a sampling rate of 25MS/ s when random mismatch is added on each capacitor in DAC. Measurement results shows the SAR ADC achieves a SNDR improvment from 47.1dB to 51.8dB at its highest sampling rate of 10MS/s.
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Yoo, Jae Ki. "A background calibration technique and self testing method for the pipeline analog to digital converter." Thesis, 2004. http://hdl.handle.net/2152/1440.
Full text
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Tien, Che-Wei, and 田哲瑋. "Digital Phase-Locked Loop With Background Supply Noise Calibration and Injection-Locked Clock Multiplier." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/k3n9vy.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
105
This thesis consists of two parts. The first part implements a digital phase-locked loop (DPLL) with background supply voltage sensitivity calibration. A digital supply voltage sensitivity controller with a frequency subtractor is used to suppress the supply voltage sensitivity. With a 50mVPP, 100kHz sinusoidal supply noise tone, the calibration scheme reduces the peak-to-peak jitter from 41.48ps to 23.15ps and the rms jitter is reduced from 7.26ps to 3.47 ps. The measured peak-to-peak jitter and rms jitter without supply noise are 19.21ps and 2.71ps. Its active area is 0.006mm2 and the power consumption is 9.34mW. The second part implements an injection-locked clock multiplier (ILCM). The ILCM is presented with a frequency calibrator (FC) using a delay time detector to calibrate the frequency error due to the process, voltage, and temperature (PVT) variations. The reference spur and timing jitter due to the PVT variations can be significantly reduced. When injection locked, the measured reference spur is -61.28dBc and the rms jitter integrated from 10kHz to 100MHz is 479fs. Its active area is 0.012mm2 and the power consumption is 2.55mW.
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Wei, Yen-Hsin, and 魏衍昕. "A 12-bit 600MS/s Time-Interleaved SAR ADC with Background Timing Skew Calibration." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/19086299833215672228.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
103
A four channel time-interleaved 12-b SAR ADC, employing the proposed digital calibration technique to correct timing skew, achieves a 600-MHz sampling rate. The interleaved ADC composed of four channel SAR ADC. Digital mixing method is used to estimate timing skew, and proposed dual core with delay sampling is used to correct the timing skew. The ADC has been fabricated in a 40-nm CMOS technology, improves interleaving spurious tones from -50dB to -76dB and achieves a 61.7-dB SNDR while dissipating 23 mW from a 0.9-V power supply. The figure of merit (FoM) is 38.7 fJ/conversion-step and the active area is 0.3 mm2
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Fan-WeiLiao and 廖凡緯. "A 14-bit 800MS/s 4-way Time-Interleaved Pipelined ADC with Digital Background Calibration." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/m564q3.
Full textAbstract:
碩士國立成功大學
電機工程學系
104
Pipelined ADCs are usually implemented for high-speed high-resolution applications. However, to achieve high resolution, the error induced by the opamp must be eliminated, including finite opamp gain error, opamp offset and distortion error. This thesis proposes a dual-residue split-ADC architecture and digital background calibration technique for opamp errors, so that a low-cost low-power amplifier could be used. This architecture and calibration technique have the benefits of low complexity and high convergence. Moreover, these techniques can be used in time-interleaved pipelined ADCs. Compared with the traditional TI-ADC, the additional cost for calibrating channel mismatches, which includes gain error mismatch and offset mismatch, is unnecessary. Besides, the timing mismatch could be overcome by a bootstrapped switch, which is embedded in the global sampling techniques proposed in this thesis. The proposed dual-residue split-ADC and calibration technique are implemented in a 14-bit 800MS/s four-way time-interleaved pipelined ADC fabricated in TSMC 40nm 1P9M CMOS process. A multi-bit front-end stage and open-loop architecture are implemented in this work for power saving. The post-simulation results show that the SNDR before calibration is 37.3 dB and improved after calibration to 66.8 dB at 370MHz input frequency and 800MS/s sampling rate. The power consumption is 83.8mW from a 1V supply excluding output buffer. The Figure of Merit (FOM) of this prototype ADC is 58.5 fJ/conversion.step.
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Lin, Yi-Shen, and 林益申. "Design and Implementation of 14 bit Pipeline-SAR ADCs with a Background Nonlinearity Calibration Scheme." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/2n665a.
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碩士國立臺灣科技大學
電子工程系
107
The Thesis focused on designing a high-speed and high-resolution Analog-to-Digital Converter (ADC) in advanced nanometer CMOS fabrication. In order to apply communication and graphics system, the author uses a pipelined-SAR ADC combined with background calibration technique. This architecture integrates the low-power SAR ADC and high-speed pipeline ADC and converts by using the two-stage pipelined method. Therefore, Pipeline-SAR ADC can efficiently use the time to increase speed. However, due to the residue amplifier (RA) has a nonlinear gain error, the author proposed a digital background calibration processor which corrects the gain and nonlinearity errors. After correcting the RA by digital background calibration, the performance of ADC will be greatly improved. In this thesis, the author implements two ADC chips. The first ADC is a 14bit 160MS/s pipeline-SAR in TSMC 40nm process, and its power is 7.2mW at the 1.0V/2.5V. When the input signal is Nyquist, the SNDR and SFDR are 72.2dB and 85dB in post-layout simulation. The Walden FOM is 14fJ/conversion-step. The second ADC is a 14bit 80MS/s pipeline-SAR in TSMC 90nm process, and its power is 7.2mW at the 1.2V/2.5V. When the input signal is Nyquist, the SNDR and SFDR are 75.2dB and 83dB in post-layout simulation. The Walden FOM is 11fJ/conversion-step.
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Yi-ShenCheng and 鄭乙申. "An 8-bit 1.6-GS/s Flash-SAR Time-Interleaved ADC with Background Offset Calibration." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/x6agxt.
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Liou, Jia-Yao, and 劉家耀. "A Background Time-Skew Calibration by Exclusive-OR Time-Skew Detection and Discrete-time Error Accumulation." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/15898863842502380676.
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碩士國立中正大學
電機工程研究所
104
This paper mainly proposes a background sampling-time skew calibrator used for timing adjustment of time-interleaved ADCs(TIADC). Though the TIADC has its merit of high-sampling rate, the mismatches between internal sub-ADCs cause mismatch errors and decrease the performance of the ADCs. These mismatch errors include offset mismatch, gain error mismatch, sampling-time error and the sampling-time error dominantly limits the performance of ADCs in high-speed applications when compared with other mismatch errors. The sampling-time error impacts the SNR of ADC outputs more seriously when the input frequency is increased. So our work mianly discuss timing calibration algorithm. We propose detection and and calibration circuits for timing errors inspired by thories of previous arts. Using ‘Altera Stratix III Development and Education board’ to fulfill the background calibrator and verifying functions of circuits by digital codes generated by Matlab Simulink model. Furthermore, this work analyzes and measures a two-chaanel, 90nm flash TIADC chip. The input clock is 1.25GHz, the resolution is 5bit, the supply voltage is 1V, the signal range is 640mV, the power consumption is 55mW under its normal operation, the digital outputs is downsampled by a factor of 8 to fit the speed requirement of used instruments.
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Hong, Tzu-Chieh, and 洪子傑. "Design and Development of Calibration Signal Source for the Receivers of Array for Microwave Background Anisotropy." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/6ca9fs.
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碩士國立中央大學
電機工程研究所
96
Abstract In this thesis, the design and test of calibration source for Array for Microwave Background Anisotropy(AMiBA) telescope receiver are proposed. The implementation of calibration source is separated into two sections. In the first section, the YIG synthesizer was designed. It could export signals about 21~ 26 GHz with interval of 1GHz, which is controlled by an embedded computer. The YIG synthesizer is composed of a YIG oscillator chain, comb generator chain and phase-locked circuit module. The output of YIG oscillator chain is generated by a YIG oscillator followed by an isolator and a coupler. The comb generator chain has a 100MHz crystal oscillator as reference source, which connects to a phase-locked coaxial resonator oscillator to generate 1GHz output signal. A comb generator is then used to generate harmonics of 1GHz, and then the harmonics are mixed with a 21GHz signal from the signal generator (In the future, it will replace by the output of phase-locked dielectric resonator oscillator from AMiBA receiver). The up-converted signal outputs will be 21~26GHz with 1GHz interval. The phase-locked circuit module is then used to integrate the YIG oscillator chain and comb generator chain into a phase-locked-loop. The phase-locked loop incorporates a down conversion mixer, and the outputs of YIG oscillator chain and comb generator chain are connected to the RF and LO port of the mixer. The 25MHz IF output is compared with the reference signal so as to lock the YIG synthesizer output frequency. In the section section, the output of YIG synthesizer is divided into two paths by a dual output amplifier and connected to two mechanical phase shifters which are followed by two switch array. The switched output signal is imported to a multiply-by-4 harmonic generator, and then transmitted to the 13 receivers of AMiBA as a calibration source. In this thesis, we have completed the implementation of the YIG synthesizer and most part of the transmission components. The testing and integration of proposed calibration source with the AMiBA receiver array will be done in the near future.
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Jie-Cheng, Lin, and 林傑澄. "The Software, Firmware, Calibration, and Running of the BGO Background/Luminosity Monitor in BEAST2 for SuperKEKB Commissioning." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/5qcp7s.
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碩士國立臺灣大學
物理學研究所
105
Beam commissioning of the SuperKEKB collider began in 2016. The Beam Ex-orcism for A STable experiment II (BEAST II) project is particularly designed to measure the beam backgrounds around the interaction point of the SuperKEKB collider for the Belle II experiment. We developed a system using undoped bismuth germanium oxide (BGO) crystals with optical fiber connections to a multianode photomultiplier tube and one field-programmable gate array embedded DAQ (data acquisition) board for real-time beam radiation background monitoring. The radia-tion sensitivity of the BGO system is calibrated as 2.2E−12 ± 11.75% Gy/ADU (analog-to-digital unit) at the 700-V operation voltage with the nominal 10-m-long fibers for transmission. Our γ-ray irradiation study of the BGO system shows that the BGO crystals suffered from radiation damage. The light yields of the BGO crystals dropped by ∼40% after receiving 4.5 krad dose in 2.5 h, which agrees with the results of the radiation hardness study we have reported. The irradiation study also proves that the BGO system is very reliable, being able to function at fairly high radiation conditions without serious saturation or other problems. Besides, the running of the BGO system in BEAST II was very successful. It has provided much useful data for the beam background study. The data that the BGO system provided will facilitate the development of the entire BEAST II project. My study contains the design of the firmware and software, the calibration of the device, the analysis of the results of the irradiation study, and the integration of the data obtained during the running in BEAST II. In this thesis, I make a comprehensive portrait of the BGO system, including the design, calibration, tests, and the results of the beam background study in BEAST II.
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Lin, Shen-Pai, and 林慎白. "Implementation of a 13-bit 100-MS/s Pipelined ADC with the Multi-Correlation Based Digital Background Calibration." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/45w88a.
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碩士國立交通大學
電機工程學系
102
With the rapid growth of portable electronics applications, reducing the power consumption of the circuits becomes a very important issue. In the pipelined analog to digital converter (ADC), the front-end multiplying digital-to-analog convertor (MDAC) needs to meet the most stringent linearity, speed and noise requirements. In the traditional closed-loop pipeline ADC, the MDAC requires an operational amplifier (OP) with a high open-loop gain and a large unity-gain bandwidth, which consumes power. Moreover, analog circuit design encounters many challenges in advanced technology, such as decreased intrinsic gain and limited signal headroom due to reduced supply voltage. Consequently, how to design an OP that can achieve the stringent specifications becomes a very difficult challenge. On the contrary, digital circuits benefit from advanced technology for fast operation, lower power, and a smaller chip area. Consequently, the digital-assisted analog circuit design concept becomes an important research topic in advanced technology. This thesis proposes a 13-bit 100-MS/s pipelined ADC which replaces the conventional closed-loop residue amplifier with a simple open-loop one in the first pipelined stage. The advantages of using an open-loop residue amplifier include fast operation, signaificantly reduced power, and the easy design of the residual amplifier. The linear and 3rd order nonlinear errors induced by the open-loop residue amplifier is estimated and calibrated using the multi-correlation based digital background calibration. The thesis implements a high performance pipelined ADC by adopting the concept of digital-assist analog circuit design. The proposed pipelined ADC has been designed and fabricated in TSMC 90-nm CMOS process. The measurement results show that, the DNL and INL of the pipelined ADC without calibration are within -1.00/+3.92 LSB and -194.74/+184.36 LSB, and improved to -1.00/+2.63 LSB and -5.60/+5.70 LSB after calibration, respectively. The dynamic test results show the ENOB of thr pipelined ADC is improved from 5.3 bits to 8.7 bits with the calibration. 3.4 ENOB enhancement is achieved. The results show the significant improvement in performance after calibration but there is still room for improvement. There are two possible resons that cause the performance degradation. First, the high order which large than 5th order nonlinear errors excess the calibration range of this thesis. Second, the capacitor mismatch in sub-DAC of under calibration stage insufficient the resolution of DAC, dramatically limits on calibration performance.
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Liu, Yi-Huang, and 劉議煌. "Design of a 13-bit 100-MS/s Pipelined ADC with Digital Background Calibration in 0.18-um CMOS." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/83221021606564543572.
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碩士國立交通大學
電控工程研究所
100
In the front-end of a conventional pipelined ADC, the embedded multiplying digital-to-analog converter (MDAC) has to meet very stringent noise, speed, and linearity requirements. As a result, the MDAC needs an operational amplifier (OP) with a very high open-loop gain and a large unity-gain bandwidth. Such an OP dominates the overall power dissipation of the pipelined ADC. Moreover, as the advanced technology keeps scaling, the reduced supply voltage limits the signal headroom and the reduced channel length decreases the intrinsic gain of transistors.Consequently, it is very difficult to design an OP that can achieve the stringent specifications with the advanced technology. In order to save power and alleviate the design difficulty in advanced technology,this thesis proposes a 13-bit 100-MS/s pipelined ADC with digital background calibration. The design replaces the conventional closed-loop residue amplifier with a simple open-loop architecture in the first pipelined stage which specifications is the most stringent in the pipelined ADC. The gain error and the third-order nonlinearity of the open-loop residue amplifier are calibrated using a digital background calibration technique. The calibration scheme continuously estimates and calibrates the errors introduced by the imprecise and nonlinear gain of the open-loop residue amplifier. By adopting the concept of digital-assist analog circuit design, this thesis implements a high performance pipelined ADC with the aid of CMOS scaling. The proposed pipelined ADC has been designed and fabricated in a TSMC 0.18-um CMOS process and the digital background calibration is implemented by a FPGA. The measurement results show that the ENOBs of the ADC output with calibration and without calibration at an analog power supply of 1.65V, a digital power supply of 1.8V, and a sampling rate of 12MS/s are 5.3 bits and 7.2 bits,respectively. There are two possible reasons that cause the performance degradation of the pipelined ADC. First, the pipelined ADC can’t work properly and the offset of the backend stage can’t be cancelled because of a timing error of the comparator design. Second, the operating speed of the flash memory on the FPGA board limits the sampling rate of the pipelined ADC to be less than 12MS/s.
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Hung, Li-Han, and 洪立翰. "A 10-bit 50-MS/s Pipelined A/D Converter with Split Background Digital Calibration and Opamp-Sharing Technique." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/41092677983566431196.
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碩士國立臺灣大學
電子工程學研究所
97
Pipelined analog-to-digital converters (ADCs) have been widely utilized in mid-resolution, high-speed applications. In this thesis, a background digital calibration technique based on the split ADC is proposed to correct linear errors in a pipelined ADC, which allows the use of simple-structured low-gain opamps in conversion stages. Raw output codes of the designed ADC exhibit a SNDR and a SFDR of merely 35.3 dB and 37.3 dBFS, respectively. As the associated linear errors are adaptively removed by the proposed calibration technique, the SNDR and the SFDR are improved to the level of 55.2 dB and 67 dBFS. Furthermore, the proposed calibration system converges in less than 10ms at 50MS/s, showing a significant improvement over previous works. Fabricated in the 0.35um CMOS technology, the core this split pipelined ADC occupies 1.64mm2. The introducing of opamp-sharing technique reduces the core power consumption to 45mW from a 3V supply voltage at 50MS/s. At the end of this thesis, a nonlinear calibration technique combining the linear approximation and the split concept is developed to enhance the resolution for pipelined ADCs realized with open-loop amplifiers.
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Wei-Der, Wang. "A 10-bit 300-Msample/s Pipelined Analog-to-Digital Converter with Open-loop Residue Amplification an Digital Background Calibration." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2207200509294600.
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