Academic literature on the topic 'Backside illuminated CMOS image sensors'

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Journal articles on the topic "Backside illuminated CMOS image sensors"

1

Kim, Bioh, Thorsten Matthias, Gerald Kreindl, Viorel Dragoi, Markus Wimplinger, and Paul Lindner. "Advances in Wafer Level Processing and Integration for CIS Module Manufacturing." International Symposium on Microelectronics 2010, no. 1 (2010): 000378–84. http://dx.doi.org/10.4071/isom-2010-wa1-paper5.

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This article presents the advances in wafer-level processing and integration techniques for CMOS image sensor module manufacturing. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications. The backside illumination technique has significant advantages over the front-side illumination due to separation of the optical path from the metal interconnects. Wafer bonding plays a key role in manufacturing backside illuminated sensors. The cost-effective integration of miniaturized cameras in various handheld devices becomes realized through the introduction of CMOS image sensor modules or camera modules manufactured with wafer-level processing and integration techniques. We developed various technologies enabling wafer-level processing and integration, such as (a) wafer-to-wafer permanent bonding with oxide or polymer layers for manufacturing backside illuminated sensor wafers, (b) wafer-level lens molding and stacking based on UV imprint lithography for making wafer-level optics, (c) conformal coating of various photoresists within high aspect ratio through-silicon vias, and (d) advanced backside lithography for various metallization processes in wafer-level packaging. Those techniques pave the way to the future growth of the digital imaging industry by improving the electrical and optical aspects of devices as well as the module manufacturability.
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Minoglou, K., Padmakumar R. Rao, M. Rahman, K. De Munck, C. Van Hoof, and P. De Moor. "Backside illuminated CMOS image sensors optimized by modeling and simulation." Optical and Quantum Electronics 42, no. 11-13 (2011): 691–98. http://dx.doi.org/10.1007/s11082-011-9456-9.

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3

Zhang, Xiang, Yudong Li, Lin Wen, et al. "Displacement damage effects induced by fast neutron in backside-illuminated CMOS image sensors." Journal of Nuclear Science and Technology 57, no. 9 (2020): 1015–21. http://dx.doi.org/10.1080/00223131.2020.1751323.

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4

De Vos, Joeri, Anne Jourdain, Wenqi Zhang, Koen De Munck, Piet De Moor, and Antonio La Manna. "The Road towards Fully Hybrid CMOS Imager Sensors." International Symposium on Microelectronics 2011, no. 1 (2011): 000173–80. http://dx.doi.org/10.4071/isom-2011-ta5-paper5.

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Monolithic imagers contain the photosensitive elements as well as the read-out IC (ROIC) on the same substrate. Backside thinning on carrier enables efficient collection of photo-generated carriers through back illumination, resulting in almost 100% fill factor. This contrary to front side illumination where light loss is introduced by reflection on metal interconnects. Together with an optimized backside ARC coating, high quantum efficiency (QE) can be achieved. Hybrid imagers consist of a detector array that is produced separately and hybridized on a ROIC. A fully-hybrid backside illuminated imager has more flexibility because the detector array and the ROIC can be separately optimized to the needs of the application leading towards further improvement on QE and inter pixel cross talk. Fully processed thinned diode arrays were flip-chipped onto the ROIC by means of an Indium bump per pixel. The choice of the bump type is very critical for yielding imager assemblies, or more in general, 3D assemblies. The Indium bump process has however limited fab compatibility to evolve towards a production mature hybrid imager process. Therefore an alternative electroplated CuSn micro bump process is described. We report an average daisy chain yield above 90% for die-to-die assemblies with CuSn bumps. Measurements were performed on a dedicated 1M bump area array test design with very long daisy chains of bumps on a 20μm pitch. Processing aspects like choice of plating seed layer, the influence of cleaning agents and seed layer etchants on the micro bump performance are being discussed. Finally, the impact on the daisy chain yield after thermal cycling is shown.
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5

Liu, Bingkai, Yudong Li, Lin Wen, et al. "Study of dark current random telegraph signal in proton-irradiated backside illuminated CMOS image sensors." Results in Physics 19 (December 2020): 103443. http://dx.doi.org/10.1016/j.rinp.2020.103443.

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6

Xu, C., C. Shen, W. Wu, and M. Chan. "Backside-Illuminated Lateral PIN Photodiode for CMOS Image Sensor on SOS Substrate." IEEE Transactions on Electron Devices 52, no. 6 (2005): 1110–15. http://dx.doi.org/10.1109/ted.2005.848106.

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7

Seok, Godeun, and Yunkyung Kim. "Front-Inner Lens for High Sensitivity of CMOS Image Sensors." Sensors 19, no. 7 (2019): 1536. http://dx.doi.org/10.3390/s19071536.

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Due to the continuing improvements in camera technology, a high-resolution CMOS image sensor is required. However, a high-resolution camera requires that the pixel pitch is smaller than 1.0 μm in the limited sensor area. Accordingly, the optical performance of the pixel deteriorates with the aspect ratio. If the pixel depth is shallow, the aspect ratio is enhanced. Also, optical performance can improve if the sensitivity in the long wavelengths is guaranteed. In this current work, we propose a front-inner lens structure that enhances the sensitivity to the small pixel size and the shallow pixel depth. The front-inner lens was located on the front side of the backside illuminated pixel for enhancement of the absorption. The proposed structures in the 1.0 μm pixel pitch were investigated with 3D optical simulation. The pixel depths were 3.0, 2.0, and 1.0 μm. The materials of the front-inner lens were varied, including air and magnesium fluoride (MgF2). For analysis of the sensitivity enhancement, we compared the typical pixel with the suggested pixel and confirmed that the absorption rate of the suggested pixel was improved by a maximum of 7.27%, 10.47%, and 29.28% for 3.0, 2.0, and 1.0 μm pixel depths, respectively.
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8

Vereecke, Bart, Celso Cavaco, Koen De Munck, et al. "Quantum efficiency and dark current evaluation of a backside illuminated CMOS image sensor." Japanese Journal of Applied Physics 54, no. 4S (2015): 04DE09. http://dx.doi.org/10.7567/jjap.54.04de09.

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9

Bingkai, Liu, Li Yudong, Wen Lin, et al. "Analysis of Dark Signal Degradation Caused by 1 MeV Neutron Irradiation on Backside‐Illuminated CMOS Image Sensors." Chinese Journal of Electronics 30, no. 1 (2021): 180–84. http://dx.doi.org/10.1049/cje.2020.12.002.

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10

Horie, Yu, Seunghoon Han, Jeong-Yub Lee, et al. "Visible Wavelength Color Filters Using Dielectric Subwavelength Gratings for Backside-Illuminated CMOS Image Sensor Technologies." Nano Letters 17, no. 5 (2017): 3159–64. http://dx.doi.org/10.1021/acs.nanolett.7b00636.

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