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Journal articles on the topic 'Backside illuminated CMOS image sensors'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 February 2022

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1

Kim, Bioh, Thorsten Matthias, Gerald Kreindl, Viorel Dragoi, Markus Wimplinger, and Paul Lindner. "Advances in Wafer Level Processing and Integration for CIS Module Manufacturing." International Symposium on Microelectronics 2010, no. 1 (2010): 000378–84. http://dx.doi.org/10.4071/isom-2010-wa1-paper5.

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This article presents the advances in wafer-level processing and integration techniques for CMOS image sensor module manufacturing. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications. The backside illumination technique has significant advantages over the front-side illumination due to separation of the optical path from the metal interconnects. Wafer bonding plays a key role in manufacturing backside illuminated sensors. The cost-effective integration of miniaturized cameras in various handheld devices becomes realized through the introduction of CMOS image sensor modules or camera modules manufactured with wafer-level processing and integration techniques. We developed various technologies enabling wafer-level processing and integration, such as (a) wafer-to-wafer permanent bonding with oxide or polymer layers for manufacturing backside illuminated sensor wafers, (b) wafer-level lens molding and stacking based on UV imprint lithography for making wafer-level optics, (c) conformal coating of various photoresists within high aspect ratio through-silicon vias, and (d) advanced backside lithography for various metallization processes in wafer-level packaging. Those techniques pave the way to the future growth of the digital imaging industry by improving the electrical and optical aspects of devices as well as the module manufacturability.

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2

Minoglou, K., Padmakumar R. Rao, M. Rahman, K. De Munck, C. Van Hoof, and P. De Moor. "Backside illuminated CMOS image sensors optimized by modeling and simulation." Optical and Quantum Electronics 42, no. 11-13 (2011): 691–98. http://dx.doi.org/10.1007/s11082-011-9456-9.

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3

Zhang, Xiang, Yudong Li, Lin Wen, et al. "Displacement damage effects induced by fast neutron in backside-illuminated CMOS image sensors." Journal of Nuclear Science and Technology 57, no. 9 (2020): 1015–21. http://dx.doi.org/10.1080/00223131.2020.1751323.

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4

De Vos, Joeri, Anne Jourdain, Wenqi Zhang, Koen De Munck, Piet De Moor, and Antonio La Manna. "The Road towards Fully Hybrid CMOS Imager Sensors." International Symposium on Microelectronics 2011, no. 1 (2011): 000173–80. http://dx.doi.org/10.4071/isom-2011-ta5-paper5.

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Monolithic imagers contain the photosensitive elements as well as the read-out IC (ROIC) on the same substrate. Backside thinning on carrier enables efficient collection of photo-generated carriers through back illumination, resulting in almost 100% fill factor. This contrary to front side illumination where light loss is introduced by reflection on metal interconnects. Together with an optimized backside ARC coating, high quantum efficiency (QE) can be achieved. Hybrid imagers consist of a detector array that is produced separately and hybridized on a ROIC. A fully-hybrid backside illuminated imager has more flexibility because the detector array and the ROIC can be separately optimized to the needs of the application leading towards further improvement on QE and inter pixel cross talk. Fully processed thinned diode arrays were flip-chipped onto the ROIC by means of an Indium bump per pixel. The choice of the bump type is very critical for yielding imager assemblies, or more in general, 3D assemblies. The Indium bump process has however limited fab compatibility to evolve towards a production mature hybrid imager process. Therefore an alternative electroplated CuSn micro bump process is described. We report an average daisy chain yield above 90% for die-to-die assemblies with CuSn bumps. Measurements were performed on a dedicated 1M bump area array test design with very long daisy chains of bumps on a 20μm pitch. Processing aspects like choice of plating seed layer, the influence of cleaning agents and seed layer etchants on the micro bump performance are being discussed. Finally, the impact on the daisy chain yield after thermal cycling is shown.

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Liu, Bingkai, Yudong Li, Lin Wen, et al. "Study of dark current random telegraph signal in proton-irradiated backside illuminated CMOS image sensors." Results in Physics 19 (December 2020): 103443. http://dx.doi.org/10.1016/j.rinp.2020.103443.

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6

Xu, C., C. Shen, W. Wu, and M. Chan. "Backside-Illuminated Lateral PIN Photodiode for CMOS Image Sensor on SOS Substrate." IEEE Transactions on Electron Devices 52, no. 6 (2005): 1110–15. http://dx.doi.org/10.1109/ted.2005.848106.

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7

Seok, Godeun, and Yunkyung Kim. "Front-Inner Lens for High Sensitivity of CMOS Image Sensors." Sensors 19, no. 7 (2019): 1536. http://dx.doi.org/10.3390/s19071536.

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Due to the continuing improvements in camera technology, a high-resolution CMOS image sensor is required. However, a high-resolution camera requires that the pixel pitch is smaller than 1.0 μm in the limited sensor area. Accordingly, the optical performance of the pixel deteriorates with the aspect ratio. If the pixel depth is shallow, the aspect ratio is enhanced. Also, optical performance can improve if the sensitivity in the long wavelengths is guaranteed. In this current work, we propose a front-inner lens structure that enhances the sensitivity to the small pixel size and the shallow pixel depth. The front-inner lens was located on the front side of the backside illuminated pixel for enhancement of the absorption. The proposed structures in the 1.0 μm pixel pitch were investigated with 3D optical simulation. The pixel depths were 3.0, 2.0, and 1.0 μm. The materials of the front-inner lens were varied, including air and magnesium fluoride (MgF2). For analysis of the sensitivity enhancement, we compared the typical pixel with the suggested pixel and confirmed that the absorption rate of the suggested pixel was improved by a maximum of 7.27%, 10.47%, and 29.28% for 3.0, 2.0, and 1.0 μm pixel depths, respectively.

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8

Vereecke, Bart, Celso Cavaco, Koen De Munck, et al. "Quantum efficiency and dark current evaluation of a backside illuminated CMOS image sensor." Japanese Journal of Applied Physics 54, no. 4S (2015): 04DE09. http://dx.doi.org/10.7567/jjap.54.04de09.

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9

Bingkai, Liu, Li Yudong, Wen Lin, et al. "Analysis of Dark Signal Degradation Caused by 1 MeV Neutron Irradiation on Backside‐Illuminated CMOS Image Sensors." Chinese Journal of Electronics 30, no. 1 (2021): 180–84. http://dx.doi.org/10.1049/cje.2020.12.002.

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10

Horie, Yu, Seunghoon Han, Jeong-Yub Lee, et al. "Visible Wavelength Color Filters Using Dielectric Subwavelength Gratings for Backside-Illuminated CMOS Image Sensor Technologies." Nano Letters 17, no. 5 (2017): 3159–64. http://dx.doi.org/10.1021/acs.nanolett.7b00636.

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11

Ngo, Nguyen Hoai, Kazuhiro Shimonomura, Taeko Ando, et al. "A Pixel Design of a Branching Ultra-Highspeed Image Sensor." Sensors 21, no. 7 (2021): 2506. http://dx.doi.org/10.3390/s21072506.

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A burst image sensor named Hanabi, meaning fireworks in Japanese, includes a branching CCD and multiple CMOS readout circuits. The sensor is backside-illuminated with a light/charge guide pipe to minimize the temporal resolution by suppressing the horizontal motion of signal carriers. On the front side, the pixel has a guide gate at the center, branching to six first-branching gates, each bifurcating to second-branching gates, and finally connected to 12 (=6×2) floating diffusions. The signals are either read out after an image capture operation to replay 12 to 48 consecutive images, or continuously transferred to a memory chip stacked on the front side of the sensor chip and converted to digital signals. A CCD burst image sensor enables a noiseless signal transfer from a photodiode to the in-situ storage even at very high frame rates. However, the pixel count conflicts with the frame count due to the large pixel size for the relatively large in-pixel CCD memory elements. A CMOS burst image sensor can use small trench-type capacitors for memory elements, instead of CCD channels. However, the transfer noise from a floating diffusion to the memory element increases in proportion to the square root of the frame rate. The Hanabi chip overcomes the compromise between these pros and cons.

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12

Lee, Jong-Kwon, Ahreum Kim, Dong-Wan Kang та Byung Yang Lee. "Efficiency enhancement in a backside illuminated 112 μm pixel CMOS image sensor via parabolic color filters". Optics Express 24, № 14 (2016): 16027. http://dx.doi.org/10.1364/oe.24.016027.

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13

Miyauchi, Ken, Kazuya Mori, Toshinori Otaka та ін. "A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel". Sensors 20, № 2 (2020): 486. http://dx.doi.org/10.3390/s20020486.

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A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than −140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved.

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14

Takayanagi, Isao, Ken Miyauchi, Shunsuke Okura, Kazuya Mori, Junichi Nakamura, and Shigetoshi Sugawa. "A 120-ke− Full-Well Capacity 160-µV/e− Conversion Gain 2.8-µm Backside-Illuminated Pixel with a Lateral Overflow Integration Capacitor." Sensors 19, no. 24 (2019): 5572. http://dx.doi.org/10.3390/s19245572.

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In this paper, a prototype complementary metal-oxide-semiconductor (CMOS) image sensor with a 2.8-μm backside-illuminated (BSI) pixel with a lateral overflow integration capacitor (LOFIC) architecture is presented. The pixel was capable of a high conversion gain readout with 160 μV/e− for low light signals while a large full-well capacity of 120 ke− was obtained for high light signals. The combination of LOFIC and the BSI technology allowed for high optical performance without degradation caused by extra devices for the LOFIC structure. The sensor realized a 70% peak quantum efficiency with a normal (no anti-reflection coating) cover glass and a 91% angular response at ±20° incident light. This 2.8-μm pixel is potentially capable of higher than 100 dB dynamic range imaging in a pure single exposure operation.

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15

Han, Chang-Fu, Jiun-Ming Chiou, and Jen-Fin Lin. "Deep Trench Isolation and Inverted Pyramid Array Structures Used to Enhance Optical Efficiency of Photodiode in CMOS Image Sensor via Simulations." Sensors 20, no. 11 (2020): 3062. http://dx.doi.org/10.3390/s20113062.

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The photodiode in the backside-illuminated CMOS sensor is modeled to analyze the optical performances in a range of wavelengths (300–1100 nm). The effects of changing in the deep trench isolation depth (DTI) and pitch size (d) of the inverted pyramid array (IPA) on the peak value (OEmax.) of optical efficiency (OE) and its wavelength region are identified first. Then, the growth ratio (GR) is defined for the OE change in these wavelength ranges to highlight the effectiveness of various DTI and d combinations on the OEs and evaluate the OE difference between the pixel arrays with and without the DTI + IPA structures. Increasing DTI can bring in monotonous OEmax. increases in the entire wavelength region. For a fixed DTI, the maximum OEmax. is formed as the flat plane (d = 0 nm) is chosen for the top surface of Si photodiode in the RGB pixels operating at the visible light wavelengths; whereas different nonzero value is needed to obtain the maximum OEmax. for the RGB pixels operating in the near-infrared (NIR) region. The optimum choice in d for each color pixel and DTI depth can elevate the maximum GR value in the NIR region up to 82.2%.

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16

Shike, Hiroya, Rihito Kuroda, Ryota Kobayashi, et al. "A Global Shutter Wide Dynamic Range Soft X-Ray CMOS Image Sensor With Backside- Illuminated Pinned Photodiode, Two-Stage Lateral Overflow Integration Capacitor, and Voltage Domain Memory Bank." IEEE Transactions on Electron Devices 68, no. 4 (2021): 2056–63. http://dx.doi.org/10.1109/ted.2021.3062576.

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17

Matthias, Thorsten, Thomas Uhrmann, Viorel Dragoi, Thomas Wagenleitner, and Paul Lindner. "Wafer Bonding for Backside Illuminated Image Sensors." ECS Transactions 44, no. 1 (2019): 1269–74. http://dx.doi.org/10.1149/1.3694458.

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18

Choi, Chung Seok, Sang Chul Yeo, Dohwan Kim, Jongchae Kim, Kyung Dong Yoo, and Hyuck Mo Lee. "Study of Shallow Backside Junctions for Backside Illumination of CMOS Image Sensors." Journal of Electronic Materials 43, no. 11 (2014): 3933–41. http://dx.doi.org/10.1007/s11664-014-3336-6.

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19

Hung, Yung-Jr, Meng-Syuan Cai, Jia-Fa Chen, et al. "High-Voltage Backside-Illuminated CMOS Photovoltaic Module for Powering Implantable Temperature Sensors." IEEE Journal of Photovoltaics 8, no. 1 (2018): 342–47. http://dx.doi.org/10.1109/jphotov.2017.2775440.

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20

Yao, Hong Tao, Zi Qiang Wang, Yuan Bao Gu, and Zhen Gang Jiang. "Analysis of Black Level Calibration Algorithm for CIS." Applied Mechanics and Materials 599-601 (August 2014): 1397–402. http://dx.doi.org/10.4028/www.scientific.net/amm.599-601.1397.

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This paper presents the structure and the operational principle of CMOS image sensors. And then the reason is illuminated for producing dark current and black level of CMOS image sensors. It is necessary to calibrate dark current and black level to improve quality of CMOS image sensors. The dark current is corrected by optimizing pixel structure, perfecting technology, improving 6layout, and correction double sample. But these ways do not calibrate black level. So, it is important to calibrate black level using black level calibration algorithm in the stage of image processing.

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21

Cavaco, C., L. Peng, F. Sebaai, et al. "On the Fabrication of Backside Illuminated Image Sensors: Bonding Oxide, Edge Trimming and CMP Rework Routes." ECS Transactions 64, no. 40 (2015): 123–29. http://dx.doi.org/10.1149/06440.0123ecst.

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22

Vici, Andrea, Felice Russo, Nicola Lovisi, Aldo Marchioni, Antonio Casella, and Fernanda Irrera. "Performance and Reliability Degradation of CMOS Image Sensors in Back-Side Illuminated Configuration." IEEE Journal of the Electron Devices Society 8 (2020): 765–72. http://dx.doi.org/10.1109/jeds.2020.2986729.

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23

Nguyen, Anh, Vu Dao, Kazuhiro Shimonomura, Kohsei Takehara, and Takeharu Etoh. "Toward the Ultimate-High-Speed Image Sensor: From 10 ns to 50 ps." Sensors 18, no. 8 (2018): 2407. http://dx.doi.org/10.3390/s18082407.

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The paper summarizes the evolution of the Backside-Illuminated Multi-Collection-Gate (BSI MCG) image sensors from the proposed fundamental structure to the development of a practical ultimate-high-speed silicon image sensor. A test chip of the BSI MCG image sensor achieves the temporal resolution of 10 ns. The authors have derived the expression of the temporal resolution limit of photoelectron conversion layers. For silicon image sensors, the limit is 11.1 ps. By considering the theoretical derivation, a high-speed image sensor designed can achieve the frame rate close to the theoretical limit. However, some of the conditions conflict with performance indices other than the frame rate, such as sensitivity and crosstalk. After adjusting these trade-offs, a simple pixel model of the image sensor is designed and evaluated by simulations. The results reveal that the sensor can achieve a temporal resolution of 50 ps with the existing technology.

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24

Doyen, Célestin, Stéphane Ricq, Pierre Magnan, Olivier Marcelot, Marios Barlas, and Sébastien Place. "Electrical Characterization of the Backside Interface on BSI Global Shutter Pixels with Tungsten-Shield Test Structures on CDTI Process." Sensors 20, no. 1 (2020): 287. http://dx.doi.org/10.3390/s20010287.

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A new methodology is presented using well known electrical characterization techniques on dedicated single devices in order to investigate backside interface contribution to the measured pixel dark current in BSI CMOS image sensors technologies. Extractions of interface states and charges within the dielectric densities are achieved. The results show that, in our case, the density of state is not directly the source of dark current excursions. The quality of the passivation of the backside interface appears to be the key factor. Thanks to the presented new test structures, it has been demonstrated that the backside interface contribution to dark current can be investigated separately from other sources of dark current, such as the frontside interface, DTI (deep trench isolation), etc.

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Chang, Yu-Chi, Cheng-Hsuan Lin, Zong-Ru Tu, et al. "0.8 um Color Pixels with Wave-Guiding Structures for Low Optical Crosstalk Image Sensors." Electronic Imaging 2021, no. 7 (2021): 93–1. http://dx.doi.org/10.2352/issn.2470-1173.2021.7.iss-093.

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Low optical-crosstalk color pixel scheme with wave-guiding structures is demonstrated in a high resolution CMOS image sensor with a 0.8um pixel pitch. The high and low refractive index configuration provides a good confinement of light waves in different color channels in a quad Bayer color filter array. The measurement result of this back-side illuminated (BSI) device exhibits a significant lower color crosstalk with enhanced SNR performance, while the better angular response and higher angular selectivity of phase detection pixels also show the suitability to a new generation of small pixels for CMOS image sensors.

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26

Jung, Chung Kyung, Sung Wook Joo, Seoung Hun Jeong, et al. "A Comparative Study for the Backside Illumination (BSI) Technology Using Bonding Wafer Cleaning Process for Advanced CMOS Image Sensor." Solid State Phenomena 195 (December 2012): 75–78. http://dx.doi.org/10.4028/www.scientific.net/ssp.195.75.

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Over the last decades, the concept of backside illumination (BSI) sensors has become one of the leading solutions to optical challenges such as improved quantum efficiency (QE), and cross-talk, respectively [1-. Direct wafer bonding is a method for fabricating advanced substrates for micro-electrochemical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer.

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27

Zhang, Xiang, Yu-Dong Li, Lin Wen, et al. "Radiation Effects Due to 3MeV Proton Irradiations on Back-Side Illuminated CMOS Image Sensors." Chinese Physics Letters 35, no. 7 (2018): 074201. http://dx.doi.org/10.1088/0256-307x/35/7/074201.

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28

Sun, Yu, Ping Zhang, Jiangtao Xu, Zhiyuan Gao, and Chao Xu. "Full well capacity and quantum efficiency optimization for small size backside illuminated CMOS image pixels with a new photodiode structure." Journal of Semiconductors 33, no. 12 (2012): 124006. http://dx.doi.org/10.1088/1674-4926/33/12/124006.

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29

Coudrain, Perceval, Pierre Magnan, Perrine Batude, et al. "Investigation of a Sequential Three-Dimensional Process for Back-Illuminated CMOS Image Sensors With Miniaturized Pixels." IEEE Transactions on Electron Devices 56, no. 11 (2009): 2403–13. http://dx.doi.org/10.1109/ted.2009.2030990.

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30

Enquist, Paul. "Low Temperature Direct Bond Technology for 3D Microelectronics Integration and Wafer Scale Packaging." International Symposium on Microelectronics 2010, no. 1 (2010): 000015–22. http://dx.doi.org/10.4071/isom-2010-ta1-paper3.

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3D microelectronics integration and wafer scale packaging promise improvements in functional density and cost compared to conventional 2D microelectronics and packaging technologies. The realization of these improvements will require further adoption of 3D volume manufacturing process technologies. These process technologies will likely include through silicon via (TSV) and die or wafer bonding with and without 3D interconnect. Low temperature direct bond technologies have a number of inherent performance and cost advantages compared to other bonding technologies. This paper describes low temperature direct oxide bond technologies with and without a scalable 3D interconnect developed by Ziptronix and cost savings, performance and applications that will be enabled by adoption of these technologies. Enabled cost savings and performance include system or network-on-chip, system in package, and TSVs. Enabled applications include backside illuminated image sensors, micron-scale pitch vertically integrated image sensor arrays, 3D system-on-chip and 3D network-on-chip.

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31

Oh, Minseok, Sergey Velichko, Scott Johnson, et al. "Automotive 3.0 µm Pixel High Dynamic Range Sensor with LED Flicker Mitigation." Sensors 20, no. 5 (2020): 1390. http://dx.doi.org/10.3390/s20051390.

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We present and discuss parameters of a high dynamic range (HDR) image sensor with LED flicker mitigation (LFM) operating in automotive temperature range. The total SNR (SNR including dark fixed pattern noise), of the sensor is degraded by floating diffusion (FD) dark current (DC) and dark signal non-uniformity (DSNU). We present results of FD DC and DSNU reduction, to provide required SNR versus signal level at temperatures up to 120 °C. Additionally we discuss temperature dependencies of quantum efficiency (QE), sensitivity, color effects, and other pixel parameters for backside illuminated image sensors. Comparing +120 °C junction vs. room temperature, in visual range we measured a few relative percent increase, while in 940 nm band range we measured 1.46x increase in sensitivity. Measured change of sensitivity for visual bands—such as blue, green, and red colors—reflected some impact to captured image color accuracy that created slight image color tint at high temperature. The tint is, however, hard to detect visually and may be removed by auto white balancing and temperature adjusted color correction matrixes.

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32

Douix, Maurin, Axel Crocherie, and Bastien Mamdy. "Back-side illuminated optical stack optimized with a high refractive index micro-lens array for CMOS image sensors." OSA Continuum 4, no. 6 (2021): 1801. http://dx.doi.org/10.1364/osac.423031.

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Thomas, Dave, Jean Michailos, Nicolas Hotellier, et al. "Integration Aspects of the Implementation of Through Silicon Vias (TSV) for CMOS Image Sensors." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (2010): 000539–56. http://dx.doi.org/10.4071/2010dpc-ta14.

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One of the first device types to benefit from TSV implementation is the CMOS image sensor, an image capture device designed to combine high image quality within a compact form-factor that can be mass produced at low cost. End markets include mobile phones, PDAs and gaming consoles. STMicroelectronics is pioneering their production, based on ≤65nm CMOS technology, at its 300mm facility in Crolles. These sensors employ TSVs as part of a wafer level package allowing the camera module to be directly soldered to a phone PCB thereby saving cost, space and time to manufacture. SPTS's Versalis fxP system is being used to combine multiple TSV formation processes onto one platform including hard-mask deposition, hard-mask etching, TSV etching, partial PMD etching, dielectric liner deposition and spacer etching to define the area for the metal contact. All processes are carried out on a silicon wafer bonded to a glass carrier, through which the final device is illuminated. We will present a TSV silicon etch process for 70 μm x 70 μm Vias in a thinned 300mm silicon wafer on glass carriers with an etch rate uniformity of ≤±1% and sidewall scalloping in the range 80–210 nm. We will show that this process can be conveniently mixed in production with the various oxide etches. A PECVD dielectric liner deposited at &lt;200 °C having excellent coverage, thermal stability and adhesion combined with a breakdown voltage &gt;8 MVcm−1 and leakage current &lt;1E-7 Acm−2 will also be described. Process integration aspects will be discussed using high resolution SEMS to show the key material interfaces in critical areas such as feature corners and along sidewalls. Furthermore the successful implementation of TSV technology on ST's CMOS image sensors will be demonstrated through a combination of electrical characteristics, parametric device data and overall device performance/reliability.

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34

Jobert, Gabriel, Pierre Barritault, Maryse Fournier, et al. "Miniature Optical Particle Counter and Analyzer Involving a Fluidic-Optronic CMOS Chip Coupled with a Millimeter-Sized Glass Optical System." Sensors 21, no. 9 (2021): 3181. http://dx.doi.org/10.3390/s21093181.

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Our latest advances in the field of miniaturized optical PM sensors are presented. This sensor combines a hybrid fluidic-optronic CMOS (holed retina) that is able to record a specific irradiance pattern scattered by an illuminated particle (scattering signature), while enabling the circulation of particles toward the sensing area. The holed retina is optically coupled with a monolithic, millimeter-sized, refracto-reflective optical system. The latter notably performs an optical pre-processing of signatures, with a very wide field of view of scattering angles. This improves the sensitivity of the sensors, and simplifies image processing. We report the precise design methodology for such a sensor, as well as its fabrication and characterization using calibrated polystyrene beads. Finally, we discuss its ability to characterize particles and its potential for further miniaturization and integration.

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35

Dragoi, Viorel, Gerald Mittendorfer, Alexander Filbert, and Markus Wimplinger. "Wafer Bonding for Backside Illuminated CMOS Image Sensors Fabrication." MRS Proceedings 1249 (2010). http://dx.doi.org/10.1557/proc-1249-f08-06.

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AbstractBackside illuminated CMOS image sensors were developed in order to encompass the pixel area limitation due to metal interconnects. In this technology the fully processed CMOS wafer is bonded to a blank carrier wafer and then back-thinned in order to open the photosensitive sensor area. The process flows of the two main competing wafer bonding technologies used for this manufacturing process (adhesive bonding and low temperature plasma activated direct wafer bonding with polymer layers) will be reviewed.

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36

"A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices." IEEE Transactions on Device and Materials Reliability 14, no. 2 (2014): 715–20. http://dx.doi.org/10.1109/tdmr.2014.2311887.

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37

AIT FQIR ALI-GUERRY, Zahra, Karim HUET, Didier DUTARTRE, et al. "Non-melt Laser Thermal Annealing of Shallow Boron Implantation for Back Surface Passivation of Backside-Illuminated CMOS Image Sensors." MRS Proceedings 1321 (2011). http://dx.doi.org/10.1557/opl.2011.808.

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ABSTRACTBack surface passivation is one of the major challenges in the backside illuminated sensor technology. Ion implantation followed by non-melt pulsed Laser Thermal Annealing (LTA) has been identified as a promising candidate to address this issue. In this work, a shallow B-doped layer is implanted at the backside, further activated using LTA in the non-melt regime. LTA process effectiveness in terms of crystal damage recovery as well as dopant diffusion and activation is studied through room-temperature photoluminescence, Secondary Ion Mass Spectroscopy and four-point probe sheet resistance. These studies demonstrate that non-melt LTA with multiple pulses induces high activation without visible diffusion with an effective curing of the implantation-induced crystalline defects. This is made possible thanks to a submicrosecond process timescale coupled to a reasonable number of shots as shown by thermal simulations and simple diffusion estimations.

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38

Na, Heedo, Jimin Lee, Juyoung Jeong, Taeho Kim, and Hyunchul Sohn. "Effect of interfacial SiO2−y layer and defect in HfO2−x film on flat-band voltage of HfO2−x/SiO2−y stacks for backside-illuminated CMOS image sensors." Applied Physics A 124, no. 3 (2018). http://dx.doi.org/10.1007/s00339-018-1659-5.

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"On the Fabrication of Backside Illuminated Image Sensors: Bonding Oxide, Edge Trimming and CMP Rework Routes." ECS Meeting Abstracts, 2014. http://dx.doi.org/10.1149/ma2014-02/33/1713.

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"The Impacts of Back-Surface Passivation Using Shallow Ion Implantation and Pulsed Laser Thermal Annealing on Back-Illuminated CMOS Image Sensors Performances: Physical and Electrical Characterizations." ECS Meeting Abstracts, 2011. http://dx.doi.org/10.1149/ma2011-02/45/2604.

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