Dissertations / Theses: 'Ball grid array technology'

1

Liang, Hongwei. "Development of microwave and millimeter-wave pin grid array and ball grid array packages." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14867.

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2

Elkady, Yasser Ahmed Suhling J. C. Knight Roy Ward. "Thermal performance of ball grid arrays and thin interface materials." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/doctoral/EL-KADY_YASSER_48.pdf.

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3

Song, Fubin. "Experimental investigation on testing conditions of solder ball shear and pull tests and the correlation with board level mechanical drop test /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?MECH%202007%20SONG.

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Jordy, Daniel Edward. "Computational drop testing of printed circuit boards with BGA components." Diss., Online access via UMI:, 2007.

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5

Lui, Hoi Wai. "Experimental evaluation of board level solder joint reliability of plastic ball grid array assemblies with eutectic Pb-Sn and Pb-free solders /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?MECH%202003%20LUI.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003. Includes bibliographical references (leaves 103-114). Also available in electronic version. Access restricted to campus users.

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6

Panchagade, Dhananjay R. "Damage prediction of lead free ball grid array packages under shock and drop environment." Auburn, Ala., 2007. http://repo.lib.auburn.edu/2007%20Spring%20Dissertations/PANCHAGADE_DHANANJAY_35.pdf.

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7

Lau, Chung Yin. "Computational stress analysis for ball grid array reliability and passive component reliability in board level assemblies /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?MECH%202005%20LAU.

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8

Drake, Jonathan Luke Lall Pradeep. "Thermo-mechanical reliability models for life prediction of ball grid arrays on Cu-core PCBs in extreme environments." Auburn, Ala., 2007. http://hdl.handle.net/10415/1400.

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9

Huang, Xingjia. "Investigation and analysis on the solder ball shear strength of plastic ball grid array, chip scale, and flip chip packages with eutectic Pb-Sn and Pb-free solders /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?MECH%202003%20HUANG.

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10

Hariharan, Ganesh Lall Pradeep. "Models for thermo-mechanical eliability trade-offs for ball grid array and flip chip packages in extreme environments." Auburn, Ala., 2007. http://repo.lib.auburn.edu/2006%20Fall/Theses/HARIHARAN_GANESH_55.pdf.

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11

Mitchell, Charles Clayton. "PBGA reliability of lead free solder balls assembled with tin lead solder paste for harsh environment electronics." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Summer/Theses/MITCHELL_CHARLES_16.pdf.

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12

Rivers, Norman. "An investigation of BGA electronic packaging using Moiré interferometry." [Tampa, Fla. : s.n.], 2003. http://purl.fcla.edu/fcla/etd/SFE0000078.

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13

Reichman, Aaron Michael. "Development of nano-characterization system for polymer film measurement and single BGA solder joint forming experiment." Diss., Online access via UMI:, 2007.

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14

Tunga, Krishna Rajaram. "Experimental and Theoretical Assessment of PBGA Reliability in Conjunction with Field-Use Conditions." Thesis, Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5266.

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With the dramatic advances that have taken place in microelectronics over the past three decades, ball-grid array (BGA) packages are increasingly being used in microsystems applications. BGA packages with area-array configuration have several advantages: smaller footprint, faster signal transmission, testability, reworkability, handling easiness, etc. Although ceramic ball grid array (CBGA) packages have been used extensively in the microsystems industry, the use of plastic ball grid array (PBGA) packages is relatively new, especially for automotive and aerospace applications where harsh thermal conditions prevail. This thesis work has developed an experimental and a theoretical modeling program to study the reliability of two PBGA packages. The physics-based theoretical models take into consideration the time-dependent creep behavior through power law creep and time-independent plastic behavior through multi-linear kinematic hardening. In addition, unified viscoplastic constitutive models are also taken into consideration. The models employ two damage-metrics, namely inelastic strain and inelastic strain energy density, to predict the solder joint fatigue life. The theoretical predictions have been validated through air-to-air in-house thermal cycling tests carried out between 55 and #61616;C and 125 and #61616;C. In addition, laser-moir interferometry has been used to determine the displacement contours in a cross-section of the package at various temperatures. These contours measured through moir interferometry have also been used to validate the thermally-induced displacement contours, predicted by the models. Excellent agreement is seen between the experimental data and the theoretical predictions. In addition to life prediction, the models have been extended to map the field-use conditions with the accelerated thermal cycling conditions. Both linear and non-linear mapping techniques have been developed employing inelastic strain and strain energy density as the damage metric. It is shown through this research that the symmetric MIL-STD accelerated thermal cycles, currently in practice in industry, have to be modified to account for the higher percentage of creep deformation experienced by the solder joints in the field-use conditions. Design guidelines have been developed for such modifications in the accelerated thermal cycles.

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Shirgaokar, Aniket Lall Pradeep. "Principal component regression models for thermo-mechanical reliability of plastic ball grid arrays on CU-core and no CU-core PCB assemblies in harsh environments." Auburn, Ala., 2009. http://hdl.handle.net/10415/1745.

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16

Majeed, Sulman. "Rework & reliability of area array components." Diss., Online access via UMI:, 2009.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engfineering and Applied Science, Department of Systems Science and Industrial Engineering, 2009. Includes bibliographical references.

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17

Selli, Giuseppe. "BGA footprints modeling and physics based via models validation for power and signal integrity applications." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Selli_09007dcc8040f1b6.pdf.

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Thesis (Ph. D.)--University of Missouri--Rolla, 2007. Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed December 7, 2007). Includes bibliographical references.

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18

Bukhari, Sarfaraz. "Evaluation of the effects of processing conditions on shear strength in Pb-free surface mount assembly." Diss., Online access via UMI:, 2004. http://wwwlib.umi.com/dissertations/fullcit/1422361.

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19

Ng, Siu Lung. "Effect of thermal and mechanical factors on single and multi-chip BGA packages." Diss., Online access via UMI:, 2007.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007. Includes bibliographical references.

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20

Tang, Zhenming. "Interfacial reliability of Pb-free flip-chip BGA package." Diss., Online access via UMI:, 2008.

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Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008. Includes bibliographical references.

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21

Yunusa, Valeri Aisha. "Reliability of Solder Joints in Embedded Packages Using Finite Element Methods." PDXScholar, 2018. https://pdxscholar.library.pdx.edu/open_access_etds/4558.

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Solder joints serve as both mechanical and electrical connections between elements in a package. They are subjected to shear strains generated as a result of the different behaviors of the elements in the package (tension and compression) due to the differences in coefficients of thermal expansion during service conditions. Some of the causes of solder joint failures are due to the following: Vibration: small rapid displacements of parts of the assembly. This is not necessarily an issue with electronic components but larger parts like automobiles. Humidity: the package being exposed to water or ionic species can undergo corrosion if an electrical bias exists resulting in electrical opens or electrical shorts if the corrosion products are electrically conductive. Thermal Aging: this occurs during the lifetime of the solder interconnects, the package can be exposed to high ambient temperature or high dissipated heat during use. The micro-structure of the solder joint becomes more coarse and brittle. Mechanical Shock: the package undergoes shock during a short term exposure to high loads. Thermo-mechanical fatigue: this type of failure arises as a result of the solder joints going through cyclic strains, due to different coefficients of thermal expansion of individual components in the package during service. The most prevalent long-term reliability issues that can cause interconnect failure are thermal aging and thermo-mechanical fatigue. This study aims to evaluate the reliability of solder joints using finite element method, considering solder joint failure due to thermo-mechanical fatigue. Three variations of the BGA (Ball Grid Array) package are evaluated using the finite element analysis. The SAC305 series lead (pb) free alloy of 96.5% tin, 3% silver, and 0.5% copper is employed for this study.

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Tunga, Krishna Rajaram. "Study of Sn-Ag-Cu reliability through material microstructure evolution and laser moire interferometry." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24805.

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23

Tumne, Pushkraj Satish. "Investigation of bulk solder and intermetallic failures in PB free BGA by joint level testing." Diss., Online access via UMI:, 2009.

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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department or Systems Science and Industrial Engineering, 2009. Includes bibliographical references.

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24

Bergman, Robin, and Johan Nilsson. "Utvärdering av JTAG Boundary scan somtestmetod vid temperaturchocker." Thesis, KTH, Hållbar produktionsutveckling (ML), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-286255.

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Rapporten beskriver ett examensarbete som har genomförts hos Scania R&D. Målet har varit att testa om det är möjligt att använda JTAG för kontroll av Ball Grid Array på komponenter som sitter på kretskort. Vanliga mätmetoder kan inte användas med mindre än att man separerar komponenten från kretskortet. Det som framkommer är att JTAG kan användas för att kontrollera Ball Grid Array samtidigt som kretskortet finns i ett så kallat temperaturchockskåp (som används för att testa hur utrustning och komponenter reagerar vid snabba temperaturändringar). Svårigheten består att den flatkabel som för över signaler mellan dator och kretskort är så lång att arrangemanget blir störningskänsligt. Detta kan lösas med en Extender som förstärker signalen så att kabeln kan vara längre än 0,5 meter. Resultat visar att JTAG kan användas med kretskort som befinner sig i temperaturchockskåpet. Målet har även varit att utveckla en kontrollmetod för att kontrollera att det kretskort som levereras till Scania uppfyller kraven i ISO 26262. För att kunna kontrollera om en leverantör uppfyller ISO 26262 behövs dokumentation som verifierar att produkten utvecklats i enlighet med ISO 26262. I ISO standarden finns det tolv delar som beskriver kraven på produkten. I rapporten har fokus lagts på delen som handlar om hårdvara. Ingen kontrollmetod har kunnat utvecklats då ISO standarden var mer omfattade än väntat.

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25

Dhakal, Ramji. "Failure mechanism of lead-free Sn-Ag-Cu solder BGA interconnects." Diss., Online access via UMI:, 2005.

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26

Rivers, Norman. "An Investigation of BGA Electronic Packaging Moiré Interferometry." Scholar Commons, 2003. https://scholarcommons.usf.edu/etd/1459.

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As technology progresses towards smaller electronic packages, thermo-mechanical considerations pose a challenge to package designers. One area of difficulty is the ability to predict the fatigue life of the solder connections. To do this one must be able to accurately model the thermo-mechanical performance of the electronic package. As the solder ball size decreases, it becomes difficult to determine the performance of the package with traditional methods such as the use of strain gages. This is due to the fact that strain gages become limited in size and resolution and lack the ability to measure discreet strain fields as the solder ball size decreases. A solution to the limitations exhibited in strain gages is the use of Moiré interferometry. Moiré interferometry utilizes optical interferometry to measure small, in-plane relative displacements and strains with high sensitivity. Moiré interferometry is a full field technique over the application area, whereas a strain gage gives an average strain for the area encompassed by the gage. This ability to measure full field strains is useful in the analysis of electronic package interconnections; especially when used to measure strains in the solder ball corners, where failure is known to originate. While the improved resolution of the data yielded by the method of Moiré interferometry results in the ability to develop more accurate models, that is not to say the process is simple and without difficulties of it's own. Moiré interferometry is inherently susceptible to error due to experimental and environmental effects; therefore, it is vital to generate a reliable experimental procedure that provides repeatable results. This was achieved in this study by emulating and modifying established procedures to meet our specific application. The developed procedure includes the preparation of the specimen, the replication and transfer of the grids, the use of the PEMI, interpretation of results, and validation of data by finite element analysis using ANSYS software. The data obtained maintained uniformity to the extent required by the scope of this study, and potential sources of error have been identified and should be the subject of further research.

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27

Yoon, Sangwoong. "LC-tank CMOS Voltage-Controlled Oscillators using High Quality Inductor Embedded in Advanced Packaging Technologies." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4887.

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This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si and GaAs substrates. All the inductors are modeled with a physical, simple, equivalent two-port model for the VCO design as well as for phase noise analysis. The losses in an LC-tank are analyzed from the phase noise perspective. For the implementation of VCOs, the effects of the interconnection between the embedded inductor and the VCO circuit are investigated. The VCO using the on-chip inductors is designed as a reference. The performance of VCOs using the embedded inductor in a FBGA and a WLP is compared with that of a VCO using the on-chip inductor. The VCO design is optimized from the high-Q perspective to enhance performance. Through this optimization, less phase noise, lower power consumption, and a wider frequency tuning range are obtained simultaneously.

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Buřival, Tomáš. "Opravy DPS s BGA a FC pouzdry." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217906.

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Graduation thesis is specialized on dilemma of the integrated circuits with ball grid array. Chapter two describes several types of packages and confrontation of their characteristics. Chapter three considers possibilities of corrections these boards bedded with packages, mounting and demounting of these packages, method of camera control and also inspection of the soldering process. Chapter four attend to practical measuring of thermal profiles and their optimalization.

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29

Chilakamarthi, Geetha. "Influence of underfill on ball grid array (BGA) package fatigue life." ScholarWorks@UNO, 2004. http://louisdl.louislibraries.org/u?/NOD,102.

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Thesis (M.S.)--University of New Orleans, 2004. Title from electronic submission form. "A thesis ... in partial fulfillment of the requirements for the degree of Master of Science in the Department of Mechanical Engineering."--Thesis t.p. Vita. Includes bibliographical references.

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30

Qi, Haiyu. "Plastic ball grid array (PBGA) solder joint reliability assessment under combined thermal cycling and vibration loading conditions." College Park, Md. : University of Maryland, 2006. http://hdl.handle.net/1903/4099.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2006. Thesis research directed by: Mechanical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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31

Yang, Kai-Tang, та 楊凱棠. "Fabrication Technology For Micro Ball Grid Array Package (μBGA)". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/88842420354936314155.

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碩士 國立清華大學 電子工程研究所 88 This thesis is dedicated to research the Micro Ball Grid Array (μBGA) technology which can be used in package. When μBGA is used in bonding, different thermal expansion coefficient between different layers will cause a stress between the bonding place as thermal treatment, and then destruct the solder or device structure. In this thesis, we choose Benzocyclobutene (BCB) as the stress buffer layer and dielectric of the solder because of it's several advantage properties：low dielectric constant, low water absorption, low stress, and high bending strength which can efficiently increase the bonding reliability. We use Cr/Cr/Cu/Cu sandwich structure as the Under Bump Metallurgy (UBM) and the redistribution layer. Electroplated copper layer in sandwich structure can achieve enough thickness to be a efficient diffusion barrier. PbSn is deposited by E-Beam Evaporation and reflowed forming a solder. We will discuss the effect of time and temperature on reflow. Finally, we flip chip by solder and measure the relationship between resistance and temperature.

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32

Hsieh, SHUN-CHOU, and 謝順州. "Investigation into Cutting Technology during Flip Chip Ball Grid Array Assembly Process." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/80201457665537420172.

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碩士 國立高雄第一科技大學 機械與自動化工程研究所 102 For the past few years, semiconductor assembly is still one of the competitive products of high technical industry. With a view of high technical products’ chain, IC foundries, assembly and test subcontractors, modules assembly and SMT, produce and already overlap each other between the chains from beginning to end. Producing and researching on 2.5D / 3D IC have made industries chain cooperation and mutual symbiosis. Assembly houses must upgrade process capability and cost down plan that might to meet industries requirement. The faster of new technology the industry can apply, the more benefits and competitive abilities it can make. This research focuses on the assembly process of flipchip devices and its influence on quality promotion of Assembly industry. The study pays attention to the sawing manufacturing process of flipchip series products because sawing plays a key role in yield. The crucial parameters and the corresponding parameter’s range of the sawing process are obtained from engineers’ knowledge. The optimal parameter of sawing is determined by Taguchi method. The confirmation experiment verifies that the average pulling force has increased and the yield of sawing to be raised up to the goal.

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Chang, Wei-Na, and 張維娜. "Visual Inspection of Ball Grid Array Substrates." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/22572692875324408871.

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碩士 國立交通大學 電機與控制工程系所 92 In the early days, traditional inspection was done by using eyes of human operators, and therefore time consuming ,unreliable and expensive.Visual inspection system provides high speed, high quality and low labor cost, and has been widely adopted in today's industry. In the thesis, we propose a visual inspection method to inspect the surface of BGA substrates. The inspection method we developed is described as follows. First of all, we need to select a defect free image and use it to define a template image. Then we segment the template image into the bond finger regions and the power/ground ring region. Each single bond finger is divided into three regions : the major inspection region , the minor inspection region, and the short circuit inspection region. The parameters extracted from the template image are stored. After the template image builded, the inspected image is captured, and aligned with the template image. In the inspection process, the inspected image is inspected and compared to the template image to determine whether the object in the inspected image is defective or not. The outcome of the final experiment showed that our method could detect all defects defined in the BGA substrate criteria.

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Chen, Wei-chi, and 陳韋至. "Realizing Microstrip Patch Antenna Array on Ball Grid Array Package." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/96a773.

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35

Chen, Hsien-Cheng, and 陳縣成. "Electrical Characterization of Ball-Grid Array (BGA) Packaging." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/86630124930041095108.

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碩士 國立交通大學 電資學院學程碩士班 90 Packaging engineers have to work with die level designers to either create a package that performs well at high frequency or to use readily available low cost packages that happen to meet the needs of the application. First time success of a design is more important and models that help achieve this are becoming more valuable. In addition, the accurate models and the analysis method to use them in circuit simulations are more readily available. This paper explores the electrical characterization of ball-grid array (BGA) packaging.

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36

Shi, Hsi Ching, and 施新慶. "Thermal fatigue life analysis of solder ball for plastic ball grid array." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/04570494662760895555.

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碩士 國立清華大學 動力機械工程學系 85 Based on the advantages of finite element method,the variation of thermal strain and stress of the solder ball for Plastic Ball GridArray under specific thermal cycles has been studied. Due to the complicated geometries of the solder ball and surrounding components( for example, substrate, copper pad and PCB etc.), a highly efficientanalysis model which combines the merits of axisymmetric and 3-D elements is established. The effects of thermal cycling on the thermalfatigue life of the Sn63-Pb37 solder ball under elastic, elasto-plasticand elasto-plastic-creep analyses are then evaluated respectively. Bythe constructed formula for predicting the thermal fatigue life of the solder ball, the influence of solder ball shape ( sphere, cylinder andhourglass ) on the thermal fatigue life is also analyzed. The resultsshow that, under elasto-plastic-creep analysis, a cylindrical or an hourglass solder ball has longer fatigue life than a spherical solder ball.

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Chen-JungWong and 翁振榮. "Reliability of Flip Chip-Plastic Ball Grid Array Package." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/54558979279914245759.

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碩士 國立成功大學 機械工程學系碩博士班 100 We used Mechanic APDL(ANSYS 12.0) to build three types of the leaded(Sn37Pb) and lead-free(Sn3.8Ag0.7Cu) solder of the flip-chip plastic ball grid array. These three types are: Type1 (no heat spreader and no molding compound), Type2 (added molding compound with no heat spreader), Type3 (added heat spreader and molding compound).The model set the chip center as the original point, and both X and Y directions are Geometric symmetry, so that the model is a quarter of the entire model. There are totally 90 minutes to proceed the temperature cycling test(TCT) simulation with 30 minutes for each cycle. In the simulations, all the solder bumps and the solder balls are modeled as nonlinear visco-plastic, and time and temperature dependent material based on Anand's constitutive equation, and other materials are treated as linear elasticity. This study uses Modified Coffin-Manson To analyze the fatigue life of the solder joint with plastic strain results from finite element simulations, and finds out the maximum and minimum stress-load and thermal strain on the solder joint. Comparing the effect of fatigue life of leaded or non-leaded solder joint with different types was then performed in this thesis.

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Huang, Jung-Cheng, and 黃榮正. "Measuring Equipment Capability in Ball Grid Array Manufacturing Process." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/22703449133476867191.

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碩士 國立高雄應用科技大學 工業工程與管理系 97 Measuring and controlling equipment capability is an important issue in the Ball Grid Array (BGA) manufacturing process. This research strengthens the whole measuring framework for controlling BGA manufacturing equipment performance by combining failure tree analysis (FTA), equipment capability average ( ) and equipment capability standard deviation (s) control charts, consistent index for equipment capability average and specification mean (Ca), equipment capability deviation for standard product quality index (Cp), and data collection procedure and out of control action plan (OCAP). An equipment capability index Cmk for measuring BGA equipment performance is proposed. Using build-in functions of Microsoft Excel, we develop a convenient, easy and effective Cmk control system which automatically creates control chart and calculates equipment capability index evaluation system. In this Cmk control system, to validate the equipment ability and to serve for further improvement references, certain related criteria, such as machine failure time rate (MFTR), product yield loss defect (parts per millions; ppm), and maintenance cost are provided. Through this system, the related industry can simply follow the procedures and documents format provided in this research to create their own equipment evaluation system which can provide their process engineers an excellent tool to control process variations in the ever changing manufacturing processes.

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Lee, In-Shung, and 李英舜. "Crack Propagation in Plastic Ball Grid Array Electronic Packaging." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/11598909404028361534.

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Lin, Tzu-Jen, and 林子仁. "Solder Ball Thermal Fatigue and Mesh Model Analysis of Ball Grid Array Packages." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/17806958686325645942.

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碩士 國立雲林科技大學 機械工程系碩士班 93 The development of electronic product is toward lighter, thinner, shorter, higher power, and more functions, and the development of electronic package follows the same trend. The BGA (Ball Grid Array) package, designed for more I/O pins, is more popular nowadays. The solder ball induces high inelastic strain under thermal loading due to the thermal expansion mismatch between the package and PWB (Print Wire Board). The inelastic behavior of solder ball under thermal loading is the important issue of board level reliability. In this study, two chip scale Ball Grid Array Packages, Pb/Sn solder WL-CSP and lead free solder TF-BGA, are simulated by FEM software to predict the thermal fatigue of solder ball under thermal cycling loading. The convergence of solder mesh model is considered to assure the accuracy of the simulation. The material model of solder is set to be elastic-plastic-creep. The equation to predict the fatigue life of solder is based on both inelastic strain energy density and accumulated creep energy. The predicted fatigue life is compared with experimental data to verify the accuracy of the FEM model. The effect of geometric dimensions and material properties on the fatigue life of solder is discussed. Furthermore, the slice model of FEM is compared with the symmetric model to discuss the feasibility of using the slice model to predict the inelastic behavior of solder.

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41

Luo, Shi-Jie, and 羅仕杰. "Measurement of Ball Grid Array Coplanarity and Solder Ball Height with Stereo Vision." Thesis, 2019. http://ndltd.ncl.edu.tw/cgi-bin/gs32/gsweb.cgi/login?o=dnclcdr&s=id=%22107NCHU5415011%22.&searchmode=basic.

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碩士 國立中興大學 生物產業機電工程學系所 107 The purpose of this study is to measure ball height and coplanarity of Ball grid array solder. In this study, stereo vision camera is used to capture RGB image and corresponding height map of BGA. In order to reduce noises in image. Red and blue light sources are projected from two difference angles. Using two channels to get solder balls and plane respectively. The method can effectively reduce noises and get clear contour of solder balls. LTS method is used to finish circle fitting. In this study, the problem that histogram distribution close to unimodal is solved by an adjusted Otsu method. This study propose a multiple thresholds method. It can exclude outlier and remove white noises effectively. This study used multiple threads to save time. After test, used two threads can reduce 30% and three threads can reduce 50% of time. Precision can be reach 0.5~0.7 μm. it show this measurement is high consistency. About RMSE, they are between 2~8 μm. Convert absolute error to relative error, only sample A is higher error and others are around 1% in RMSE. It show the method is good measurement accuracy. The important contribution of this study is building a BGA measurement software. It cooperates with stereo vision camera to measure BGA. In the study, the algorithm were proposed to exclude noise and get the position height of BGA rapidly and efficiently.

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Ting, Huang, and 黃鼎焱. "Multi-objective Process Optimization of Sn-Ag-Cu Ball Mounting for Ball Grid Array." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/58075018105573380823.

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碩士 國立高雄第一科技大學 機械與自動化工程所 95 Lead-bearing solders, such as the PbSn eutectic, have been used extensively in the microelectronic industry for a long period of time. Recently, the European Union proposed to phase out the lead-bearing solders by January, 2008. Moreover, many major Japanese electronic companies, such as Panasonic and Fujitsu, have decided to switch voluntarily to lead-free processes by the year of 2002. It is generally believed that this lead-free transition is unevitable this time. Past research by the academia and industry indicated that a drop-in replacement for PbSn eutectic is difficult to find, if not impossible. Due to the extremely tight time schedule to go lead-free, the U.S. industry had reached a consensus to use SnAgCu series of solders to replace the PbSn eutectic, despite the fact that the literature for SnAgCu solders is still seriously lacking. The main objective of this proposal is then to study the reactions between such different composition lead-free solders with the IR-reflow parameter finish used in the industry. This research paper is focused on discussion of development of multiple quality characteristics optimisation in production procedure with use of Taguchi Method, fuzzy logic. The characteristics of this method are using Orthogonal Arrays (OAs) in order to decrease the experiment and obtain best quality in design. Further, this method also includes the characteristics of vague logics within questions transferring multiple quality characteristics into single measuring index. With use of factor analysis and variable number analysis, a best combination of index can be found out and linked to the design of reflective surface. Then, the change of surface which is constructed by tangible factor will be observed. It can be further to tell from the optimised point of index.

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鄭森勵. "Development and Estimation of a Ball Grid Array Inspection System." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/53162645502411047805.

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碩士 國立臺灣大學 機械工程學研究所 90 The aim of this study is to construct a prototype of a Precision 3D Measurement System for the Dimensional Inspection of BGA Components. The system includes 2D inspection on True Position Error, Pitch, Diameter and Board Edge, as well as 3D inspection on Coplanarity, Ball height and Board Warpage. The 2D part has been developed by using a CCD(charge coupled device) and a circular LED light source. Through the application of Blob Analysis method, sub-pixel edge detection and least square circle, those characteristics we want to inspect can be found. On the 3D inspection a micro focus laser line was adopted to project onto the BGA surface. With image processing technique it can convert to 3D image currently.

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Lin, Yung-Chia, and 林詠嘉. "A 2-Layer Global Router for Ball Grid Array Packages." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/83355502905733391903.

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碩士 國立清華大學 資訊工程學系 95 As the manufacturing technology keeps shrinking, the number of I/O pins in a current VLSI design has easily grown to hundreds, or even thousands. With the pressing need of connecting the huge number of I/O pins to a PCB (Printed Circuit Board), a BGA (Ball Grid Array) package is used mostly nowadays. In this thesis, we propose a two-layer BGA global routing algorithm which routes the net in the order of fingers one at a time while considering the minimization of the total wirelength and overflow. Our algorithm begins with constructing a routing graph and assigning a parameter which represents the maximum overflow tolerance initialized to 0. Our algorithm then extracts a routing subgraph from the routing graph for each net based on the viewpoint of planar routing. Our algorithm next routes nets one at a time on their respective routing subgraphs. If our algorithm cannot find a routing path from a finger to a ball on the given routing subgraph, our algorithm will expand the routing subgraph and try to route again until our algorithm find a routing path or the number of expanding times reaches the user-specified upper bound. A history cost is introduced to make our routing algorithm avoid constructing routing paths through grids which are overflowed during previous iteration. Once it is found that our algorithm cannot finish routing a net, our algorithm will increase the maximum overflow tolerance by one and restart the whole routing process. The experimental results show that our algorithm averagely decreases 96.8% total overflow and 83.33% maximum overflow as compared to a most recent work. Besides, our algorithm produces smaller total wirelength and runs 4.39 times faster.

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Chou, Cheng-Hung, and 周建宏. "Coplanarity Inspection of Ball Grid Array Using Phase-Shifted Interferometry." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/25448365204433647714.

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碩士 國立成功大學 電機工程學系 88 In order to increase the functionality of IC-chips, the requirement of high pin count was also increased. Then the BGA packaging technique was developed and used widely. The major problem of surface mounting is the coplanarity of the BGA solder balls. Poor coplanarity causes an open circuit, and reduces the reliability. The high-resolution surface profile of the ball grid array (BGA) is obtained by measurement of the phase distribution across the image of a projected sinusoidal grating deformed by the surface. A shearing polarization interferometer is used for projection. When a sinusoidal grating is projected on either a reference plane or a BGA object to be measured, every point along a line normal to the grating lines, on the reference plane as well as the object, can be characterized by a unique phase value. By measuring this phase accurately using phase modulation methods and by determining the phase differences of points on the reference plane and the object, it is shown that the object height can be computed. A coplanarity inspection process of the BGA is also proposed. By a blob search of a 2-D image, the locations of the BGA solder balls can be determined. And the height of solder balls are also be determined by the PSI method. The coplanarity was calculated.

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Hsu, Yung-hsing, and 徐永興. "Mold Flow and Thermal Analysis of Ball Grid Array Packages." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/22012935201528940896.

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碩士 國立雲林科技大學 機械工程系碩士班 93 The mold flow software C-MOLD and Moldflow are used to simulate the flow behavior of Fine-Pitch Ball Grid Array （FBGA） package during encapsulation. The molding behavior during encapsulation for different chip thicknesses and offsets of hole on the substrate are discussed. The wave front shape predicted by simulation is compared with the shape by short shot experiment to verify the accuracy of the simulation model. The wire sweep during the encapsulation is predicted by C-MOLD, Moldflow, as well FEM software ANSYS, where the applied load is the drag force calculated by the acquisition of the flow viscosity and velocity from the mold flow simulation. The predictions of the wire sweep are compared with the experimental measurements. Also, the effects of chip thicknesses and offsets of hole on the substrate on the wave front difference between mold halves, wire sweep, and resin bleed are discussed. For the thermal analysis, the ANSYS software is used to build the FEM solid model and CFD fluid-thermal model of Micro Ball Grid Array Package （μBGA） to predict the thermal resistance of the package under the natural and forced convection, and the predicted thermal resistance is compared with the experimental measurement to verify the accuracy of the simulation. The averaged surface convection coefficients for both package and PCB （Printed Circuit Board） surfaces acquired from the CFD model are compared with the plate surface convection coefficients to show the difference. Furthermore, the effects of chip thickness, flow velocity, and PCB thickness on the thermal performance of the package are discussed.

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Yi-wei, Liu, and 劉怡威. "Thermal Analysis of Flip Chip -Plastic Ball Grid Array Assembly." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/51320434324780394856.

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碩士 元智大學 機械工程研究所 89 The steady-state thermal performance of the 164-Lead flip chip plastic ball grid array (FC-PBGA) under low to moderate convective air cooling conditions has been simulated through computational fluid dynamics (CFD) methods with CFX. Package with three different substrates were investigated. Package performance has been presented in the form of a linear relationship between the normalized junction to ambient thermal parameter (θJA) verses the normalized board to ambient thermal parameter (θJB). Results cast in the form represent a first order thermal figure of merit for packages. Such a figure of merit can be used to rank in a consistent manner the thermal performance of different package types.

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欽, 林. 文. "Ball Grid array (BGA) Failure analysis for Semiconductor Packaging Process." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/40438364220370550753.

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Chang, Hsin-Yu, and 張馨予. "Irregular Bumps Design Planning for Modern Ball Grid Array Packages." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/jpvr56.

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碩士 國立交通大學 電子研究所 107 In modern flip-chip packages, bumps are often placed irregularly due to different design needs. It costs a great amount of time and manual effort to generate substrate routing from bumps through vias to package balls. Moreover, any single model in prior works could not be simultaneously applied between bumps, vias and balls. In this work, we propose a hybrid flow network model to formulate the 2-layer substrate routing problem on irregular package structure. We present a new bump model that can handle irregular bump plans. With our methodology, signal assignment on vias and balls, and substrate routing on two layers can be obtained at the same time. We also present an iterative optimization technique to improve wire congestion. Our results show that the proposed method completes via and ball assignment efficiently, and obtain 100% routability and an average wirelength improvement of 16.45%, compared with manual design in real industrial cases.

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Ho, Cheng-I., and 何承益. "The Thermal Analysis and Optimization for Ball Grid Array Package." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/e3e94k.

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碩士 國立成功大學 機械工程學系碩博士班 90 With the rapid development of technology, the trend of electronic products getting smaller and multi-functional. Therefore, it is better to design an electronic product with high heat dissipation. In this study, the computational fluid dynamics approach is employed to analyze the heat transfer for ball grid array (BGA) package that is popular in modern electronic industry. Due to the complicate geometric configuration of BGA, the sub-model approach is used to simulate the temperature distributions of thermal vias and solder balls with maintaining the physics in this study. The effective thermal resistance of BGA package is then obtained from numerical simulations. An artificial neural network is trained to build up the relation between input geometry and output thermal resistance. The well-trained network is then used to couple with a complex optimization method to search the optimal BGA design with lower thermal resistance. The study will provide electronic package industry a reliable and rapid method of the heat dissipation design of BGA package.

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Dissertations / Theses on the topic 'Ball grid array technology'

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