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1
Lall, Pradeep, Nokibul Islam, John Evans, and Jeff Suhling. "Reliability of BGA and CSP on Metal-Backed Printed Circuit Boards in Harsh Environments." Journal of Electronic Packaging 129, no. 4 (2007): 382–90. http://dx.doi.org/10.1115/1.2804086.
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Increased use of sensors and controls in automotive applications has resulted in significant emphasis on the deployment of electronics directly mounted on the engine and transmission. Increased shock, vibration, and higher temperatures necessitate the fundamental understanding of damage mechanisms, which will be active in these environments. Electronics typical of office benign environments uses FR-4 printed circuit boards (PCBs). Automotive applications typically use high glass-transition temperature laminates such as FR4-06 glass∕epoxy laminate material (Tg=164.9°C). In application environments, metal backing of printed circuit boards is being targeted for thermal dissipation, mechanical stability, and interconnections reliability. In this study, the effect of metal-backed boards on the interconnect reliability has been evaluated. Previous studies on electronic reliability for automotive environments have addressed the damage mechanics of solder joints in plastic ball-grid arrays on non-metal-backed substrates (Lall et al., 2003, “Model for BGA and CSP in Automotive Underhood Environments,” Electronic Components and Technology Conference, New Orleans, LA, May 27–30, pp. 189–196;Syed, A. R., 1996, “Thermal Fatigue Reliability Enhancement of Plastic Ball Grid Array (PBGA) Packages,” Proceedings of the 1996 Electronic Components and Technology Conference, Orlando, FL, May 28–31, pp. 1211–1216;Evans et al., 1997, “PBGA Reliability for Under-the-Hood Automotive Applications,” Proceedings of InterPACK ’97, Kohala, HI, Jun. 15–19, pp. 215–219;Mawer et al., 1999, “Board-Level Characterization of 1.0 and 1.27mm Pitch PBGA for Automotive Under-Hood Applications,” Proceedings of the 1999 Electronic Components and Technology Conference, San Diego, CA, Jun. 1–4, pp. 118–124) and ceramic ball-grid arrays (BGAs) on non-metal-backed substrates (Darveaux, R., and Banerji, K., 1992, “Constitutive Relations for Tin-Based Solder Joints,” IEEE Trans-CPMT-A, Vol. 15, No. 6, pp. 1013–1024;Darveaux et al., 1995, “Reliability of Plastic Ball Grid Array Assembly,” Ball Grid Array Technology, Lau, J., ed., McGraw-Hill, New York, pp. 379–442;Darveaux, R., 2000, “Effect of Simulation Methodology on Solder Joint Crack Growth Correlation,” Proceedings of 50th ECTC, May, pp. 1048–1058). Delamination of PCBs from metal backing has also been investigated. The test vehicle is a metal-backed FR4-06 laminate. The printed circuit board has an aluminum metal backing, attached with pressure sensitive adhesive (PSA). Component architectures tested include plastic ball-grid array devices, C2BGA devices, QFN, and discrete resistors. Reliability of the component architectures has been evaluated for HASL. Crack propagation and intermetallic thickness data have been acquired as a function of cycle count. Reliability data have been acquired on all these architectures. Material constitutive behavior of PSA has been measured using uniaxial test samples. The measured constitutive behavior has been incorporated into nonlinear finite element simulations. Predictive models have been developed for the dominant failure mechanisms for all the component architectures tested.
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Dudek, Rainer, Ralf Do¨ring, and Bernd Michel. "Reliability Prediction of Area Array Solder Joints." Journal of Electronic Packaging 125, no. 4 (2003): 562–68. http://dx.doi.org/10.1115/1.1604802.
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Packages for high pin counts using the ball grid array technology or its miniaturized version, the chip scale package, inherently require reliability concepts as an integral part of their development. This is especially true for the latter packages, if they are combined with the flip chip technology. Accordingly, thermal fatigue of the solder balls is frequently investigated by means of the finite element method. Various modeling assumptions and simplifications are common to restrict the calculation effort. Some of them, like geometric modeling assumptions, assumptions concerning the homogeneity of the cyclic temperature fields, simplified creep characterization of solder, and the related application of Manson-Coffin failure criteria, are discussed in the paper. The packages chosen for detailed analyses are a PBGA 272 and a FC-CSP 230.
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Chen, Shih Feng. "An Optical System for the Ball Grid Array Inspection and Measurement Using the Back-Propagation Neural Network Technology." Key Engineering Materials 364-366 (December 2007): 92–97. http://dx.doi.org/10.4028/www.scientific.net/kem.364-366.92.
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In this study, the back-propagation neural network technology (BPN) is utilized to identify the shape of the defective solder ball of ball grid array (BGA) so as to promote the accuracy of the optical inspection and measurement. The two dimensional BGA optical inspecting system is implemented by Visual Basic as the developing tool incorporated with the Halcon’s function which is the database of the image processing on Windows operation system. For the development of the processing procedure of the automatic optical inspecting system, the precise geometrical information of the solder ball is evaluated by the sub-pixel method to identify the shape of solder ball and its location which are acquired to classify the defects of solder ball including the ball offset, the ball over scale, the ball absence, and the ball shape under the BGA board is offset and rotated at any angle. From the experimental results, the back-propagation neural network technology is proved to properly identify and classify the shape defects, especially for the ball deformation and the ball bridging of the solder ball which can achieve and contribute the requirements for the automatic inspection and the high identification efficiency.
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Tian, Yan Hong, and Chun Qing Wang. "Shape Prediction and Reliability Design of Ball Grid Array Solder Joints." Key Engineering Materials 353-358 (September 2007): 2944–47. http://dx.doi.org/10.4028/www.scientific.net/kem.353-358.2944.
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Reliability optimization design of Ball Grid Array (BGA) solder joints is a major concern in area array electronics packaging technology. In this paper, shapes of the solder joints and their reliability were predicted and analyzed. Through the variations of lower pads’ diameters, the shapes of full array BGA solder joints with different solder volumes were predicted by using surface evolver software. Based on the results of shape prediction, 3-D finite element models were established with MSC.MARC and the distribution of the stress and strain in the BGA solder joints under thermal cyclic loading were simulated. Finally, fatigue lives of the BGA solder joints with different solder volumes were calculated, and the diameter ratios of lower pad to upper pad for these two kinds of BGA assemblies with the best reliability were optimized.
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Yoon, Seung Wook. "Advanced 3D eWLB-SiP (embedded Wafer Level Ball Grid Array – System in Package) Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (2017): 1–20. http://dx.doi.org/10.4071/2017dpc-tp2_presentation5.
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FO-WLP (Fan-Out Wafer Level Packaging) has been established as one of the most versatile packaging technologies in the recent past and is already accounting for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduce the total form factor as well as cost-effectiveness. The emerging of advanced of silicon node technology down to 10 nanometer (nm) in support of higher performance, bandwidth and better power efficiency in mobile products pushes the boundaries of emerging packaging technologies to smaller form-factor packaging designs with finer line/spacing as well as improved thermal electrical/performance and integration of SiP or 3D capabilities. Advanced eWLB FO-WLP technology provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. This paper reports developments that extend multi-die and 3D SiP applications with eWLB technology, including ultra thin devices or/and with an interposer substrate attachment. Test vehicles have been designed and fabricated to demonstrate and characterize integrated packaging solutions for network, mobile products including IoT and wearable electronics. The test vehicles have ranged from ~30mm2 to large sizes up to ~230mm2 and 0.4mm ball pitch. Assembly process details including 3D vertical interconnect, laser ablation, RDL processes and mechanical reliability characterizations are to be discussed with component and board level reliability results. In addition, warpage behavior and the PoP stacking process will also be presented. Innovative structure optimization that provides dual advantages of both height reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, packages with multiple redistribution layers (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability and electrical characterization results on multi-die and 3D eWLB-SiP configurations are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.
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Babaeihaselghobi, Akbar, and Habib Badri Ghavifekr. "Development of a planar helix slow-wave structure based on ball-grid array technology." Journal of Electromagnetic Waves and Applications 34, no. 13 (2020): 1771–81. http://dx.doi.org/10.1080/09205071.2020.1787235.
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Chiang, Kuo-Ning, and Chang-Ming Liu. "A Comparison of Thermal Stress/Strain Behavior of Elliptical/Round Solder Pads." Journal of Electronic Packaging 123, no. 2 (1999): 127–31. http://dx.doi.org/10.1115/1.1339196.
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As electronic packaging technology moving to the CSP, wafer level packaging, fine pitch BGA (ball grid array) and high density interconnections, the wireability of the PCB/substrate and soldering technology are as important as reliability issues. In this work, a comparison of elliptical/round pads of area array type packages has been studied for soldering, reliability, and wireability requirements. The objective of this research is to develop numerical models for predicting reflow shapes of solder joint under elliptical/round pad boundary conditions and to study the reliability issue of the solder joint. In addition, a three-dimensional solder liquid formation model is developed for predicting the geometry, the restoring force, the wireability, and the reliability of solder joints in an area array type interconnections (e.g., ball grid array, flip chip) under elliptical and round pad configurations. In general, the reliability of the solder joints is highly dependent on the thermal-mechanical behaviors of the solder and the geometry configuration of the solder ball. These reliability factors include standoff height/contact angle of the solder joint, and the geometry layout/material properties of the package. An optimized solder pad design cannot only lead to a good reliability life of the solder joint but also can achieve a better wireability of the substrate. Furthermore, the solder reflow simulation used in this study is based on an energy minimization engine called Surface Evolver and the finite element software ABAQUS is used for thermal stress/strain nonlinear analysis.
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Gao, Huijun, Wanxin Jin, Xianqiang Yang, and Okyay Kaynak. "A Line-Based-Clustering Approach for Ball Grid Array Component Inspection in Surface-Mount Technology." IEEE Transactions on Industrial Electronics 64, no. 4 (2017): 3030–38. http://dx.doi.org/10.1109/tie.2016.2643600.
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Bachman, Mark A., Jerry Liao, John Osenbach, Zafer Kutlu, Jaeyun Gim, and Danny Brady. "Large Die Size Lead Free Flip Chip Ball Grid Array Packaging Considerations for 40nm Fab Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 000570–85. http://dx.doi.org/10.4071/2012dpc-ta23.
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To reduce the RC latency, leading edge silicon nodes employ porous SiO2 dielectrics in the interconnect stack. Introduction of porosity lowers the dielectric constant, k, but also significantly decreases both the elastic modulus and fracture toughness of the dielectric. As such, devices manufactured in silicon processes that use low K (90nm, 65nm, and 55nm) and even more so extremely low K ( 45nm, 40nm, and 28nm) interlayer dielectrics are substantially more prone to fracture as a result of package induced stresses than non porous higher K dielectrics. Since the package stresses scale with die size and package body size and inversely with bump pitch, manufacture of large die and package size flip chip devices made with extremely low K dielectrics has proven to be challenging. The stress challenge is further exacerbated by the RoHS requirements for lead free packaging which requires higher process temperatures and somewhat higher yield point solders. The combination of increased stress and reduced mechanical robustness of porous dielectrics has lead to significant reliability and assembly yield issues that have in some cases slowed the introduction of 45nm and 40nm large die lead free flip chip into the market. The work summarized in this paper shows that devices designed to withstand stresses in combination with appropriate assembly processes and bill of materials, yield highly reliable, lead free flip chip packaged devices, with die sizes greater than 400mm2 and package sizes greater than 42.5mm on a side in commercial assembly production lines.
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Rooks, S. M., B. Benhabib, and K. C. Smith. "Development of an inspection process for ball-grid-array technology using scanned-beam X-ray laminography." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A 18, no. 4 (1995): 851–61. http://dx.doi.org/10.1109/95.477473.
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Basaran, Cemal, and Yujun Wen. "Coarsening in BGA Solder Balls: Modeling and Experimental Evaluation." Journal of Electronic Packaging 125, no. 3 (2003): 426–30. http://dx.doi.org/10.1115/1.1602707.
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The reliability of solder joints in electronic packaging is becoming more important as the ball grid array (BGA) develops rapidly into the most popular packaging technology. Thermal fatigue of solder joints has been a reliability concern in the electronic packaging industry since the introduction of surface mount technology (SMT). Microstructural coarsening (phase growth) is considered to be closely related to thermomechanical fatigue failure. Many researchers proposed coarsening models for bulk scale metals. But these models have never been verified for micron-scale actual BGA solder balls. In the present study, three different phase growth models are investigated experimentally on BGA solder balls in a real-life electronic package. Model simulations obtained from three models were compared against test data. The best performing model was chosen for finite element fatigue reliability studies based on continuum damage mechanics.
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Jung, W., J. H. Lau, and Y. H. Pao. "Nonlinear Analysis of Full-Matrix and Perimeter Plastic Ball Grid Array Solder Joints." Journal of Electronic Packaging 119, no. 3 (1997): 163–70. http://dx.doi.org/10.1115/1.2792229.
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The application of Ball Grid Array (BGA) technology in electronic packaging on high I/O plastic and ceramic packages has grown significantly during the past few years. Although PBGA (plastic BGA) has several advantages over fine-pitch Quad Flat Pack (QFP) in terms of smaller package area, higher I/Os, lower switching noise, large pitch, higher assembly yield, and improved robustness in manufacturing process, potential package reliability problems can still occur, e.g., excessive solder joint deformation induced by substrate warpage, moisture ingression (popcorn effect), large variation in solder ball size, voiding as a result of flux entrapment and improper pad/solder mask design (Marrs and Olachea, 1994; Solberg, 1994; Freyman and Petrucci, 1995; Lau, 1995; Donlin, 1996; Lasky et al., 1996; Munroe et al., 1996). Regardless of its improved thermal fatigue performance over the past few years through an extensive amount of research, the BGA solder joint may still pose a reliability issue under harsh environment, e.g., automotive underhood, larger package size, or higher temperature and temperature gradient due to increase in power dissipation of the package. Numerous studies in BGA solder joint deformation and reliability under thermal and mechanical loadings can be found in the literature, e.g., Borgesen et al. (1993), Choi et al. (1993), Guo et al. (1993), Ju et al. (1994), Lau et al. (1994) Lau (1995), and Heinrich et al. (1995). Also, reliability prediction models have been developed by, e.g., Darveaux et al. (1995) and Darveaux (1996). The present study focuses on the application of a detailed nonlinear finite element analysis (FEA) to studying the thermal cyclic response of solder joints in two particular BGA packages, full-matrix and perimeter. Both time-independent plasticity and time-dependent effect, i.e., creep and relaxation, are considered in the constitutive equations of solder joint to evaluate the discrepancy in the results of life prediction. The critical solder joint is identified, and the locations that are most susceptible to fatigue failure in the critical joint are discussed. Some limitations in computation and reliability prediction are also discussed.
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Chen, Ming-Kun, Cheng-Chi Tai, and Yu-Jung Huang. "Electrical approach to Nondestructive Analysis on WB-PBGA with TDR Technology." Journal of Microelectronics and Electronic Packaging 2, no. 4 (2005): 240–52. http://dx.doi.org/10.4071/1551-4897-2.4.240.
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Time Domain Reflectometry (TDR) is a powerful measurement technique that uses the reflection of a pulse sent down a transmission line to characterize the impedance of that line. The voltage of a reflection will vary depending on the distance to the fault and on the amount of energy reflected. In this paper we develop a simple and effective electrical nondestructive analysis (NA) system for the evaluation of the interconnection of wire-bonded plastic ball grid array (WB-PBGA) package. An open-end fixture (OEF) was employed to connect fast rising edge signals to the package which was monitored for its time delay and reflection voltage parameters. This technology represents a valuable new method for the NA of WB-PBGA packages, and it has enabled the rapid and efficient detection and location of faults. Comparative TDR measurements accurately predicted the location of opens and short circuits in the copper traces of the substrate, bond wire, and solders balls. The TDR analysis was verified by using X-ray analysis. The paper establishes the use of a TDR system incorporating an open-end fixture for locating opens and shorts in WB-PBGA packages.
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Frank, Martin, Torsten Reissland, Fabian Lurz, et al. "Antenna and Package Design for 61- and 122-GHz Radar Sensors in Embedded Wafer-Level Ball Grid Array Technology." IEEE Transactions on Microwave Theory and Techniques 66, no. 12 (2018): 5156–68. http://dx.doi.org/10.1109/tmtt.2018.2873368.
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Babaeihaselghobi, Akbar, Muhammad Nadeem Akram, Habib Badri Ghavifekr, Laxma Reddy Billa, Eivind Bardalen, and Per Alfred Ohlckers. "Design and implementation of a planar helix for traveling wave tubes based on package compatible ball grid array technology." Microsystem Technologies 26, no. 5 (2019): 1681–87. http://dx.doi.org/10.1007/s00542-019-04713-8.
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Rahman, Akhlaq, and Jim Norman. "Influence of Different Packaging and Footprint Technique for Microwave Absorptive Bessel Filter's Performance." International Symposium on Microelectronics 2012, no. 1 (2012): 001073–77. http://dx.doi.org/10.4071/isom-2012-thp23.
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In present day's ultra high speed data transmission environment, passive filters play a very important and critical function to achieve high-end system performance, especially in Microwave frequency ranges of 10 GHz or higher. Excellent electrical specification such as accurate −3dB cutoff frequency bandwidth, stable group delay, along with VSWR characteristics are very important parameters for system performance. Filters mechanical specification is similarly important, if not more. Products need not only be in certain size to fit in the board but also needs to be complement with other components. As available space in PCB become miniature for each component, filters footprint as well as via position need to be in certain ways to optimize board space and performance. Packaging material and packaging techniques play significant role to be ease of mass production as well. While some manufacturers like “Wirebonding” packaging, some like “Through Via”, and “Ball Grid Array” is the packaging choice of some manufacturers. Component vendors need to have capability to change component design space, as the system designers' demand for their choice of footprint and packaging environment. Moreover, these stringent mechanical specifications cannot compromise the electrical specification. To realize the effect of different packaging technique, we extensively studied several packaging techniques for Bessel filters with −3dB cutoff frequencies of 7 GHz to 10 GHz. We explored “stud bump ball grid array”, “wirebonding”, and “land grid array” footprint packaging. We modeled different packaging technique and incorporated that into simulation to design the filter. We successfully manufacture surface mount filters with three different footprint packaging. We explored the influence of each packaging technique for electrical performance. We studied the hidden parasitic introduction from each packaging style and the detrimental effect of these to electrical performance, especially for frequency of 7 GHz to 10 GHz. We showed the advantages and disadvantages of all three kind of packaging technology in respect of electrical as well as mechanical specification.
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Chaparala, S., J. M. Pitarresi, S. Parupalli, S. Mandepudi, and M. Meilunas. "Experimental and Numerical Investigation of the Reliability of Double-Sided Area Array Assemblies." Journal of Electronic Packaging 128, no. 4 (2006): 441–48. http://dx.doi.org/10.1115/1.2353280.
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One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.
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Kim, J. Y., and J. S. Yoon. "Image Distortion Compensation by Using a Polynomial Model in an X-Ray Digital Tomosynthesis System." Key Engineering Materials 297-300 (November 2005): 2034–39. http://dx.doi.org/10.4028/www.scientific.net/kem.297-300.2034.
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X-ray technology has been widely used in a number of industrial applications for monitoring and inspecting inner defects which can hardly be found by normal vision systems as a ball grid array (BGA) or a flip chip array (FCA). Digital tomosynthesis (DT) is one of the most useful X-ray cross-sectional imaging methods for PCB inspection, and it usually uses an X-ray image intensifier. However, the image intensifier distorts X-ray images severely both of shape and intensity. This distortion breaks the correspondences between those images and prevents us from acquiring accurate cross-section images. Therefore, image distortion compensation is one of the most important issues in realizing a DT system. In this paper, an image distortion compensation method for an X-ray DT system is presented. It is to use a general distortion polynomial model on two dimensional plane that can cope with arbitrary, complex and various forms of distortion. Experimental results show a great improvement in compensation speed and accuracy.
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Benson, Mollie, Burton Carpenter, and Andrew Mawer. "Solder-Joint Reliability of a Radar Processor for Semi-Autonomous Driving Applications." International Symposium on Microelectronics 2018, no. 1 (2018): 000104–9. http://dx.doi.org/10.4071/2380-4505-2018.1.000104.
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Abstract Radar is currently employed in automotive applications to provide the range, angle, and velocity of objects using RF waves (77GHz). This paper outlines solder joint reliability of a specific micro-processor that processes data received from a SRR (short range radar operating from 0.2 to 30 meters). It is a powerful digital signal processing accelerator, which targets safety applications that require a high Automotive Safety Integrity Level (ASIL-B). The paper explores the package design and construction, SMT (surface mount technology) assembly, and board level reliability testing of various BGA pad surface finish and solder ball alloy materials on a 0.65 mm pitch, 10 × 10 mm body 141 MAPBGA (mold array process-ball grid array) package. The package configurations include two BGA pad surface finishes (Ni/Au and OSP [organic solderability protectant]) and three solder alloys (SnAg, SAC405, and SAC-Bi [a Bi containing SAC derivative]). Solder joint reliability analysis was performed through AATS (air-to-air thermal shock) between 40°C and +125°C and JEDEC Drop Testing at 1500G's. Thermal shock was extended until at least 75% of the populations failed, which was well past the points needed to qualify the packages for the intended end-use applications. The evaluations of the micro-processor indicate that the MAPBGA package can meet the ASIL-B specification requirements with optimized combinations of BGA pad surface finish and solder alloy. The focus of this paper was to determine the baseline solder-joint thermal shock and JEDEC drop performance with varied BGA pad surface finish and solder ball alloy materials.
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Kornain. "Comparative Study of Different Underfill Material on Flip Chip Ceramic Ball Grid Array Based on Accelerated Thermal Cycling." American Journal of Engineering and Applied Sciences 3, no. 1 (2010): 83–89. http://dx.doi.org/10.3844/ajeassp.2010.83.89.
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Kwon, Woon-Seong, Suresh Ramalingam, Xin Wu, et al. "New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA." Journal of Microelectronics and Electronic Packaging 12, no. 3 (2015): 111–17. http://dx.doi.org/10.4071/imaps.452.
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This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.
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O'Toole, Eoin, Steffen Kroehnert, José Campos, Virgilio Barbosa, and Leonor Dias. "Package Thickness - Ultrathin WLFO (Wafer-Level Fan-Out)." International Symposium on Microelectronics 2016, no. 1 (2016): 000305–8. http://dx.doi.org/10.4071/isom-2016-wp31.
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Abstract NANIUM's Fan-Out Wafer-Level Packaging technology WLFO (Wafer-Level Fan-Out) is based on embedded Wafer-Level Ball Grid Array technology eWLB of Infineon Technologies [1]. Since it′s invention almost 10 years ago, it became the leading technology for Fan-Out Wafer-Level packages. The WLFO technology is based upon the reconstitution of KGD (known good die) from incoming device wafer, independent of wafer diameter and material, to recon wafer format of active semiconductor dies or other active/passive components separated by mold compound applied through compression molding on a temporary mold carrier. The resulting recon wafer can be processed in standard wafer processing equipment. One of the challenges for the future of semiconductor packaging is reduction of the board level volume real estate occupied by each component. With the drive towards lower profile end user devices incorporating large display area and battery life the three dimensional space available for semiconductor packages is diminishing. It is well known that WLFO single die packaging but even more significant system integration enables the shrinkage of the XY footprint of the package through flexible very dense heterogeneous system-in-package integration [2]. But one of the disruptive advantages of the substrate-less WLFO technology is to also permit significant reduction of the overall package height (Z). A total package height for a BGA package including solder balls <500um and for a LGA package with solder land pads only <300um is achievable today, and further development towards even thinner packages is on the way.
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Doyle, Rory. "SMART group news." Soldering & Surface Mount Technology 6, no. 3 (1994): 54–55. http://dx.doi.org/10.1108/eb037880.
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The SMART Group has been investigating joining methods for ball grid arrays (BGAs). Originally a development of IBM, and expected to be a dominant packaging technology, the BGA is best visualised as a legless PGA. It has the same advantages—high lead count, wide pitch, small area—but does not need holes. The problem of the BGA is that the interconnects are not visible. This places a high demand on process control and material selection — it really is a case of ‘right first time’. The investigation concentrated on this aspect.
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Böck, J., M. Wojnowski, C. Wagner, et al. "Low-cost eWLB packaging for automotive radar MMICs in the 76–81 GHz range." International Journal of Microwave and Wireless Technologies 5, no. 1 (2013): 25–34. http://dx.doi.org/10.1017/s1759078712000621.
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Embedded wafer-level ball grid array (eWLB) is investigated as a low-cost plastic package for automotive radar applications in the 76–81 GHz range. Low transmission losses from chip to package and board are achieved by appropriate circuit and package design. Special measures are taken to effectively remove the heat from the package and to optimize the package process to achieve automotive quality targets. A 77 GHz radar chip set in eWLB package is developed, which can be applied on the system board using standard solder reflow assembly. These radar MMICs provide excellent radio frequency (RF) performance for the next generation automotive radar sensors. The potential for even higher system integration is shown by a radar transceiver with antennas integrated in the eWLB package. These results demonstrate that eWLB technology is an attractive candidate to realize low-cost radar systems and to enable radar safety affordable for everyone in the near future.
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Furqan, Muhammad, Faisal Ahmed, Reinhard Feger, Klaus Aufinger, Walter Hartner, and Andreas Stelzer. "A SiGe-based fully-integrated 122-GHz FMCW radar sensor in an eWLB package." International Journal of Microwave and Wireless Technologies 9, no. 6 (2017): 1219–30. http://dx.doi.org/10.1017/s1759078717000095.
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High-performance SiGe HBTs and advancements in packaging processes have enabled system-in-package (SiP) designs for millimeter-wave applications. This paper presents a 122-GHz bistatic frequency modulated continuous wave (FMCW) radar SiP. The intended applications for the SiP are short-range distance and angular position measurements as well as communication links between cooperative radar stations. The chip is realized in a 130-nm SiGe BiCMOS technology and is based on a fully differential frequency-multiplier chain with in phase quadrature phase receiver and a binary phase shift keying modulator in the transmit chain. On-wafer measurement results show a maximum transmit output power of 2.7 dBm and a receiver gain of 11 dB. The chip consumes a DC power of 570 mW at a supply voltage of 3.3 V. The fabricated chip is integrated in an embedded wafer level ball grid array (eWLB) package. Transmit/receive rhombic antenna arrays with eight elements are designed in two eWLB packages with and without backside metal, with a measured peak gain of 11 dBi. The transceiver chip size is 1.8 mm × 2 mm, while the package size is 12 mm × 6 mm, respectively. FMCW measurements have been conducted with a sweep bandwidth of up to 17 GHz and a measured range resolution of 1.5 cm has been demonstrated. 2D positions of multiple targets have been computed using two coherently linked radar stations.
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Gospodinova, M., G. Nan, J. Thomas, R. Subraya, and J. Held. "Electrical Characterization of High Performance Memory FBGA BOC Package." Journal of Microelectronics and Electronic Packaging 3, no. 1 (2006): 44–51. http://dx.doi.org/10.4071/1551-4897-3.1.44.
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A multilayer Fine-pitch Ball Grid Array (FBGA) Board-on-chip (BOC) memory package used for applications running at more than 1 Gbit/p/s has been characterized using S-(distributed) parameter measurements and three types of test chips made using state of the art technology. The low parasitics FBGA test board itself was characterized for frequencies up to 5 GHz (the frequency range of interest) with the transmission being greater than −0.12 dB below 5 GHz. S-parameter model simulation of the package itself indicated that the transmission was greater than −1.5 dB up to 5 GHz. Correlation between the S-parameter simulation and measurements for the package and fixture combined was acceptable - in the order of tenths of dB in the frequency range DC to 2.5 GHz. Comparison of the S-parameter model versus lumped (RLC) model in the frequency range from DC to 5 GHz showed that the lumped model can be used for frequencies up to 2.9 GHz. A high degree of correlation between simulation and measurement has been shown. The lumped model bandwidth has been assessed and its application limits for time domain signal integrity simulations have been evaluated.
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Chen, Chi-Han, Kuan-Chung Lu, Chang-Ying Hung, et al. "GHz High Frequency TSV for 2.5D IC Packaging." International Symposium on Microelectronics 2012, no. 1 (2012): 001215–20. http://dx.doi.org/10.4071/isom-2012-thp62.
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TSV (Through Silicon Via) is the key enabling technology for 2.5D & 3D IC stacking solution in FCBGA (Flip Chip Ball Grid Array). As the 2.5D interposer design pushing toward smaller & shorter via due to high I/O density and high frequency requirement, the electrical performance of thinner interposer is therefore much more challenging in low signal loss performance for high frequency application and process. From the structure point of view, the silicon interposer is an additive layer between top side chip(s) and bottom side substrate, it is therefore an additional electrical interconnection which affects the signal propagation between chip(s) and substrate. Therefore, the performance of the TSV insertion loss in silicon interposer becomes critical, especially for above GHz application. Real measurement is conducted to validate the electrical performance of TSV interconnection up to 67GHz, and the wideband scalable model of TSV is also proposed and compared with the measured data. The measurement of this TSV structure has demonstrated the advantages with low parasitic capacitance and low insertion loss at high frequency. Full validated reliability test is also presented to verify interposer fabrication, assembly process optimization, and interconnection stability of the 2.5D IC package.
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Pressel, Klaus, Gottfried Beer, and Maciej Wojnowski. "Assembly and Packaging Enabling System Integration." International Symposium on Microelectronics 2013, no. 1 (2013): 000171–76. http://dx.doi.org/10.4071/isom-2013-ta61.
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More than Moore is a major trend to tackle the increasing difficulties of traditional Moore's law scaling. System in Package technologies, which allow heterogeneous integration, are appearing in ever more electronic applications. Furthermore we observe merging of silicon wafer technology with assembly and packaging technologies. Today a more coherent development taking into account chip, package, and the board is needed. In this paper we show how assembly and packaging can take up the slack because traditional More Moore downscaling is becoming more difficult. First, we introduce the Thin Small Leadless Package (TSLP) e.g. used in mobile systems. The TSLP is similar to the Quad Flat No-Lead (QFN) package, but thinner and with less parasitics. Second, we introduce wafer level type packages. The limits of standard wafer level packaging in respect to I/O counts pushed the development of the embedded Wafer Level Ball Grid Array (eWLB). We demonstrate the outstanding system integration capabilities of the eWLB including excellent mm-wave performance. For all the above mentioned packages chip and package technologies merge. They are door opener for nanoelectronic devices in respect to energy efficiency, mobility and security.
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Olson, Tim. "Transforming Electronic Interconnect." International Symposium on Microelectronics 2017, S1 (2017): 000080–108. http://dx.doi.org/10.4071/isom-2017-slide-4.
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From nanometers at the transistor level to 100's of microns at the ball grid array (BGA) connections, electronic interconnect of semiconductors spans orders of magnitude as it forms the central nervous system of today's advanced electronic products. Tectonic shifts are currently underway within the industries providing electronic interconnect. Traditional supply chain boundaries produce back end of line (BEOL) structures within wafer foundries ranging from 10's of nanometers to 10's of microns. First-level interconnect, or packaging, the classical purvey of semiconductor assembly and test services (SATS) providers operates in 10's to 100's of microns. Second-level interconnect, or board level assembly, historically rests with electronic manufacturing systems (EMS) providers measuring their work in 100's of microns and above. The transformation underway in electronic interconnect will redefine historical supply chain boundaries as it blurs the lines between foundries, SATS and EMS providers. At the heart of the transformation is ‘fan-out’ technology moving from initial capacities in wafer form to an emerging format of large panels. Breaking through capital cost, reliability and yield concerns with novel solutions will open the door for widespread industry growth of fan-out.
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Siadat, David, and Judy Priest. "Pinout Optimization for 10 Gbps+ Serial Link Routing." International Symposium on Microelectronics 2010, no. 1 (2010): 000588–92. http://dx.doi.org/10.4071/isom-2010-wp2-paper5.
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Definition and optimization a BGA (ball grid array) package pinout is a complicated process. Multiple factors must be considered, such as chip level floorplan, board placement of the component, the board stackup, escape routability, and signal and power integrity constraints. These tradeoffs and decisions impact package body size and board real estate, therefore overall system cost. At high frequencies, such as >10 Gbps, the BGA to board via transitions cause visible impedance and noise mismatches and becomes a critical factor in the end to end channel design. Determining BGA pin assignments and their PCB transitions must meet the package crosstalk constraints within the required commodity PCB technology manufacturing rules. This paper describes a methodology of extracting 4 differential signal pairs in the board file from BGA ball to its PCB via transitions through BGA pin field into 3D field solver. The extracted geometry is simulated to determine near-end and far-end crosstalk noise levels between a single victim pair and its associated aggressors. Different pin assignment designs will have different number of aggressors to consider. Different routing layers will also produce different signal via stub lengths (specific resonant frequency) and signal via coupling contributing to far-end crosstalk noise. This may require back drilling of differential signal via stubs to minimize this noise. The aggregated crosstalk noise level must be equal to or better than what the package can deliver. Once these design rules are determined, they can be leveraged across all channels running at the same frequency.
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Li, Zhiqiang, Houjun Sun, Hongjiang Wu, and Shuai Zhang. "An Ultra-Wideband Compact TR Module Based on 3-D Packaging." Electronics 10, no. 12 (2021): 1435. http://dx.doi.org/10.3390/electronics10121435.
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This study presents a novel four-channel tile-type T/R module which achieves excellent performances in ultra-wideband (2–12 GHz) and integrates all circuits in a super-light (25 g) and compact (27.8 × 27.8 × 12 mm3) mechanical structure in active phased array systems. The key advancement of this T/R module was to choose a Ball Grid Array (BGA) as the vertical interconnection and bracing between High-Temperature Co-fired Ceramic (HTCC) substrates in order to achieve a high-integration 3-D structure. Exploiting the HTCC multilayer layout, this paper presents the design and development of an ultra-wideband, compact and light, high-output power, four-channel, dual-polarization Transmit/Receive (T/R) Module. In this module, microwave circuits and power control circuits are highly integrated into electrically isolated HTCC layers or substrates, resulting in low coupling and crosstalk between signals. Furthermore, multichip assembly technology, multifunctional MMICs, and other high-integration technologies were adopted for this module. Each channel could provide more than 2 W transmit output power, more than 15 dB receive gain, and less than 5 dB receive noise figure. Every module contains four channels. The power supply and phase/amplitude conditioning of each channel can be controlled individually and showed good consistency of the amplitude and phase of all channels. The connectors of manifold port and polarization ports are all SSMP, which can achieve further integration. This module has also an automatic negative power protection function. The module has stabilized performance and mass production prospects.
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Hamidipour, Abouzar, Reinhard Feger, Sebastian Poltschak, and Andreas Stelzer. "A 160-GHz system in package for short-range mm-wave applications." International Journal of Microwave and Wireless Technologies 6, no. 3-4 (2014): 361–69. http://dx.doi.org/10.1017/s1759078714000270.
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This paper proposes a fully integrated 160-GHz transmitter and receiver in package for millimeter-wave applications. The monolithic integrated circuits were designed with a harmonic approach and were fabricated using a SiGe:C HBT production technology with an fTand fmaxof 170 and 250 GHz, respectively. The manufactured 2006 × 1865 µm2bare dies were integrated in 6 × 6 mm2embedded wafer level ball grid array packages, where they were interconnected with highly directional antennas built on the redistribution layer of the packages. With a total frequency multiplication factor of 36 and an active balun at the first stage, the transmitter allows the use of a 4.5-GHz input signal driven from a single-ended signal source [1] and distributed on a standard low-cost printed circuit board. The receiver comprises a Gilbert-cell-based subharmonic mixer with a simulated 1-dB input compression point of −4 dBm, and a minimum double-sideband noise figure of 16.5 dB. The functionality of the proposed system was successfully demonstrated in a quasi-monostatic FMCW radar measurement with a 1-ms up-chirp frequency sweep from 157 to 160 GHz and in a forward-scatter imaging experiment with an 8-GHz frequency ramp from 157 to 165 GHz.
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Akay, Hasan U., Yan Liu, and Mostafa Rassaian. "Simplification of Finite Element Models for Thermal Fatigue Life Prediction of PBGA Packages." Journal of Electronic Packaging 125, no. 3 (2003): 347–53. http://dx.doi.org/10.1115/1.1569956.
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The use of PBGA (plastic ball grid array) electronic packages has been greatly increased in the last decade due to high I/O densities offered. The fatigue life prediction for them is a relatively new task in the electronic field. PBGA packages have more complex geometry than conventional SMT (surface mount technology) packages, such as Leaded and Leadless Chip Carriers (LDCC and LLCC), in which the I/O pins are distributed along the perimeters of chip carriers and their geometries are suitable for two-dimensional (2-D) finite element (FE) simulation. This choice is not so clear in PBGAs. In this study, sectional 2-D, sliced three-dimensional (3-D), and 1/8th 3-D FE models for PBGA assemblies are compared to determine the appropriate FE models that are able to save computational time and memory while maintaining reasonable calculation accuracy. The comparisons and merits of each modeling approach are discussed. An energy-based method is used to predict the fatigue life for solder joints in PBGAs. The fatigue coefficients in the correlation equation, which were obtained previously from the analysis of traditional SMT packages, are updated for more accurate prediction. New fatigue coefficients are obtained for different modeling approaches.
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Dziurdzia, Barbara, Maciej Sobolewski, and Janusz Mikolajek. "Convection vs vapour phase reflow in LED and BGA assembly." Soldering & Surface Mount Technology 30, no. 2 (2018): 87–99. http://dx.doi.org/10.1108/ssmt-10-2017-0031.
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Purpose The aim of this paper is to evaluate using statistical methods how two soldering techniques – the convection reflow and vapour phase reflow with vacuum – influence reduction of voids in lead-free solder joints under Light Emitted Diodes (LEDs) and Ball Grid Arrays (BGAs). Design/methodology/approach Distribution of voids in solder joints under thermal and electrical pads of LEDs and in solder balls of BGAs assembled with convection reflow and vapour phase reflow with vacuum has been investigated in terms of coverage or void contents, void diameters and number of voids. For each soldering technology, 80 LEDs and 32 solder balls in BGAs were examined. Soldering processes were carried out in the industrial or semi-industrial environment. The OM340 solder paste of Innolot type was used for LED soldering. Voidings in solder joints were inspected with a 2D X-ray transmission system. OriginLab was used for statistical analysis. Findings Investigations supported by statistical analysis showed that the vapour phase reflow with vacuum decreases significantly void contents and number and diameters of voids in solder joints under LED and BGA packages when compared to convection reflow. Originality/value Voiding distribution data were collected on the basis of 2D X-ray images for test samples manufactured during the mass production processes. Statistical analysis enabled to appraise soldering technologies used in these processes in respect of void formation.
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Klengel (Bennemann), S., M. Krause, L. Berthold, et al. "High resolution analyzes of resistance behavior in eWLB metal contacts." International Symposium on Microelectronics 2011, no. 1 (2011): 000241–48. http://dx.doi.org/10.4071/isom-2011-tp2-paper3.
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The embedded Wafer Level Ball Grid Array (eWLB) technology is a new packaging solution that allows a minimum package size for any number of interconnects at a given pitch and the possibility of further system integration in x-, y- and z-direction. The eWLB is a fan-out wafer level package solution realized by a thin film redistribution layer above the semiconductor chip and using standard thin-film processes. The eWLB technology is driven by smaller form factor and better electrical performance with respect to high frequency applications. For optimum electrical performance, it is important to measure and control the contact resistance at interfaces caused by intermediate layers of the electrical re-routing. This paper presents a case study for high resolution analyzes at the eWLB metallization system Al/TiW/Cu with different intermetallic resistance behavior. First, we investigate different eWLB metallization systems after different process step variations. We observe chemically high resistance intermediate layers using Time-of-Flight Mass Spectrometry (ToF-SIMS). These results show that the intermediate layer consists of carbon, oxygen, fluorine, chlorine and sulfur. Second, we applied Focused Ion Beam (FIB) preparation and Transmission Electron Microscopy (TEM) as well as High Resolution Transmission Electron Microscopy (HRTEM) experiments to investigate the metallization interface Al/TiW/Cu. We resolve a porous 2–10 nm thin layer. We show that control of different humidity concentration out of the mold compound and different pre-clean etch rates at warped wafer parts are crucial for optimum contact resistance. The results demonstrate that high resolution analyzes and combinations of different analytical methods (e.g. HRTEM and ToF-SIMS) are very important for optimum process developments in modern package technology.
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Yoon, Seung Wook. "Robust Reliability Performance of Large size eWLB (Fan-out WLP)." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (2013): 001438–57. http://dx.doi.org/10.4071/2013dpc-wp21.
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With reducing form-factor and functional integration of mobile devices, Wafer Level Packaging (WLP) is attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP, it is more optimal and promising solution compared to fan-in WLP, because it can offer greater flexibility in design of more IOs, multi-chips, heterogeneous integration and 3D SiP. eWLB (embedded wafer level packaging) is a type of fan-out WLP enabling applications that require smaller form-factor, excellent heat dissipations, thin package profile as it has the potential to evolve in various configurations with proven manufacturing capacity and production yield. This paper discusses the recent advancements of robust reliability performance of large size eWLB. It will also highlight the recent achievement of enhanced component level reliability with advanced dielectric materials. After a parametric study and mechanical simulations, new advanced materials were selected and applied to eWLB. Standard JEDEC tests were carried out to investigate component level reliability of large size (9x9~14x14mm2) test vehicles and both destructive/non-destructive analysis were performed to investigate potential structural defects. Daisychain test vehicles were also tested for drop and TCoB (Temperature Cycle on Board) reliability performance in industry standard test conditions. Besides, this paper will also present a study of package level warpage behaviour with Thermo-Moire measurement.
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Woychik, Charles, Robert Mundella, Keith Kunard, Victor Vilar, Justin Borski, and Robert Nead. "Heterogeneous System-In-Package (HSIP) Technology." International Symposium on Microelectronics 2020, no. 1 (2020): 000034–41. http://dx.doi.org/10.4071/2380-4505-2020.1.000034.
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Abstract A stitched test vehicle has been designed using molded wafer technology to characterize the assembly yield and reliability of a 4-layered topside Buildup (BU) and 4 layered bottom side BU package. In this design, the individual module uses 20 1mm square Si die elements, and one 10mmm square Si die and 8 through substrate vias (TSVs) arrayed on a 14mm square module size to produce a Reliability Test Vehicle (RTV) using Fan-out Wafer-Level (FOWL) technology. 17 individual RTV modules are molded on a 100mm wafer to create a reconstituted wafer. On the 1mm square Si die are two dog bone structures that allows for the design of a stitched net for each build layer with the embedded Si die. Therefore one can generate a stitched net between the first BU layer with the embedded Si die, the second BU layer with the embedded die layer, and so on. The layered stitched design feature, allows one to characterize the integrity of the individual BU layers during the sequential BU processing of the layers on both sides of the molded core. The TSVs allow for signal communication between the top 4 BU layers with the 4 backside BU layers. On top of each 4th layer is a ball grid array (BGA) pad on a 0.8mm pitch that can be used to stack this module using conventional soldering methods. This approach to embed die in a molded wafer and then BU layers on each side is referred to as Heterogeneous System-in-Package (HSIP) technology. Another feature to be included in this work is the use of Current Induced Thermal Cycle (CITC) testing. This is a fast and accurate test method developed by i3 Electronics in Endicott, NY to assess the reliability of vias in a BU package. It is widely used in the industry for circuit boards and build up organic substrates, and is now be applied to the finer via dimension (25um diameter) used for HSIP technology. As was discussed above for the RTV design, the same BU and TSV features will be tested in this CITC module design. The BU layers are exactly the same as that used in the above RTV design. For this wafer build, the die will be molded to create a reconstituted wafer. The first goal is to develop a molding process that has less than 20um die shift and produces a molded substrate with the acceptable amount of bow to accommodate the topside build up layers. For each BU layer, the assembly yield can be characterized by probing the stitched nets for the first, second, and so on BU layers for both sides. This data will provide assembly yield. The individual RTV and CITC modules can then be diced from the wafer, solder balls are attached to the topside BGA pads, and then tested using a conventional clam shell socket test fixture. The first set of reliability tests will be thermal cycling and temperature humidity. In this paper we will discuss the challenges with building HSIP modules, their yield and the first phase of reliability testing.
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Yang, Ping, Xiusheng Tang, Yu Liu, Shuting Wang, and Jianming Yang. "Dynamic reliability approach of chip scale package assembly under vibration environment." Microelectronics International 31, no. 2 (2014): 71–77. http://dx.doi.org/10.1108/mi-11-2013-0061.
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Purpose – The purpose of this paper is to perform experimental tests on fatigue characteristics of chip scale package (CSP) assembly under vibration. Some suggestions for design to prolong fatigue life of CSP assembly are provided. Design/methodology/approach – The CSP assembly which contains different package structure modes and chip positions was manufactured. The fatigue characteristics of CSP assembly under vibration were tested. The fatigue load spectrum of CSP assembly was developed under different excitation. The fatigue life of chips can be estimated by using the high-cycle fatigue life formula based on different stress conditions. The signal–noise curve shows the relationship between fatigue life and key factors. The design strategy for improving the fatigue life of CSP assembly was discussed. Findings – The CSP chip has longer fatigue life than the ball grid array chip under high cyclic strain. The closer to fixed point the CSP chip, the longer fatigue life chips will have. The chip at the edge of the printed circuit board (PCB) has longer fatigue life than the one in the middle of the PCB. The greater the excitation imposed on the assembly, the shorter the fatigue life of chip. Research limitations/implications – It is very difficult to set up a numerical approach to illustrate the validity of the testing approach because of the complex loading modes and the complex structure of CSP assembly. The research on an accurate mathematical model of the CSP assembly prototype is a future work. Practical implications – It builds a basis for high reliability design of high-density CSP assembly for engineering application. In addition, vibration fatigue life prediction method of chip-corner solder balls is deduced based on three-band technology and cumulative damage theory under random vibration so as to verify the accuracy of experimental data. Originality/value – This paper fulfils useful information about the dynamic reliability of CSP assembly with different structural characteristics and material parameters.
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Lim, Jacinta Aman, and Vinayak Pandey. "Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology." International Symposium on Microelectronics 2017, no. 1 (2017): 000263–69. http://dx.doi.org/10.4071/isom-2017-wa42_039.
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Abstract Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effectiveness. The increasing complexities in achieving a higher degree of performance, bandwidth and better power efficiency in various markets are pushing the boundaries of emerging packaging technologies to smaller form factor packaging designs with finer line/width spacing as well as improved thermal/electrical performance and the integration of System-in-Package (SiP) or 3D capabilities. SiP technology has been evolving through utilization of various package technology building blocks to serve the market needs with respect to miniaturization, higher integration, and smaller form factor as cited above, with the added benefits of lower cost and faster time to market as compared to silicon (Si) level integration, which is commonly called system-on-chip or SoC. As such, SiP incorporates flip chip (FC), wire bond (WB), and fan-out wafer-level packaging (FOWLP) as its technology building blocks and serves various end applications ranging from radio frequency (RF), power amplifiers (PA), Micro-Electro-Mechanical-Systems (MEMS) and Sensors, and connectivity, to more advanced application processors (AP), and other logic devices such as graphics processing units (GPUs)/central processing units (CPUs). FOWLP, also referred to as advanced embedded Wafer Level Ball Grid Array (eWLB) technology, provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D SiP configurations. This paper presents developments in SiP applications with eWLB/Fan-out WLP technology, integration of various functional blocks such as wire bonding, Package-on-Package (PoP), 2.5D, 3D, smaller form factor, embedded passives, multiple redistribution layer routing and z-height reduction. Test vehicles have been designed and fabricated to demonstrate and characterize these low profile and integrated packaging solutions for mobile products including Internet of Things (IoT)/wearable electronics (WE), MEMS and sensors. Finer line/width spacing of 2/2mm with multiple redistribution layers (RDL) are fabricated and implemented on the eWLB platform to enable higher interconnect density and signal routing. Assembly process details, component level reliability, board level reliability and characterization results for eWLB SiP will be discussed.
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Rodriguez, G., and D. F. Baldwin. "Analysis of Solder Paste Release in Fine Pitch Stencil Printing Processes." Journal of Electronic Packaging 121, no. 3 (1999): 169–78. http://dx.doi.org/10.1115/1.2792680.
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Advanced electronics packaging technologies such as chip scale packages, fine pitch ball grid arrays, and flip chip are pushing solder paste stencil printing to the limit. In order to achieve solder print deposits of the sizes required for emerging electronic packaging technology, a rigorous understanding of the process is required. This paper seeks to expand our understanding of the physical characteristics of stencil printing specifically focusing on the solder paste release process based on experimental and analytical approaches. First, designed experiments were conducted to identify the main process variables affecting final print quality. An in-situ measurement system using a high speed imaging system monitored the solder paste release process. Based on experimental observations, different modes of solder paste release and their corresponding mechanisms were identified. A model was developed to predict print quality for fine pitch applications. The proposed model was experimentally verified showing good agreement with measured values for fine pitch and very fine pitch printing. It was found that the cohesive and adhesive forces acting on the paste tend to govern the release process rather than the viscous and inertial forces.
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Song, Xiaoyu, Shaodi Gao, and Tejasvi P. Chakravarthy. "An efficient ball grid array router." International Journal of Electronics 89, no. 4 (2002): 317–24. http://dx.doi.org/10.1080/00207210210127005.
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Owens, Norman L. "Near-CSP plastic ball grid array." Microelectronics Reliability 40, no. 7 (2000): 1109–16. http://dx.doi.org/10.1016/s0026-2714(00)00037-8.
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Liu, Jay J., Howard Berg, Yenting Wen, Shailesh Mulgaonker, Reed Bowlby, and Andrew Mawer. "Plastic ball grid array (PBGA) overview." Materials Chemistry and Physics 40, no. 4 (1995): 236–44. http://dx.doi.org/10.1016/0254-0584(95)80004-2.
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Castillou, Paul, Roberto Gaddi, Rob van Kampen, Yaojian Lin, Babak Jamshidi, and Seung Wook Yoon. "Advanced Wafer Level Packaging of RF-MEMS with RDL Inductor." International Symposium on Microelectronics 2016, no. 1 (2016): 000185–89. http://dx.doi.org/10.4071/isom-2016-wa33.
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Abstract The market for portable and mobile data access devices that are wirelessly connected to the cloud anytime and anywhere is exploding. The trend to access any network from anywhere is driving increased functional convergence in the radio, which translates into increased packaging complexity and sophistication. This is creating unprecedented demand for RF components providing more integration- in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as wafer level chip scale packaging (WLCSP) or fan-out wafer level packaging (FO-WLP) solutions such as embedded Wafer Level Ball Grid Array (eWLB) to meet these needs. One of the most promising solutions to enable the required RF performance levels in mobile and wearable devices is the use of RF MEMS Tuners. Mobile original equipment manufacturers (OEMs) are rapidly adopting antenna tuning solutions to be able to provide the required signal strength across the large number of LTE spectrum bands used globally. With RF MEMS technology now maturing, the biggest challenge to address the fast growing opportunity was to find a suitable packaging technology that can deliver RF MEMS tuners in the smallest possible form factor, while maintaining the excellent performance characteristics of the RF MEMS technology. After careful analysis, an eWLB/FO-WLP package was adopted and released to volume production in 2015. The commercial eWLB/FO-WLP RF MEMS tuners outperform traditional RF silicon-on-insulator (SOI) switch-based antenna tuning solutions, resulting in much higher data rates (up to 2×) and improved battery life (up to 40%). Redistribution layers (RDL) in eWLB are utilized for higher electrical performance and complex routing to meet electrical requirements. The ability to utilize embedded passives in a multi-layer eWLB structure provides a number of advantages including cost reduction, footprint reduction and increased reliability. Inductors in eWLB offer significantly better performance compared to inductors in standard on-chip technologies. In this paper, we examine the WLCSP and eWLB packaging assembly flow, solutions to RF design challenges as well as characterization of RF performance. Further improvement of the quality factor of the integrated inductor and capacitors by using low-loss thin-film dielectrics and molding compound in eWLB will be reported as well. Package level reliability test results will also be presented in this paper.
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He, Xiaoyuan. "Coplanarity study on ball grid array packaging." Optical Engineering 40, no. 8 (2001): 1608. http://dx.doi.org/10.1117/1.1386639.
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Sawada, Y., A. Yamaguchi, S. Oka, and H. Fujioka. "Reliability of plastic ball grid array package." IEEE Transactions on Components and Packaging Technologies 25, no. 1 (2002): 73–77. http://dx.doi.org/10.1109/6144.991178.
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Zhong, C. H., S. Yi, and D. C. Whalley. "Solder ball failure mechanisms in plastic ball grid array packages." Soldering & Surface Mount Technology 14, no. 2 (2002): 40–50. http://dx.doi.org/10.1108/09540910210427817.
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Lei Nie, M. Osterman, Fubin Song, J. Lo, S. W. R. Lee, and M. Pecht. "Solder Ball Attachment Assessment of Reballed Plastic Ball Grid Array Packages." IEEE Transactions on Components and Packaging Technologies 32, no. 4 (2009): 901–8. http://dx.doi.org/10.1109/tcapt.2009.2021392.
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Yim, Byung-Seung, Jeong Il Lee, Byung Hun Lee, Young-Eui Shin, and Jong-Min Kim. "Bonding Characteristics of Underfilled Ball Grid Array Packaging." MATERIALS TRANSACTIONS 56, no. 7 (2015): 974–80. http://dx.doi.org/10.2320/matertrans.mi201407.
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Lee, C., R. Gopalakrishnan, K. Nyunt, A. Wong, R. C. E. Tan, and J. W. L. Ong. "Plasma cleaning of plastic ball grid array package." Microelectronics Reliability 39, no. 1 (1999): 97–105. http://dx.doi.org/10.1016/s0026-2714(98)00184-x.
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