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Journal articles on the topic 'Bandgap reference (BGR)'
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1
Zhou, Qian Neng, Yun Song Li, Jin Zhao Lin, Hong Juan Li, Chen Li, Yu Pang, Guo Quan Li, Xue Mei Cai, and Qi Li. "A High-Order CMOS Bandgap Voltage Reference." Advanced Materials Research 989-994 (July 2014): 1165–68. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.1165.
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A high-order bandgap voltage reference (BGR) is designed by adopting a current which is proportional to absolute temperature T1.5. The high-order BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the designed high-order BGR achieves temperature coefficient of 2.54ppm/°C when temperature ranging from-55°C to 125°C. The high-order BGR at 10Hz, 100Hz, 1kHz, 10kHz and 100kHz achieves, respectively, the power supply rejection ratio of-64.01dB, -64.01dB, -64dB, -63.5dB and-53.2dB. When power supply voltage changes from 1.7V to 2.5V, the output voltage deviation of BGR is only 617.6μV.
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Zhou, Qian Neng, Rong Xue, Hong Juan Li, Jin Zhao Lin, Yun Song Li, Yu Pang, Qi Li, Guo Quan Li, and Lu Deng. "A Sub-1V High Precision CMOS Bandgap Reference." Applied Mechanics and Materials 427-429 (September 2013): 1097–100. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.1097.
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In this paper, a low temperature coefficient bandgap voltage (BGR) is designed for A/D converter by adopting piecewise-linear compensation technique. The designed BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the PSRR of the designed BGR achieves-72.51dB, -72.49dB, and-70.58dB at 10Hz, 100Hz and 1kHz respectively. The designed BGR achieve the temperature coefficient of 1.57 ppm/°C when temperature is in the range from-35°C to 125°C. When power supply voltage VDD changes from 1V to 7V, the deviation of the designed BGR output voltage VREF is only 4.465μV.
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Saponara, Sergio. "Integrated Bandgap Voltage Reference for High Voltage Vehicle Applications." Journal of Circuits, Systems and Computers 24, no. 08 (August 12, 2015): 1550125. http://dx.doi.org/10.1142/s021812661550125x.
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This work presents a bandgap voltage reference (BGR) integrated in 0.25-μm bipolar-CMOS-DMOS (BCD) technology. The BGR circuit generates a reference voltage of 1.22 V. It is able to withstand large supply voltage variations of vehicle applications from 4.5 V, e.g., in case of cranking, up to 60-V, maximum value in case of emerging 48-V battery systems for hybrid and electrical vehicles. The circuit has an embedded high-voltage (HV) pseudo-regulator block that provides a more stable internal supply rail for a cascaded low-voltage bandgap core. HV MOS are used only in the pre-regulator block thus allowing the design of a BGR with compact size. The proposed architecture permits to withstand large input voltage variations with a temperature drift of a hundred of ppm/°C, a line regulation (LR) of few mV/V versus the external supply voltage and a power supply rejection ratio (PSRR) higher than 90 dB.
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SAPONARA, SERGIO, LUCA FANUCCI, TOMMASO BALDETTI, and ENRICO PARDI. "BANDGAP VOLTAGE REFERENCE IC FOR HV AUTOMOTIVE APPLICATIONS WITH PSEUDO-REGULATED BIAS AND SERVICE REGULATOR." Journal of Circuits, Systems and Computers 22, no. 01 (January 2013): 1250069. http://dx.doi.org/10.1142/s0218126612500697.
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The paper presents a bandgap voltage reference (BGR) implemented in TSMC 0.25 μm BCD technology for an automotive application. To withstand a car's battery large voltage variations, from 5 V to 40 V, the circuit features an embedded pseudo-regulator providing a stable bias current for the bandgap core. High-voltage (HV) MOS count has been kept low thus allowing the design of a compact BGR with an area of 0.118 mm2. The BGR has been designed to operate in automotive extended temperature range (-40°C to 150°C) and it provides a stable voltage of 1.21 V, which is also used as reference for a cascade 3.7 V linear regulator. Measurements carried on fabricated IC samples prove the effectiveness of the BGR design in terms of supported input voltage variations and operating temperature range, temperature drift, line regulation and PSRR performance.
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Zhou, Ze-kun, Hongming Yu, Yue Shi, Zhuo Wang, and Bo Zhang. "A High-Precision Bandgap Voltage Reference with Automatic Curvature-Compensation Technique." Journal of Circuits, Systems and Computers 28, no. 13 (January 8, 2019): 1950214. http://dx.doi.org/10.1142/s0218126619502141.
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A high-precision bandgap voltage reference (BGR) with a novel curvature-compensation scheme is proposed in this paper. The temperature coefficient (TC) can be automatically optimized with a built-in adaptive curvature-compensation technique, which is realized in a digitization control way. An exponential curvature-compensation method is first adopted to reduce the TC in a certain degree, especially in low temperature range. Then, the temperature drift of BGR in higher temperature range can be further minimized by dynamic zero-temperature-coefficient point tracking (ZTCPT) with temperature changes. With the help of proposed adaptive signal processing, the output voltage of BGR can approximately maintain zero TC in a wider temperature range. Verification results of the BGR proposed in this paper, which is implemented in 0.35-[Formula: see text]m BiCMOS process, illustrate that the TC of 1.4[Formula: see text]ppm/∘C is realized under the power supply voltage of 3[Formula: see text]V and the power supply rejection of the proposed circuit is [Formula: see text][Formula: see text]dB without any filter capacitor.
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Agarwal, Neeru, Neeraj Agarwal, Chih-Wen Lu, and Masahito Oh-e. "A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator." Electronics 10, no. 18 (September 14, 2021): 2257. http://dx.doi.org/10.3390/electronics10182257.
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A chopper-embedded bandgap reference (BGR) scheme is presented using 0.18 μm CMOS technology for low-frequency noise suppression in the clock generator application. As biasing circuitry produces significant flicker noise, along with thermal noise from passive components, the proposed low-noise chopper-stabilized BGR circuit was designed and implemented for wide temperature range from −40 to 125 °C, including a startup and self-biasing circuit to reduce critical low-frequency noise from the bias circuitry and op amp input offset voltage. The BGR circuit generated a reference voltage of 1.25 V for a supply voltage range of 2.5–3.3 V. The gain of the implemented BGR operational transconductance amplifier is 84.1 dB. A non-overlapping clock circuit was implemented to reduce the clock skew effect, which is also one of the noise contributors. The noise analysis of a chopped bandgap voltage reference was evaluated through cadence periodic steady-state (PSS) analysis and periodic noise (PNoise) analysis. The low-frequency flicker noise was reduced from 1.5 to 0.4 μV/sqrt(Hz) at 1 KHz, with the proposed chopping scheme in the bandgap. Comparisons of the noise performance of the chopper-embedded BGR, with and without a low-pass filter, were also performed, and the results show a further reduction in the overall noise. A reduction in the flicker noise, from 181.3 to 10.26 mV/sqrt(Hz) at 100 KHz, was observed with the filter. All circuit blocks of the proposed BGR scheme were designed and simulated using the EDA tool HSPICE, and layout generation was carried out by Laker. The BGR architecture layout dimensions are 285.25 μm × 125.38 μm.
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Xu, Jiangtao, Yawei Wang, Minshun Wu, Ruizhi Zhang, Sufen Wei, Guohe Zhang, and Cheng-Fu Yang. "A High-Accuracy Ultra-Low-Power Offset-Cancelation On-Off Bandgap Reference for Implantable Medical Electronics." Electronics 8, no. 7 (July 21, 2019): 814. http://dx.doi.org/10.3390/electronics8070814.
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An ultra-low-power and high-accuracy on-off bandgap reference (BGR) is demonstrated in this paper for implantable medical electronics. The proposed BGR shows an average current consumption of 78 nA under 2.8 V supply and an output voltage of 1.17 V with an untrimmed accuracy of 0.69%. The on-off bandgap combined with sample-and-hold switched-RC filter is developed to reduce power consumption and noise. The on-off mechanism allows a relatively higher current in the sample phase to alleviate the process variation of bipolar transistors. To compensate the error caused by operational amplifier offset, the correlated double sampling strategy is adopted in the BGR. The proposed BGR is implemented in 0.35 μm standard CMOS process and occupies a total area of 0.063 mm2. Measurement results show that the circuit works properly in the supply voltage range of 1.8–3.2 V and achieves a line regulation of 0.59 mV/V. When the temperature varies from −20 to 80 °C, an average temperature coefficient of 19.6 ppm/°C is achieved.
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Liu, Quanwang, Bo Zhang, Shaowei Zhen, Weidong Xue, and Ming Qiao. "A 2.6 ppm/°C 2.5 V Piece-Wise Compensated Bandgap Reference with Low Beta Bipolar." Electronics 8, no. 5 (May 17, 2019): 555. http://dx.doi.org/10.3390/electronics8050555.
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Traditional bandgap reference (BGR) is sensitive to process variation and is not suitable for mass production. Consequently, a stacked piece-wise compensated bandgap reference (SPWBGR) with low beta bipolar is proposed, designed and fabricated in the 0.18 μm high-voltage (HV) BCD process. Two stacked BGR (SBGR) cores make up the proposed BGR circuit. Through setting the target reference voltage near the output voltage of SBGR cores, the feedback resistor ratio is reduced and the base current side-effect is significantly decreased. Notably, the SBGR core is implemented by the low beta npn bipolar and it relaxes the requirement for the high beta bipolar. The two SBGR cores are almost identical except for the temperature slope and feedback ratio. The two cores have different zero temperature coefficient (TC) points, one is set at −5 °C, and the other is set at 60 °C, named as SBGRA and SBGRB, respectively. The SBGRA and SBGRB output the same voltage at their zero TC point. The higher voltage of SBGRA and SBGRB is the output voltage. Through the process of tracking the maximum value of different SBGR cores, the proposed SPWBGR achieves 2.6 ppm/°C TC from −40 to 100 °C. As a result, the average TC for five random samples is 5.3 ppm/°C. The line regulation is 2 mV/V from 4.5 to 5.5 V power supply. The current consumption is 6.8 µA. The active area of the proposed BGR is 0.075 mm2.
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Zhao, Gongyuan, Mao Ye, Yiqiang Zhao, Kai Hu, and Ruishan Xin. "A High Order Curvature-Compensated Bandgap Voltage Reference with a Novel Error Amplifier." Journal of Circuits, Systems and Computers 26, no. 09 (April 24, 2017): 1750127. http://dx.doi.org/10.1142/s0218126617501274.
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This paper presents a bandgap voltage reference (BGR), utilizing high order curvature-compensated technique with the temperature dependent resistor. Based on an improved error amplifier, [Formula: see text]80[Formula: see text]dB power supply rejection (PSR) @1[Formula: see text]kHz is achieved without additional complicated circuits. The circuit is fabricated in a standard [Formula: see text]m CMOS process, consuming 50[Formula: see text][Formula: see text]A at 25[Formula: see text]C with a supply voltage of 3.3[Formula: see text]V. Simulation results show that the proposed BGR can achieve a temperature coefficient as low as 1.18[Formula: see text]ppm/[Formula: see text]C over the temperature range from [Formula: see text]C to 120[Formula: see text]C. Monte Carlo simulation and Experimental Results validate the design.
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Qiu, Jinpeng, Tong Liu, Xubin Chen, Yongheng Shang, Jiongjiong Mo, Zhiyu Wang, Hua Chen, Jiarui Liu, Jingjing Lv, and Faxin Yu. "A New Digital to Analog Converter Based on Low-Offset Bandgap Reference." Journal of Electrical and Computer Engineering 2017 (2017): 1–10. http://dx.doi.org/10.1155/2017/1658695.
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This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5 μm 5 V 1P4M process. The measured differential nonlinearity (DNL) of the output voltages is less than 0.45 LSB and integral nonlinearity (INL) less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The DNL and INL at −55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.
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Liu, Xiao Wei, Bing Jun Lv, Peng Fei Wang, Liang Yin, and Na Xu. "A Curvature-Compensated, High Power Supply Rejection CMOS Bandgap Reference for MEMS Micro-Accelerometer." Key Engineering Materials 483 (June 2011): 481–86. http://dx.doi.org/10.4028/www.scientific.net/kem.483.481.
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The reference is an important part in the accelerometer system. With the development of science and technology, the request of the performance of accelerometers is increasingly higher and the precision of reference directly affects the performance of accelerometers. Therefore, a reference voltage applicable to accelerometers is presented based on the analysis of basic principles of conventional bandgap reference (BGR) in this paper. A high-order curvature compensation technique, which uses a temperature dependent resistor ratio generated by a high poly resistor and a nwell resistor, effectively serves to reduce temperature coefficient of proposed reference voltage circuit and to a large extent improve its performance. To achieve a high power supply rejection ratio (PSRR) over a broad frequency range, a pre-regulator is introduced to remain the supply voltage of the core circuit of BGR relatively independent of the global supply voltage. The proposed circuitry is designed in standard 2.0μm CMOS process. The simulated result shows that the average temperature coefficient is less than 2ppm/°C in the temperature range from -40 to 120°C. The improvement on temperature coefficient (TC) is about 10 times reduction compared to the conventional approach. And the PSR at DC frequency and 1kHz achieves -107 and -71dB respectively at 9.0V supply voltage.
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Ishida, Yosuke, and Toru Tanzawa. "A Fully Integrated AC-DC Converter in 1 V CMOS for Electrostatic Vibration Energy Transducer with an Open Circuit Voltage of 10 V." Electronics 10, no. 10 (May 15, 2021): 1185. http://dx.doi.org/10.3390/electronics10101185.
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This paper proposes an AC-DC converter for electrostatic vibration energy harvesting. The converter is composed of a CMOS full bridge rectifier and a CMOS shunt regulator. Even with 1 V CMOS, the open circuit voltage of the energy transducer can be as high as 10 V and beyond. Bandgap reference (BGR) inputs a regulated voltage, which is controlled by the output voltage of the BGR. Built-in power-on reset is introduced, which can minimize the silicon area and power to function normally found upon start-up. The AC-DC converter was fabricated with a 65 nm low-Vt 1 V CMOS with 0.081 mm2. 1 V regulation was measured successfully at 20–70 °C with a power conversion efficiency of 43%.
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Nagulapalli, R., K. Hayatleh, S. Barker, A. A. Tammam, P. Georgiou, and F. J. Lidgey. "A 0.55 V Bandgap Reference with a 59 ppm/°C Temperature Coefficient." Journal of Circuits, Systems and Computers 28, no. 07 (June 27, 2019): 1950120. http://dx.doi.org/10.1142/s0218126619501202.
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This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with the existing BJT-based reference circuits by using a MOS transistor operating in sub-threshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65[Formula: see text]nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55[Formula: see text]V, and generates a 286[Formula: see text]mV reference voltage with a temperature coefficient of 59[Formula: see text]ppm/∘C. The circuit takes 413[Formula: see text]nA current from 0.55[Formula: see text]V supply and occupies 0.00986[Formula: see text]mm2 of active area.
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Wu, Hongbing, and Hongxia Liu. "An Improved Bandgap Reference with Curvature-Compensated and High Power Supply Rejection." Journal of Circuits, Systems and Computers 25, no. 11 (August 14, 2016): 1650147. http://dx.doi.org/10.1142/s0218126616501474.
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This paper presents a bandgap reference (BGR) with the characteristics of curvature-compensation and high power supply rejection ratio (PSRR). To achieve a better performance, the base current of BJT is injected to a small segment of resistor string to flatten the temperature variation, and a pre-regulator of the power supply is implemented to improve the PSRR. The circuits, designed in 0.18[Formula: see text][Formula: see text]m BCD technology, exhibit an average voltage of 1.212[Formula: see text]V with temperature coefficient of 2.0[Formula: see text]ppm/[Formula: see text] in the range from [Formula: see text] to 110[Formula: see text] at typical condition, and a power supply rejection ratio of [Formula: see text][Formula: see text]dB at low frequency. After 4-bit trimming, Monte Carlo simulation results show that the proposed design gets an accuracy of 0.29%, with a variation of [Formula: see text][Formula: see text]mV. The active design area is 160[Formula: see text][Formula: see text]m, and the power supply current is about 8.2[Formula: see text][Formula: see text]A.
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Salehi, Mohammad Reza, Rezvan Dastanian, Ebrahim Abiri, and Sajad Nejadhasan. "A 1.58nW power consumption and 34.45ppm/°C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag." Microelectronics Journal 46, no. 5 (May 2015): 383–89. http://dx.doi.org/10.1016/j.mejo.2015.03.002.
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Abarca, Accel, and Albert Theuwissen. "In-Pixel Temperature Sensors with an Accuracy of ±0.25 °C, a 3σ Variation of ±0.7 °C in the Spatial Domain and a 3σ Variation of ±1 °C in the Temporal Domain." Micromachines 11, no. 7 (July 8, 2020): 665. http://dx.doi.org/10.3390/mi11070665.
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This article presents in-pixel (of a CMOS image sensor (CIS)) temperature sensors with improved accuracy in the spatial and the temporal domain. The goal of the temperature sensors is to be used to compensate for dark (current) fixed pattern noise (FPN) during the exposure of the CIS. The temperature sensors are based on substrate parasitic bipolar junction transistor (BJT) and on the nMOS source follower of the pixel. The accuracy of these temperature sensors has been improved in the analog domain by using dynamic element matching (DEM), a temperature independent bias current based on a bandgap reference (BGR) with a temperature independent resistor, correlated double sampling (CDS), and a full BGR bias of the gain amplifier. The accuracy of the bipolar based temperature sensor has been improved to a level of ±0.25 °C, a 3σ variation of ±0.7 °C in the spatial domain, and a 3σ variation of ±1 °C in the temporal domain. In the case of the nMOS based temperature sensor, an accuracy of ±0.45 °C, 3σ variation of ±0.95 °C in the spatial domain, and ±1.4 °C in the temporal domain have been acquired. The temperature range is between −40 °C and 100 °C.
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Sun, Jie, and Jianhui Wu. "A 12-bit 350 MS/s Single-Channel Pipeline ADC with 75 dB SFDR in 0.18 μm BiCMOS." Journal of Circuits, Systems and Computers 28, no. 03 (February 24, 2019): 1950044. http://dx.doi.org/10.1142/s0218126619500440.
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A 12-bit 350[Formula: see text]MS/s ADC with 75[Formula: see text]dB SFDR fabricated in 0.18[Formula: see text][Formula: see text]m SiGe BiCMOS process is presented. To improve the power efficiency, the ADC employs a novel residue amplifier (RA) by exploiting the hetero-junction bipolar transistor (HBT). We also propose a fast comparator to save time for the residue settling of pipeline stages. A fully integrated reference buffer with “negative bootstrap power” (NBP) is proposed to improve both high power supply rejection ratio (PSRR) and ground supply rejection ratio (GSRR). A bandgap reference (BGR) with ultra-low leakage current start-up loop is also presented. The measured results show that with Nyquist input, the SFDR achieves 75[Formula: see text]dB and 63[Formula: see text]dB SNDR up to 350[Formula: see text]MS/s and consumes 180[Formula: see text]mW (only ADC core) with 580[Formula: see text]fj/cov Waldon FOM.
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Wong-Ng, W., G. Y. Liu, D. D. Shi, Y. Q. Yang, R. Derbeshi, D. Windover, and J. A. Kaduk. "Crystal chemistry, X-ray diffraction reference patterns, and bandgap studies for (BaxSr1–x)2CoWO6 (x = 0.1, 0.2, 0.3, 0.5, 0.7, and 0.9)." Powder Diffraction 35, no. 3 (June 23, 2020): 197–205. http://dx.doi.org/10.1017/s0885715620000342.
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X-ray reference powder patterns and structures have been determined for a series of cobalt- and tungsten-containing cubic alkaline-earth perovskites, (BaxSr1–x)2CoWO6 (x = 0.1, 0.2, 0.3, 0.5, 0.7, and 0.9). The structure of the end members of the series, Sr2CoWO6 and Ba2CoWO6, were tetragonal and cubic, respectively, agreeing with the literature data. From Rietveld refinements, it was found that when x = 0.1 and 0.2, the structure was tetragonal I4/m (a = 5.60481(6) and 5.62305(11) Å and c = 7.97989(12) and 7.9847(2) Å, respectively; Z = 2). When x > 0.2, the structure was cubic (Fm$\bar{3}$m, No. 225; Z = 4) (from x = 0.3 to 0.9, a increases from 7.98399(13) to 8.08871(10) Å). This tetragonal series of compounds exhibit the characteristics of a distorted double-perovskite structure. The bond valence sum values for the alkaline-earth (Ba, Sr) sites in all (BaxSr1−x)2CoWO6 members are greater than the ideal value of 2.0, indicating over-bonding situation, whereas for the W sites, as x increases, a change from under-bonding to slightly over-bonding situation was observed. Density functional theory calculations revealed that while Sr2CoWO6 is a semiconductor, Ba2CoWO6 and SrBaCoWO6 are half-metals. Powder X-ray diffraction patterns of this series of compounds (BaxSr1−x)2CoWO6, with x = 0.1, 0.2, 0.3, 0.5, 0.7, and 0.9, have been submitted to be included in the Powder Diffraction File.
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Kaushik, Roohie, Jasdeep Kaur, and Anushree Anushree. "Design of folded cascode op amp and its application – bandgap reference circuit." Circuit World ahead-of-print, ahead-of-print (March 29, 2021). http://dx.doi.org/10.1108/cw-10-2019-0137.
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Purpose Reference voltage or current generators are an important requirement for an analog or digital circuit design. Bandgap reference circuits (BGR) are most common way of generating the reference voltage. This paper aims to provide a detailed insight of design of a folded cascode operational amplifier (FC op amp) and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm semiconductor laboratory (SCL) process leading to bonding diagram for possible tape-out is discussed. This study work has been supported by MeitY, Govt. of India, through Special Manpower Development Project Chip to System Design. Design/methodology/approach This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the two circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. Section 2 shows the design of FC op amp, beta-multiplier circuit and their simulation results. Section 3 describes the comparison of design of conventional BGR and the proposed BGR with other state-of-art BGR circuits. Section 4 gives the comparison of their performance. The conclusion is given in Section 5. Findings The post-layout simulation of FC op amp show an open-loop gain of 64.5 dB, 3-dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5µW. Among the two BGR designs, the conventional BGR generated 693 mV of reference voltage with a temperature coefficient of 16 ppm/°C the other BGR, with curvature correction generated 1.3 V of reference voltage with a temperate coefficient of 6.3 ppm/°C , both results in temperature ranging from −40°C to 125°C. The chip layout of the circuits designed on 180 nm SCL process ensures design rule check (DRC), Antenna and layout versus schematic (LVS) clean with metal fill. Research limitations/implications Slew rate, stability analysis, power are important parameters which should be taken care while designing an op amp for a BGR. Direct current gain should be kept higher to reduce offset errors. Input common mode range is decided by the operating temperature range. A higher power supply rejection ratio will reduce BGR sensitivity to supply voltage variations. Input offset should be kept low to reduce BGR error in reference voltage. However, this paper emphasis on the flow from schematic to layout using simulation tools. As part of the study, the bonding diagram for tape-out of BGR and FC design in the given SCL frame size with seal ring is also explored, for possible tape-out. Practical implications Reference voltage or current generators are an important requirement for an analog or digital circuit design. BGR are most common way of generating the reference voltage. This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. The chip layout of the circuits was designed on 180 nm SCL process ensuring DRC, antenna and LVS clean with metal fill using Cadence virtuoso and Mentor Graphics Calibre simulation tools. Social implications BGR are most common way of generating the reference voltage. This paper gives a detailed insight of a BGR design using a folded-cascode operational amplifier. The FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror circuit. The paper discuss FC circuit design flow from schematic to layout. Originality/value FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror. The paper discusses FC design flow from schematic to layout. The circuits were designed on 180 nm SCL technology with 1.8 V of power supply. The post-layout simulation show an open-loop gain of 64.5 dB, 3 dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5 µW. BGR were designed using FC op amp. The proposed BGR generated 1.3 V of reference voltage with a temperature coefficient of 6.3 ppm/°C in the range from −40°C to 125°C in schematic simulation.
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Ebrahimi, Emad, and Maliheh Arabnasery. "A New Sub-1 Volt 17ppm/°C Offset-Insensitive Resistorless Switched-Capacitor Bandgap Voltage Reference." Journal of Circuits, Systems and Computers, July 27, 2020, 2150029. http://dx.doi.org/10.1142/s0218126621500298.
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A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.
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"Energy Efficient Bandgap Reference Generator for RFID Transponder EEPROM in 130 nm CMOS Process." International Journal of Recent Technology and Engineering 8, no. 4 (November 30, 2019): 6422–26. http://dx.doi.org/10.35940/ijrte.d5151.118419.
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Reducing power dissipation of any circuit can make that circuit more energy-efficient and at the same time promise stability. Recent researchers mainly focus on controlling and monitoring low power designs for different low power applications, wireless systems such as radio frequency identification (RFID) transponder. Therefore, generating an internal reference voltage (VR) for the power management unit is the key challenges for researchers to design such applications. Bandgap reference (BGR) is an essential module that assures temperature and independent VR supply in analog circuits. In this research, an improved BGR is designed with the self-startup circuit, bandgap core and an operational amplifier (OP-AMP) to generate a stable VR. A low-power BGR is simulated using Silterra 130 nm CMOS technology. The designed BGR generates a VR of 1.1 V and consumes only 1.4 µA power form 1.2 V power supply voltage. Moreover, it has a temperature coefficient of 41.6 ppm/℃.