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1
Yang, Shijun. "Smart receiver using baseband digital signal processing." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0017/MQ48478.pdf.
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Yang, Shijun Carleton University Dissertation Engineering Electronics. "Smart receiver using baseband digital signal processing." Ottawa, 1999.
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Li, Yushan. "Receiver algorithms that enable multi-mode baseband terminals." Thesis, University of Edinburgh, 2005. http://hdl.handle.net/1842/11051.
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Wireless communications is rapidly moving towards so called 4G wireless systems. This has led to an increasing demand to develop integrated mobile terminals which have multi-mode capabilities, i.e. multiple communication systems can coexist. The central goal of this thesis is to determine appropriate structures and algorithms for multi-mode receivers that maximize flexibility without excessive compromise in performance. The work develops multi-mode terminals from the algorithm viewpoint, reducing receiver complexity by taking advantage of the commonalities among different specifications and receiver requirements. For example, the commonalities among DAB, DVB-T and HIPERLAN-2 physical layers are investigated and a common system clock is adopted for these communication systems. In addition, a receiver architecture combining sampling rate conversion and OFDM symbol synchronisation is also presented. The coexistence of WCDMA and OFDM systems from the perspective of using the same equalisation structure is elaborated; chip-level frequency domain equalisation for WCDMA forms a major part of this thesis. Simulation results verify the effectiveness of the proposed equalisation algorithms. Moreover, SC-FDE with more flexible structures, i.e. with a varying length feedback filter or without cyclic prefix, is examined. Then the importance of an accurate channel estimation for practical spread spectrum systems is emphasized. A code-multiplexed pilot sequence is used for the purpose of channel estimation in both WCDMA and CP-CDMA systems and to maintain bandwidth efficiency. System performance is improved significantly by a proposed joint iterative channel estimation and parallel interference cancellation algorithm. Finally conclusions are drawn and suggestions for further work presented.
4
Sahin, Mustafa. "Baseband receiver algorithms for 4G co-channel femtocells." [Tampa, Fla] : University of South Florida, 2009. http://purl.fcla.edu/usf/dc/et/SFE0003283.
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Axell, Christian, and Mikael Brogsten. "Efficient WiMAX Receiver Implementation on a Programmable Baseband Processor." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7684.
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WiMAX provides broadband wireless access and uses OFDM as the underlying modulation technique. In an OFDM based wireless communication system, the channel will distort the transmitted signal and the performance is seriously degraded by synchronization mismatches between the transmitter and receiver. Therefore such systems require extensive digital signal processing of the received signal for retrieval of the transmitted information.
In this master thesis, parts of an IEEE 802.16d (WiMAX) receiver have been implemented on a programmable baseband processor. The implemented parts constitute baseband algorithms which compensates for the effects from the channel and synchronization errors. The processor has a new innovative architecture with an instruction set optimized for baseband applications.
This report includes theory behind the baseband algorithms as well as a presentation of how they are implemented on the processor. An impartial evaluation of the processor performance with respect to the algorithms used in the reference model is also presented in the report.
6
Jeon, Okjune. "Analog baseband processor for CMOS 5-GHz WLAN receiver." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0013035.
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Bahmani, Faramarz. "High performance RF and baseband building blocks for wireless receivers." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5818.
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Because of the unique architecture of wireless receivers, a designer must
understand both the high frequency aspects as well as the low-frequency analog
considerations for different building blocks of the receiver. The primary goal of this
research work is to explore techniques for implementing high performance RF and
baseband building blocks for wireless applications. Several novel techniques to improve
the performance of analog building blocks are presented. An enhanced technique to
couple two LC resonators is presented which does not degrade the loaded quality factor
of the resonators which results in an increased dynamic range.
A novel technique to automatically tune the quality factor of LC resonators is
presented. The proposed scheme is stable and fast and allows programming both the
quality factor and amplitude response of the LC filter.
To keep the oscillation amplitude of LC VCOs constant and thus achieving a
minimum phase noise and a reliable startup, a stable amplitude control loop is presented.
The proposed scheme has been also used in a master-slave quality factor tuning of LC
filters.
An efficient and low-cost architecture for a 3.1GHz-10.6GHz ultra-wide band
frequency synthesizer is presented. The proposed scheme is capable of generating 14A novel pseudo-differential transconductance amplifier is presented. The
proposed scheme takes advantage of the second-order harmonic available at the output
current of pseudo-differential structure to cancel the third-order harmonic distortion.
A novel nonlinear function is proposed which inherently removes the third and
the fifth order harmonics at its output signal. The proposed nonlinear block is used in a
bandpass-based oscillator to generate a highly linear sinusoidal output.
Finally, a linearized BiCMOS transconductance amplifier is presented. This
transconductance is used to build a third-order linear phase low pass filter with a cut-off
frequency of 264MHz for an ultra-wide band receiver.
carrier frequencies.
8
Svensson, Gustaf. "Analog Baseband Implementation of a Wideband Observation Receiver for RF Applications." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-131081.
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During the thesis, a two-staged analog baseband circuit incorporating a passive analog filter and a wideband voltage amplifier were successfully designed, implemented in an IC mask layout in a 65nm CMOS technology, and joined with a previously designed analog front-end design to form a wideband observation receiver. The baseband circuit is capable of receiving an IF bandwidth up to 990MHz produced by the analog front-end using low-side injection. The final circuit shows high IMD3 of at least 90 dBc. The voltage amplifier delivers a voltage amplification of 15 dB with around 0.08 dB amplitude precision over the bandwidth, while the passive filter is capable of a passband amplitude precision of 0.67 dB over the bandwidth, while effectively suppress signal images created by the mixer with at least 60 dBc. Both stages were realized in an IC mask layout, in addition, the filter layout were simulated using an EM simulator.
9
Chen, Minghui. "Multiple Gb/s DQPSK direct-conversion baseband receiver for 60-GHz communications." Diss., Restricted to subscribing institutions, 2007. http://proquest.umi.com/pqdweb?did=1375535621&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Park, Seok-Bae. "Compact high performance analog CMOS baseband design solutions for multistandard wireless transceivers." Columbus, Ohio : Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1149024229.
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Chen, Xin-Hong, and 陳信宏. "Baseband Receiver Design for GSM." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/24396070344233533939.
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碩士國立交通大學
電子工程系
87
GSM is a digital and based on narrowband TDMA communication system, and data rate is 270.83 kb/s on the baseband receiver, to be time-divided between eight users, each has 33.85 kb/s In this thesis, a baseband GSM receiver was proposed. It consists of a correlator, equalizer, deinterleaving and a decoder. Comprehensive channel model and GSM frame structure are provided for performance evaluation. The equalizer features soft output calculated by Euclidean distance, and traceback theorem would be used for survivor memory management which would also be need for the decoder. The thorough data flow had been simulated for the bit error rate requirements and architecture design for the modules had been down. Gate count for the equalizer without optimization is approximated to be 13000. Throughput represents to be 1.5 MHz under 50 MHz clock.
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Shiau, Jung-chin, and 蕭仲欽. "Design of Baseband Circuit for Wireless Receiver." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/79529567962092247621.
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碩士國立臺灣科技大學
電機工程系
100
With the advancement of biomedical technology, implantable chip systems have become a new research topic. This thesis presents two designs of baseband circuits for wireless biomedical receiver applications under TSMC 0.18 um 1P6M CMOS process. The first circuit is designed as an implantable receiver which focuses on lowering the power consumption. The baseband circuit has a variable gain range of 56 dB with the highest and lowest gain of 70 dB and 14 dB respectively. The medium operating frequency is 20 kHz to 100 kHz. The demodulator at the back end can demodulate amplitude shift keying (ASK) signals. The implantable receiver has a power consumption of 319 uW, sensitivity of -71 dBm (BER≤ 10 -2) under 1 kbps data rate, maximum input power of 5 dBm, and a chip area of 1.2 mm2. The second circuit is designed as an external receiver outside the body to receive signals from the implantable transmitter. The baseband circuit provides a 500 kHz bandwidth, a variable gain ranging from 20 dB to 56 dB, sensitivity of -65 dBm (BER≤ 10 -2), power consumption of 16.7 mW, and a chip area of 1.2 mm2. In addition, improvements are made for the external receiver baseband circuit. In solving the DC offset problem, mixed signal method is utilized; successive approximation (SAR) is used to adjust the current of the amplifier in order to calibrate the DC offset. Furthermore, auto gain control function is added inside the circuit. The function can detect the input signal intensity and adjust the loop gain so that the output signal amplitude is suitable for the following stage demodulator circuit. The adjustable gain range is increased to 72 dB, the bandwidth of the circuit is 400 kHz. From the simulation results, the sensitivity of the receiver is -90 dBm, maximum input power of over -18 dBm, power consumption of 27.2 mW, and a chip area of 1.4 mm2.
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蔡協倫. "Baseband Receiver of DAB System by Simulink." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/24097108667378479668.
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Chen, Hou-ting, and 陳厚廷. "Design and FPGA Implementation for WiMAX Baseband Receiver." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/34362823312295820967.
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碩士國立中山大學
通訊工程研究所
95
This thesis describes the design and implementation of the baseband receiver for the IEEE 802.16-2004 Worldwide Interoperability for Microwave Access (WiMAX) wireless communications systems. Firstly, a Matlab floating-point simulation platform is built for system design. In addition to the transmitted signals and the channel models, the signal processing algorithms for the baseband receiver are verified to meet the system performance required by the standard. Then the receiver functional blocks, which include packet detection, timing synchronization, frequency synchronization, channel estimation, and the 256-point fast Fourier transform (FFT), are designed and integrated. Fixed point simulation is also conducted by using Matlab. The hardware implementation is realized by using the Verilog Hardware Description Language (HDL). Behavioral level and gate level simulations are also conducted to verify the system design. The design is downloaded to the Field Programmable Gate Array (FPGA) for system verification.
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Hung, Chao-jung, and 洪照榮. "A Baseband Chip Design of 200kbps FSK Receiver." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/61350947496557922508.
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碩士國立臺灣大學
電機工程學研究所
88
The demand of wireless communication grows rapidly in recent years. However the price of equipments for wireless transmission must be cheap enough so that customers can afford it. The goal of this work is to design and implement a low-cost FSK baseband receiver for indoor wireless communication systems. A RF front-end down-converts the RF signal to IF stage. The IF is located at 750kHz. IF of 10.7MHz is evaluated incorporated with subsampling and single sideband image rejection. IF signal is sampled at a rate of 8MHz by a slicer. Down conversion circuit translates signal from 750kHz to baseband. Balanced quadri-correlator changes the deviation of frequency to the magnitude of amplitude. Decision circuit finally decides the signal whether is logic-1 or logic-0. In order to combat carrier frequency drift through wireless transmission, an automatic frequency control (AFC) loop is adopted to compensate carrier frequency drifts between the transmitter and receiver. The AFC loop is a frequency-locked loop (FLL), which consists of frequency discriminator, loop filter and numerical-controlled oscillator (NCO). Early-late timing recovery is used to get the optimum sampling phase and recover data rate. Chip implementation obeys the design flow suitable to system designer and time of system implementation can be reduced. System simulation is complete by Matlab and SPW is used to fixed-pointed system simulation. VHDL code is derived from SPW and logic synthesis is achieved by Synopsys. The floorplan, placement and routing of the chip is complete by Candence. The chip uses Avant! standard-cell library and is fabricated with TSMC 0.35 1P4M CMOS technology. The data rate is targeted at 200kbps and the chip operates at 8MHz and 3.3V power supply. The designed low-IF baseband architecture is suitable for integration with RF front-end and A/D converter in a single chip in the future.
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Tsai, Frank S., and 蔡尚峰. "A Baseband Receiver for Fast Frequency Hopping Systems." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/09684122644962795380.
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碩士國立交通大學
電子工程系
89
Wireless Personal Area Network (WPAN) technology can bring more convenience into our future lives. The importance of WPAN can be seen from the vast amount of energy spent on developing WPAN related technology such as Bluetooth, 802.15, etc. WPAN technology requires better security and greater system capacity than other wireless technologies. Therefore, fast frequency hopping system is the most suitable physical layer system for WPAN technology. Although there are several accomplishments in the design of fast frequency hopping systems have been achieved, there are still several difficulties to over come. First of all, in a conventional fast frequency hopping system, timing recovery requires knowledge of received signal energy. Recent researches on timing recovery for fast frequency hopping requires either advanced analog circuit design or complicated fast digital circuits. In this thesis, new timing recovery method without the need of received signal energy is experimented. Second, it is difficult to design a fast frequency switching frequency synthesizers with large output frequency bandwidth. By modeling oscillators into functions, the frequency synthesizer can switch different frequency with zero acquisition time. During the development of the proposed circuits in this thesis, system simulations are required to ensure the correctness of the developed circuit. It was found that using the conventional way to simulate the entire frequency hopping system is time consuming and inefficient. After several derivations, it was found that by simplifying several equations, a more efficient channel model could be derived. This channel model not only saved time, but also was able to be written into Verilog code for gate level code verification.
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Chen, Ching-teng, and 陳靖騰. "Design of Synchronization for DVB-T Baseband Receiver." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/96651250337824074192.
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碩士國立中央大學
電機工程研究所
96
The European terrestrial broadcasting standard DVB-T has been adopted an official digital TV speciation in Taiwan. The modulation scheme for DVB-T is orthogonal frequency division multiplexing (OFDM). And the non-ideal effects of synchronization influence the orthogonality between subcarriers very much. And without orthogonality, the OFDM system will introduce Inter-Symbol Interference (ISI) and Inter-Carrier Interference (ICI), and it will be destroyed by ISI and ICI. Therefore, how to synchronize rapidly and exactly will be the major topic in our system. In this thesis, we will discuss these different non-ideal synchronization effects, including symbol boundary offset, carrier frequency offset and sampling frequency offset. We will compare and analyze the algorithms which detect these non-ideal synchronization effects, and build up a simulation platform by Matlab and C program. In integer carrier frequency offset detection circuit, we reduce chip area by using proposed architecture. And we use interpolator in sampling frequency offset compensation for all digital synchronization circuit. Finally, we integrate and implement all synchronization circuits.
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Chuang, Bing-Juo, and 莊秉卓. "Design and Implementation of IEEE 802.11n Baseband Receiver." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/58352098268172725249.
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碩士國立交通大學
電信工程系所
93
IEEE 802.11n is known as the specification for the next generation high-speed WLAN systems. The distinct baseband feature is the use of multi-input multi-output (MIMO) OFDM technology. In this thesis, we consider the design and implementation of an IEEE 802.11n baseband receiver (with the TGn Sync proposal). We divide the receiver into the front-end and the back-end receiver. The front-end receiver includes modules of packet detection, automatic gain control, frequency offset estimation, frame detection, channel estimation, and fast Fourier transform (FFT). The back-end receiver includes modules of the minimum mean square error (MMSE) signal estimator, the soft-bit demapper, and the Viterbi decoder. We first design the front-end receiver and perform system simulations for the whole receiver. Using the FPGA design flow, we then implement the front-end receiver for a 2x2 system. In the design, we use the CORDIC algorithm for phase estimation and rotation and propose efficient structures for packet detection and frequency offset estimation. Simulations show that our design perform properly in random generated MIMO channels.
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Chen, Chun-Hao, and 陳春豪. "Analog baseband circuit design for direct conversion receiver." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/17655369005105974293.
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碩士國立臺灣大學
電子工程學研究所
91
This paper presents a circuit design and implantation for the analogous filter and amplifier sections of a direct conversion receiver. It is designed for 5GHz wireless LAN fabricated in a TSMC 0.35-µm SiGe BiCMOS technology. The design includes a first order low pass channel selection filter, a fifth order Butterworth filter, two stage programmable gain amplifiers (PGA), dc offset cancellation circuit, and a PTAT current source. The Gm-C channel selection filter can be programmable to two different bandwidths from 10 to 20MHz radio frequency (RF) spacing. The overall PGA varies from 8dB to 56dB with 2dB per step.
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Huang, Jun-Jue, and 黃俊傑. "DVB-T receiver design : algorithms and baseband architecture." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/rw6g99.
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碩士國立交通大學
電信工程系所
92
To offer high-bit-rate high performance bandwidth-efficient multimedia services and combat the inevitable frequency-selective fading, the European standard for terrestrial digital video broadcasting (DVB-T) has adopted the orthogonal frequency-division multiplexing (OFDM) technique for transmission over wideband wireless channels. This thesis presents a baseband architecture for a single frequency network (SFN) DVB-T receiver. We study algorithms for the baseband signal processing unit. These algorithms serve the functionalities of time and frequency synchronization, channel estimation/equalization and impulse noise suppression. In particular, we propose a decision-aided algorithm for joint channel estimation and impulse noise suppression. The channel estimation part makes full use of the time and frequency correlation information. The performance of each subsystems and the overall system is evaluated through computer simulations and related parameters are optimized accordingly.
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Su, Wei-Chen, and 蘇韋禎. "Diversity Combining Technique and Outer Receiver Design for the IEEE 802.11a Baseband REceiver." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/29319681968900133306.
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碩士國立中正大學
通訊工程研究所
92
As the wireless communication becomes more demanding, the wireless local area network (WLAN) become more popular. Among the various industrial standards, the orthogonal frequency division multiplexing (OFDM) based IEEE 802.11a provides data rates as high as 54 Mbps and attracts most attention. The design of an IEEE 802.11a baseband tranceiver is therefore important. In this thesis, several design techniques and issues for an 11a baseband transceiver are studied and discussed. Diversity technique, channel estimation, and decoder of the convolutional code are the emphasis of this thesis. Performance study of the maximal ratio combining (MRC) based diversity technique and channel estimation from computer simulations is reported. The hardware structure and circuit design of the Viterbi decoder, which is used to decode convolutional code, is studied and verified. Finally, some tricks, including the use of block memory, about FPGA is reported.
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Chen, Yen-Yi. "Design and Implementation of a Bluetooth IF/Baseband Receiver." 2004. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-0607200421335700.
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胡獻中. "CMOS IF/Baseband Downconverter for DSSS WLAN Receiver AFE." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/50821740409330682767.
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碩士國立臺灣大學
電機工程學研究所
90
This thesis is aimed at developing an analog front-end VLSI architecture that deals with IF signal in wireless LAN system. The system performs signal down-conversion and amplitude control ability exploiting limiting amplifier. Amplitude control plays an important role in the receiver especially wireless communication, because of the large range of receiving signal strength. Two commonly used schemes are Automatic Gain Control (AGC) and limiting amplifier. These two methods will be discussed and compared with each other. The limiting amplifier has the advantage of simple structure and fast signal response is adopted in our system. The frequencies of RF, IF and baseband chosen are 2.4GHz, 280MHz and 17.6MHz respectively. The whole IF/Baseband analog front end consists of limiting amplifier, Received Signal Strength Indicator, down conversion mixer, ring oscillator and 5th order Butterworth lowpass filter. The limiting amplifier is used to provide constant magnitude for the input signal with 80dB dynamic range and about 280MHz frequency. The RSSI detects the strength of input signal and delivers the exponential equivalent value within 3dB error. The mixer followed by a low pass filter (LPF) down converts the 280MHz IF signal into baseband. The local oscillation signal is provided by a ring-oscillator. The LPF -3dB frequency can be tuned into one of the 4 discrete values: 2.2/4.4/8.8/17.6 MHz, according to the chip rate in spreading spectrum system. The architecture and circuit design is mainly aimed at low power consumption and high speed. All the circuits employ 0.35μm 1P4M TSMC CMOS standard technology using single power supply 3V. The circuits of the IF/Baseband analog front end have been verified with chip testing. The chip area is 2.4mm╳2mm with individual blocks for testing. The total power consumption is 150mW.
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Lin, Keng-Hsien, and 林耕賢. "Design of a Baseband Receiver for DVB-T Standard." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/92232591702191749999.
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碩士國立臺灣大學
電子工程學研究所
93
This thesis proposes a baseband receiver and a baseband equivalent channel model according to the transmitter and system specification of Euporean DVB-T standard. The baseband equivalent channel model includes effects of multipath fading channel, Additive White Gaussian Noise (AWGN), Carrier Frequency Offset (CFO), Sampling Frequency Offset (SCO), and phase noise. DVB-T system has two choices in Fast Fourier Transform (FFT) size and four choices in Guard-Interval Ratio (GR) size, so a DVB-T reciever should detect FFT mode and GR mode used in the transmitter in the beginning. This thesis proposes a two-stage mode detection algorithm to perform the function, and combines algorithms of symbol timing detection, CFO acquisition, compensation, and tracking as well as SCO, 2k-8k FFT processor, phase modification, channel estimation and compensation, soft-out demapper, and soft-in Viterbi decoder to implement the whole system of DVB-T receiver. In hardware circuit design, this thesis also proposes to use output SNR instead of Bit Error Rate (BER) as the metric of optimum wordlength and use piecewise linear approximation algorithm to save hardware cost with tolerable approximation error. Through system performance simulation and verification of whole system RTL Verilog, the proposed DVB-T baseband receiver is proven to work well.
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Wei, Ting-Zhen, and 魏庭楨. "Design of Carrier Recovery for DVB-T Baseband Receiver." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/73204334852298075689.
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碩士國立中央大學
電機工程研究所
93
Digital Video Broadcasting for Terrestrial (DVB-T) is the digital TV broadcasting standard in Taiwan. The adopted communication technical is Orthogonal Frequency Division Multiplexing (OFDM). OFDM is a kind of multi-carrier modulation and divides the data into several differential and orthogonal sub-carriers. In this thesis, we focus on synchronization and channel estimation of DVB-T and build a simulation platform using Matlab and C language. This platform contains digital down conversion, carrier frequency synchronization, timing synchronization and frequency domain channel estimation. Finally, we propose a memory reduction architecture for integer carrier frequency offset estimation. This architecture reduces the usage of memory by 90 %, the memory access number is reduced by 94% and the estimation time is reduced by 37%.
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Chen, Chiao-En, and 陳喬恩. "Design and Implementation of a Synchronous CDMA Baseband Receiver." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/58598292281388971588.
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碩士國立臺灣大學
電機工程學研究所
88
In this thesis, the architecture of an all-digital quaternary phase-shift keying (QPSK) synchronous code division multiple access (synchronous-CDMA) baseband transceiver for HFC CATV-networks upstream transmission is proposed. Conventional CDMA techniques provide the robustness to transmit data over the ingress noise environment, but the capacity tends to degrade as more users share the same spectrum. Synchronous-CDMA avoided this problem by synchronizing all of the cable modem units to the headend. Every transmitted signal received by the headend is aligned in code and is orthogonal to each other. This reduces multi-user-interference (MAI) and increases spectral efficiency. For the sake of timing synchronization, we proposed an upstream transmission system which includes two physical channels: the upstream Asynchronous Request Channel (ARCH) and the upstream Synchronous Data Channel (SDCH). Each customer who wants to connect to the network has to listen to the downstream pilot channel and contact the headend by the ARCH asynchronously. The headend receives the request by the ARCH receiver and then calculates the round-trip delay. The timing information is fed back to the requesting cable modem unit by the downstream pilot channel. After that, the cable modem unit gets synchronized, switch to the SDCH transmitter, and begin to transmit data. The data will be recovered by the SDCH receiver at the headend. The basic principles of synchronous-CDMA and the characteristics of HFC upstream channel are introduced in the thesis. Both behavior and circuit level simulations are performed to verify the proposed architecture. Furthermore, the proposed architecture is implemented and verified by FPGA emulation.
27
Wei-Cherng, Liao, and 廖偉成. "Design & Implementation of IF/Baseband Receiver for Bluetooth." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/10867581549978188613.
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碩士國立臺灣大學
電機工程學研究所
88
Wireless communication has been widely used in personal communication systems in recent years. It comes from the advances in digital communications, digital signal processing and very large scale integrated circuits (VLSI) techniques. In 1998, a new integrated technology, named Bluetooth, was formed for local area voice and data communications. It is an open specification personal wireless networking standard which is characterized by its low-power, short-range, wireless application. Therefore, a system solution for Bluetooth is porposed in this thesis. This thesis can be divided into three parts : system architecture design and two integrated circuit implementation for frequency hopped spread-spectrum (FH-SS) communication system. System architecture for Bluetooth is developed first. Referring to Bluetooth specification, design link budget and consideration are estimated to meet the standard. Furthermore a total solution from RF to IF and finally baseband is proposed. Second, a 4-bit ash type analog to digital converter (ADC) used in IF analog front end was designed and implemented. Designed ADC can operate at 8 MHz with 750 KHz IF input signal. Therefore, a 8-oversampled, digitized IF signal can be obtained for baseband signal processing. The ADC was implemented in 0.35 um SPQM CMOS technology and occupied 650 x 610 um2 active area. The sampling rate is 8 Msamples/second and the total power dissipation is 48 mW at a 3.3 V supply voltage. The second module is an all-digital low-IF FH-SS GFSK receiver. This receiver consists of three parts: forward demodulation path, carrier recovery loop, and timing recovery loop. The center frequency of this low-IF receiver is 750 KHz and the sampling rate is 8 Ms/s. Architecture design and hardware optimization was performed in high level computer language before gate-level design and layout implementation. The receiver was fabricated through a 0.35 um SPQM CMOS technology occupied 1.6 x 1.6 mm2 active area. The receiver was functionality tested and proven to work at a speed of 2 Mbps at a single 3.3 V power supply. And for low power applications, this chip can be slowed down to 1 Mbps (compatible to Bluetooth/IEEE 8.2.15) where it draws 106 mW from a 2.6 V supply voltage.
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Leong, Edmund Wen Jen, and 梁文禎. "ISI-ICI-Suppression Equalizer for 60GHz FBMC Baseband Receiver." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/965s6b.
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碩士國立交通大學
電機資訊國際學程
104
This thesis reviews the FBMC transmission system and its characteristics. Conventionally the FBMC waveform do not make use of the cyclic prefix, which makes it vulnerable to multipath ISI. In view of this, the time domain equalizer and the frequency domain minimum mean square error (MMSE) multi-tap equalizer is reviewed for their ability to perform equalization in the presence of ISI for an FBMC system. The MMSE joint feedback feed-forward equalizer (MJFFE) is proposed to deterministically suppress the ISI and ICI suffered by the FBMC in a long multipath channel. A coefficients calculation method for the MJFFE is also presented. The three equalizers mentioned above are simulated with the FBMC system, with IEEE 802.15.3c frame structure in NLOS multipath channels that is generated from channel models provided for the IEEE 802.15.3c standard. The average RMS delay spread of the simulated multipath channel is 3.4ns, while the sampling rate is 2.64GHz. Simulation results show that the time domain equalizer and the frequency domain MMSE multi-tap equalizer do not perform well in the highly dispersive multipath channels. The proposed MJFFE is able to achieve the 10-2 bit error rate threshold at SNR that is 0.6dB lower than that of a frequency domain one-tap zero-forcing equalizer. Compared to the one-tap zero-forcing equalizer, the MJFFE also significantly lowers the BER error floor. The MJFFE has very high computation complexity due to the complicated coefficients calculation method. By using time multiplexing, memory sharing and computing element sharing methods, the complexity of the whole MJFFE system is reduced by approximately 50%. The MJFFE system is then implemented with the TSMC 40nm general purpose standard cell library at worst case conditions and temperature of 125C. The final area and gate count is 1.335 mm2 and 1882k respectively. The estimated power consumption operating in the IEEE 802.15.3c frame is 50mW, which translates to 2.6pJ/b.
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Peng, Chen-Hung, and 彭振洪. "Design of a Baseband Receiver for Optical OFDM System." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/04714752398381009972.
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碩士國立清華大學
電機工程學系
98
In recent years, technology of communication devices is developed rapidly due to the growing demand for transmission system. In order to provide large bandwidth for high quality services, realizing a transceiver for optical OFDM system becomes very important. In this thesis, we propose a design of the baseband receiver with a set of 16-way parallel processing for the optical OFDM system. The baseband receiver contains the frame detection, CFO estimation and compensation, channel estimation, and equalization. We complete the hardware design of the system and show the simulation results under the optical channel. Besides, this thesis proposes a fast Fourier transform(FFT) with high parallelism based on pipeline architecture and integrate it in optical OFDM system to reach the high-throughput goal. Finally, the FFT processor is designed and implemented as a single chip using 90nm UMC CMOS technology and Faraday cell library. The chip with a set of 16-way parallel processing can achieve the throughput up to 2.67GS/s.
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Wu, Wei-jun, and 吳偉俊. "Implementation and performance evaluation of DVB-H baseband receiver." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/38817656963035295631.
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碩士國立中山大學
通訊工程研究所
94
In this thesis, the baseband signal processing and hardware implementation of the Digital Video Broadcasting - Handheld (DVB-H) are investigated. DVB-H is an emerging and promising wireless communication system and is based on the Orthogonal Frequency Division Multiplexing (OFDM) scheme. The algorithms for baseband signal processing include timing synchronization, frequency offset compensation, channel estimation, and scatter pilot detection. The developed algorithms are verified using Matlab program to meet performance requirements. Then, the algorithms are implemented using Verilog hardware description language (HDL), which is downloaded to Xilinx FPGA (Field Programmable Gate Array) for system verification. The selected algorithms for baseband signal processing have to meet the both the requirements of system performance and low complexity.
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Chen, Yen-Yi, and 陳宴毅. "Design and Implementation of a Bluetooth IF/Baseband Receiver." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/65830016637618669595.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
92
In the recent years, with the growth of semiconductor process and technology, the wireless communication has been developed more quickly, like IEEE 802.11 series, 3GPP, and Bluetooth technology etc. The Bluetooth Special Interest Group (SIG) was founded in 1998, and they defined Bluetooth as a low cost, low power, short range radio technology. In this Thesis, we propose a digital IF/Baseband receiver for Bluetooth specification, its data rate is 1 Mb/s, operation clock is 16 MHz, and intermediate frequency is defined as 800 KHz. The I and Q parts of the IF signal after AD converter are the input of our IF/Baseband receiver. In this design, we consider three nonidealities: carrier frequency offset, sampling frequency offset, and additive white Gaussian noise. Since Bluetooth uses a short range radio technology, we do not consider multi-path delay and Doppler effect. We let the IF I and Q signals be influenced by the above three effects, then we use our receiver to demodulate these signals and check whether we can deliver a correct output. To prove our design, we use Matlab, Verilog, and other CAD tools to run simulations, and then we use FPGA to verify our simulation results. We observe performance factors, like bit error rate (BER) and power consumption, and check whether they conform to the Bluetooth specification or not. Finally, we tape out this chip by using TSMC 0.35μm Mixed Signal (2P4M) CMOS process.
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Chang, Wei-Tang, and 張偉棠. "All Digital Baseband Direct-Sequence Spread-Spectrum Receiver Design." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/35001830324841633752.
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碩士國立交通大學
電信工程系
88
In direct-sequence spread-spectrum receiver design, code synchroni- zation is an important part. The main purpose of this thesis is to investigate the steady state tracking performance of a all digital baseband noncoherent code tracking loop in the presence of additive white Gaussian noise (AWGN). We also consider issues related to the designs of subsystems. These practical concerns include the effect of ADC (quantizer), the selections of interpolation filter and local code pulse shape, the design of code tracking lock detector and carrier phase recover. Proper solutions are provided for these concerns. We give either analytical or simulated estimations of the corresponding numerical performance. The bit error probability performance of the overall receiver is given, taking all the above practical and nonideal effects into account. Numerical results show that our design is indeed appropriate for meeting the system specifications.
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Han-Chiang, Su. "System Design of Baseband Receiver for the DVB-H Standard." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2806200510453800.
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Chang, Chiao-Chih, and 張喬智. "Design and Implementation of a Baseband Receiver for VDSL System." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/08934153237092346327.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
90
In this work, we propose a baseband transceiver architecture for ETSI VDSL standard using discrete multi-tone modulation (DMT). According to Channel impairments defined in the standard, such as additive white Gaussian noise (AWGN), near end crosstalk (NEXT), far end crosstalk (FEXT), radio frequency interference (RFI) and impulse noise, algorithms for symbol boundary estimation, sampling clock offset estimation and compensation, fast Fourier transform(FFT), channel estimation/equalization, and forward error correcting code (FEC) decoder are designed and integrated into the receiver architecture. Fixed-point system simulation results show that the proposed receiver architecture is capable of very high-rate transmission in digital subscriber loop channels. A baseband receiver chip is implemented to verify the proposed architecture. The FEC decoder and FFT unit are not included in this chip to maintain flexibility and reduce complexity. The technology used is TSMC 1P4M CMOS technology. The area of this chip is 4.23 x 4.11 mm2, and it consists of 287,929 transistors and the operating clock frequency is 35 MHz. Furthermore, test points and test scan chains are inserted to increase testability.
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Luo, You-Cheng, and 羅友成. "DSP Realization and ASIC Design of 3G WCDMA Baseband Receiver." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/28179751572927463620.
Full textAbstract:
碩士國立交通大學
電子工程系
90
In this thesis, DSP realization and ASIC architecture design of the baseband receiver of the third Generation Mobile Communication (Wideband Code Division Multiple Access) systems were presented. In WCDMA system, a baseband receiver includes Rake receiver, channel estimator, and code synchronization circuit. First, we simulated and analyzed the whole baseband receiver system in C language for Rake receiver, channel estimation of linear interpolation and sliding window method, and path search and tracking in code synchronization. We implement the WCDMA baseband receiver on Innovative Integration Company’s Quatro6x DSP board. Finally, the WCDMA baseband receiver architecture suitable for ASIC design is proposed. With low-power correlator design and low-complexity correlation algorithms design, the architecture can achieve a low-power consumption and high performance baseband receiver.
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Su, Han-Chiang, and 蘇漢強. "System Design of Baseband Receiver for the DVB-H Standard." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/91946498729630151431.
Full textAbstract:
碩士國立臺灣大學
電信工程學研究所
93
We investigate a DVB-H (Digital Video Broadcasting – Handheld) baseband receiver in the thesis. The architecture is based on the DVB-H standard which is published by ETSI (European Telecommunication Standard Institute). Mobility is an important requirement, meaning that access to services should be possible not only at almost all indoor and outdoor locations but also while moving in a vehicle at high speed. However, the situation is worsened by the fact that a multi-antenna diversity approach is almost impossible because of space limitations. In this work, we propose a new algorithm which only uses a single antenna to compensate for the Doppler effect. When the carrier frequency of the transmitted signal is about 550 MHz, the tolerable maximal speed is about 110 Km/h. The method has much better performance than the conventional algorithm. In addition, we also propose some new algorithms to improve the performance of symbol timing synchronization, carrier frequency offset estimation and channel estimation. Finally, we make simulation in Simulink environment to demonstrate that the receiver we design indeed works well.
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Chu, Chin-Wei, and 朱志偉. "Design of a Baseband Down-Link Receiver for 3GPP-LTE." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/68707897503520023690.
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碩士國立清華大學
通訊工程研究所
96
科技的日新月異，手機也開始追求著高傳輸率，以致影像傳輸的功能，而且還要在高速環境中，能有良好的收訊，而第四代手機系統也正追求著這樣的目標。目前第四代手機規格標準的競爭，非常激烈，最大的兩大競爭對手為Mobile Worldwide Interoperability for Microwave Access技術的標準，簡稱mobile WiMAX標準也就是IEEE 802.16e與3rd Generation Partnership Project Long Tern Evolution所使用的技術規格，簡稱3GPP LTE，這兩大對手的共通點在於其傳輸技術都是利用正交分頻多工存取技術(OFDMA)，而3GPP LTE期望能將傳輸率達到100M bps，並且接收機可以在時速250 km/hr高速移動下，正常接收。著眼於3GPP LTE的優勢，所以在本論文中，乃是根據3GPP LTE所提出的標準，設計了一個可以使用在不同傳輸頻寬下的正交分頻多工系統之基頻下傳接收機。其中包含了低成本的取樣頻率轉換處理器可以操作在不同的頻寬下得到不同的取樣頻率，來實現scalable bandwidth 概念。還有整合可感知通道低功率快速傅立業轉換器，此快速傅立業轉換器與一般常見快速傅立業轉換器相比約可降低36%的功率損耗，並且此傅立業轉換器可以支援FFT的大小從128點到1024點。以及在通道估測部份，我們設計了可重置通道估測內插器，利用polynomial interpolation，不同階數的內插方程式的組合，可以根據不同的通道環境下來使用，而我們主要模擬的環境有三種，一是small cells，二是urban area，以及 hilly terrain。另外還包括了符元時間偵測，取樣頻率同步，載波頻率回復等。最後我們完成其系統電路設計及模擬，然後根據cell-based設計流程，並且使用tsmc0.18μm cell library得到其合成的結果。
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Liu, Chia-Hsun, and 呂嘉勳. "Design of a DVB-T Baseband Receiver with Antenna Diversity." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/95283850807380128043.
Full textAbstract:
碩士國立臺灣大學
電信工程學研究所
95
Digital Video Broadcasting-Terrestrial (DVB-T) adopted Orthogonal Frequency Division Multiplexing (OFDM) technique which exhibits superior characteristics in terms of high-bit-rate transmission, efficiency in spectral utilization and simplicity in combating multi-path fading for broadcasting over wideband wireless channels. The DVB-T system has higher quality (HDTV、SDTV) than the traditional analogue TV and it had been formally started broadcasting in Taiwan on 2004. Primarily, DVB-T was designated to the fixed and portable reception of video services. However, by the increasing demand for mobile reception, there are limitations of the available DVB-T system operated in a mobile environment. As compared with handheld mobile devices, because of space limitations, mobile DVB-T with multi-antenna diversity technique is an effective approach to combat Doppler effects. In this thesis, we design and verify a DVB-T baseband receiver with dual-antenna diversity by signal processing procedure. The investigation major focuses on the 8k transmission mode operated in Taiwan and the mobile DVB-T device employed such as in a vehicle is moving in Typical Urban (TU6) environment. The signal format of the transmission mode is based on the DVB-T standard specified by ETSI. Furthermore, we establish the TU6 channel model with dual-antenna reception. In addition, symbol timing synchronization, carrier frequency synchronization and channel estimation are designed and discussed in the architecture of the receiver. From the simulation results, it shows that the DVB-T dual-antenna receiver with Maximal Ratio Combining (MRC) can achieve excellent system performance in a mobile environment. We also know that the DVB-T dual-antenna receiver with MRC outperforms the conventional single-antenna receiver. Besides, the simulation results demonstrate that the DVB-T 2k mode exhibits higher mobility than 8k mode as well.
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Liu, Chia-Hsun. "Design of a DVB-T Baseband Receiver with Antenna Diversity." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1507200723443500.
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Hsu, Jing-Ming, and 許景銘. "Implementation of DVB-T Baseband Receiver with a SDR platform." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/w97zhp.
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碩士國立中央大學
通訊工程學系
105
Digital Video Broadcasting - Terrestrial is a digital video broadcast standard adopted in Taiwan, and it is ratifies by European Broadcast Union. In this thesis, we implement the DVB-T Baseband Receiver with a Realistic Software-defined Radio platform. Our laboratory combine FPGA and Radio Frequency module(AD9361) to finish SDR platform. This baseband receiver need the digital signal processing units which are down sampling, time synchronizer, frequency synchronizer, Fast Fourier Transform processor, channel estimator, channel equlizer. First, recording DVB-T signal is programmed using MATLAB to demodulate the signal. Second, the specification for each digital signal processing units is designed, progrmaed by using Verilog hardware description language and verified with ModelSim. Then, the real-time haradware is implemented and verified with SDR platform. The measurement and analysis of recording signal in the difference places by DVB-T Baseband Receiver with a Realistic Software-defined Radio platform.
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CHOU, CHIA-PENG, and 周家鵬. "Some Baseband Signal Processing Techniques for the MIMO-OFDM Receiver." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/jt573u.
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博士國立中正大學
通訊工程研究所
106
In this dissertation, some baseband signal processing techniques are studied. First, the Forney-style factor graphs are used for modeling space-frequency-coded MIMO OFDM systems over the frequency-selective fading channels. The Gaussian message passing mechanism for the factor graphs of the Alamouti scheme and linear transformation are analyzed . A new decision rule is derived in terms of the mean vector and covariance matrix of modulated vector symbols. The K-best algorithm with reduced complexity is used to justify the effectiveness of our receiver. Next, at the analog front end of receivers, due to the imperfection of implementation of the downconversion mixer, there have some mismatch between the in-phase and quadrature - phase (IQ) components of the received signals, a phenomenon leads to the IQ imbalance problem. If the IQ imbalance is not compensate, it will cause the performance degradation. A joint least square(LS) estimation of the channel impulse response and IQ imbalance parameters for pilot-assisted OFDM system in low-IF receivers is proposed. After that, a training based joint LS estimation of channel impulse response, IQ imbalance parameters and DC offset parameter in direct conversion OFMD receiver by using training symbol is proposed. Finally, the solution for single antenna IQ imbalance problem is extended to solve the IQ imbalance in the MIMO OFDM system. By exploiting the block-typed pilots, a unified design of low-IF and direct conversion MIMO OFDM with joint LS estimation of channel impulse responses, IQ imbalance parameters, and DC offset parameters are presented. There is only one OFDM block needed for training symbols and the training sequence can be arbitrarily chosen. Through the Matrix Inverse Lemma, the matrix inverse operation can be replaced by few vector product and effectively to reduce the computing complexity. The simulation results show that all the parameters are accurately estimated.
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Wang, Ching-Wen, and 王經文. "Implementation of the DVB-T Receiver For Baseband Processing Algorithms." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/a8ggsc.
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碩士國立臺北科技大學
電腦與通訊研究所
95
In the recent year, Orthogonal Frequency Division Multiplexing (OFDM) becomes the technique of the popular choice for the transmission. Because this technique can provide high data rate transmission within the bandwidth limit. Furthermore, in the multipath fading channel, it also have high performance by guard interval. Since the evolution of Digital Signal Processing, it has been used for many transmission systems such as DAB (digital audio broadcasting),DVB (digital video broadcasting), WLAN (wireless local area networking)…etc. Previously, most researches about the performance of the Digital Video Broadcasting-terrestrial (DVB-T) systems are studied in hardware scheme and simulate in the channel environments assumed by researchers. Only a few of researches are researched by software and in the real channel environments. We keep on researching the previous program of the lab about DVB-T receiver. We’ll change the method of interpolation to calculate more accurate channel coefficients. And we will consider the channel state information into the metric to get higher performance. And we‘ll propose some problems that we will solve in the future.
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Hsieh, Ming-Che, and 謝明哲. "DSP Software Implementation of an IEEE 802.16-2004 Baseband Receiver." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/30320586337516641904.
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碩士國立臺灣大學
電子工程學研究所
98
In this Thesis, we propose a baseband physical layer transceiver architecture according to the 802.16-2004 OFDM specifications. The baseband channel model is defined according to the SUI channel model, with Additive White Gaussian Noise (AWGN), carrier frequency offset, and sampling clock offset. To recover the data, suitable algorithms are used to detect the symbol boundary, to estimate and compensate carrier frequency offset and sampling clock offset, to interpolate, and to perform the frequency-domain equalization in the receiver. Moreover, the TMS320C6416 DSP of Texas Instruments (TI) is used in software implementation. By a sequence of code development flow, the operation cycles are reduced and the inner receiver is able to meet the real time requirement.
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Chen, Yu-Yen, and 陳語煙. "Baseband Channel Simulation and Communication Receiver Implementation Using GPU Acceleration." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/30833807545253079954.
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碩士國立臺灣大學
電子工程學研究所
97
The Graphics Processing Unit (GPU) has been evolving for various generations, from a fixed-funcion graphics pipeline to a programmable parallel processor. Due to the fact that GPU has a high memory bandwidth and a high Giga FLoating points Operations Per Second (GFLOPS) performance, it is used to accelerate the computations of non-graphics data, which is also referred as General Purpose Computing on Graphics Processing Units (GPGPU). However, not all algorithms benefit equally from this technique. The GPU computing is only suitable for algorithms with repeating computation and low data dependency, which means with a high degree of parallel computing characteristics. There are mainly two groups of communication applications analyzed and implemented in this thesis, which are all implemented and simulated using general personal computer under the NVIDIA CUDA environment. First, the method and result of the baseband channel simulation implementation using parallel computing concept is presented in the thesis. Then the parallel computing concepts are being used to implement the communication receiver. Both of the speedup performance and the GPU programming experience will be covered in this thesis.
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Yang, Shuen-Chuan, and 楊順全. "Pulse Shaping and Baseband Receiver Design for DS-UWB System." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/11909790569658946813.
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碩士國立成功大學
電腦與通信工程研究所
94
Ultra-Wideband (UWB) technology is one of the promising solutions for short-range indoor wireless communication applications. The attractive feature of the UWB communication systems is high communication capability (greater than 400 Mbps) with low transmission power. Now there are two proposals for UWB physical layer. One is DS-CDMA UWB proposed by Motorola, which preserves the original UWB pulses nature. The other is a Multi-band approach combining frequency hopping with Orthogonal Frequency Division Multiplexing (OFDM UWB) proposed by Intel. In this thesis, we will first introduce some pulse waveforms design for DS-UWB system. On the other hand, we also design a robust receiver to combat ISI due to dense multipath. In this part, we will follow the packet format of DS-UWB system to introduce the process of synchronization, coarse channel estimation, SFD detection, fine channel estimation, rake receiver, and equalizer. Finally, we will compare the system performance under different UWB channel model.
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詹崇志. "Design and Implementation of Baseband Space Diversity Receiver for IEEE802.11a." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/44371077249890933552.
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碩士國立臺灣大學
電子工程學研究所
91
Recently, more and more research focuses on the technique of wireless local area network (WLAN). With the development of very large scale integration (VLSI), we have implemented the IEEE 802.11a baseband transceiver into a single chip. The design of the modules in the baseband transceiver system, including the coarse symbol boundary detector, the fine symbol boundary detector, the coarse carrier frequency offset (CFO) estimation loop, the CFO tracking loop, the fast fourier transform (FFT) processor, the frequency domain equalizer, and the transmitter blocks, will be illustrated in the thesis. Nevertheless, there exists some circuit problems in the chip, such that a large amount of errors will be caused. Hence, we have to adjust some parameters and the specification to make the chip work more regularly. Furthermore, with the knowledge of space diversity, we redesign the IEEE 802.11a baseband space-diversity receiver on the basis of the existent chip. We employ two antennas in the receiver to collect two signals from independent paths and apply the MRC technique to combine those signals. We make use of several circuits inside the chips and implement the others in the DSP development board.
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Fu, Yi-How, and 傅奕豪. "Baseband Receiver Algorithms for OFDM-Based Wireless Local Area Networks." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/3ksw3p.
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碩士國立清華大學
通訊工程研究所
92
Wireless local area network (WLAN) are now becoming a viable alternative to traditional wired solutions, due to the advantage of ease of installation and mobility. IEEE 802.11a is a high-rate WLAN standard, based on the popular orthogonal frequency division multiplexing (OFDM) technology. In this thesis we manage to combine frequency, timing, and frame synchronization plus channel estimation and detection based on the 802.11a standard. The channel considered is a multipath channel with additive white Gaussian noise (AWGN) and is assumed to be quasi-static. Based on the maximum likelihood (ML) criterion, we have derived estimator algorithms to conduct the above mentioned synchronization tasks. Jointly with previous proposed channel estimation and combined detection/decoding algorithms, an entire baseband receiver has been obtained. Simulation results show that our baseband receiver performs similarly as those previously proposed best methods, but requires lower complexity.
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Kulkarni, Raghavendra Laxman. "Analog Baseband Filters and Mixed Signal Circuits for Broadband Receiver Systems." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10550.
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Data transfer rates of communication systems continue to rise fueled by aggressive demand for voice, video and Internet data. Device scaling enabled by modern lithography has paved way for System-on-Chip solutions integrating compute intensive digital signal processing. This trend coupled with demand for low power, battery-operated consumer devices offers extensive research opportunities in analog and mixed-signal designs that enable modern communication systems.
The first part of the research deals with broadband wireless receivers. With an objective to gain insight, we quantify the impact of undesired out-band blockers on analog baseband in a broadband radio. We present a systematic evaluation of the dynamic range requirements at the baseband and A/D conversion boundary. A prototype UHF receiver designed using RFCMOS 0.18[mu]m technology to support this research integrates a hybrid continuous- and discrete-time analog baseband along with the RF front-end. The chip consumes 120mW from a 1.8V/2.5V dual supply and achieves a noise figure of 7.9dB, an IIP3 of -8dBm (+2dbm) at maximum gain (at 9dB RF attenuation).
High linearity active RC filters are indispensable in wireless radios. A novel feed-forward OTA applicable to active RC filters in analog baseband is presented.
Simulation results from the chip prototype designed in RFCMOS 0.18[mu]m technology show an improvement in the out-band linearity performance that translates to increased dynamic range in the presence of strong adjacent blockers.
The second part of the research presents an adaptive clock-recovery system suitable for high-speed wireline transceivers. The main objective is to improve the jitter-tracking and jitter-filtering trade-off in serial link clock-recovery applications. A digital state-machine that enables the proposed mixed-signal adaptation solution to achieve this objective is presented. The advantages of the proposed mixed-signal solution operating at 10Gb/s are supported by experimental results from the prototype in RFCMOS 0.18[mu]m technology.
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Yang, Hung-wen, and 楊宏文. "Integration of MB-OFDM UWB Baseband Inner Receiver Design and Channel Shortening Technology with Multiple Receive Antennas." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/98589197545139843358.
Full textAbstract:
碩士國立清華大學
通訊工程研究所
95
UWB system is one of the most popular broadband wireless access technologies. Its main advantage is the capability of transmitting high rate data in a short distance. It is also a potential candidate for future wireless personal area network, and can be widly adopted in transmission of data, video and voice. In this thesis, we implement a baseband inner receiver for MB-OFDM UWB, including synchronization, Fast Fourier Transform, and channel equalization circuits. We also propose a channel shortening with receiver diversity scheme to deal with multipath environment. Detail simulations and derivations are also given in this thesis.
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Wu, Tsung-Han. "DVB-T Baseband Receiver Design Based on Multimode Communication Silicon IPs." 2004. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2707200416070600.
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