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Journal articles on the topic 'Baseband Receiver'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

MAHMOUD, SOLIMAN A., and EMAN A. SOLIMAN. "MULTI-STANDARD RECEIVER BASEBAND CHAIN USING DIGITALLY PROGRAMMABLE OTA BASED ON CCII AND CURRENT DIVISION NETWORKS." Journal of Circuits, Systems and Computers 22, no. 04 (April 2013): 1350019. http://dx.doi.org/10.1142/s0218126613500199.

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In this paper, a digitally programmable OTA-based multi-standard receiver baseband chain is presented. The multi-standard receiver baseband chain consists of two programmable gain amplifiers (PGA1 and PGA2) and a fourth-order LPF. The receiver is suitable for Bluetooth/UMTS/DVB-H/WLAN standards. Three different programmable OTA architectures based on second generation current conveyors (CCIIs) and Current Division Networks (CDNs) are discussed. The programmable OTA with the lowest power consumption, moderate area and good linearity — better than -50 dB HD3 — is selected to realize the multi-standard baseband receiver chain. The power consumption of the receiver chain is 6 mW. The DC gain varies over a 68 dB range with 1 MHz to 13.6 MHz programmable bandwidth. The receiver baseband chain is realized using 90 nm CMOS technology model under ±0.5 V voltage supply.

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2

Lee, Joohyun, Hyuk Kim, Jinkyu Kim, Bontae Koo, Nakwoong Eum, and Hyuckjae Lee. "Design of AT-DMB Baseband Receiver SoC." ETRI Journal 31, no. 6 (December 4, 2009): 795–802. http://dx.doi.org/10.4218/etrij.09.1209.0009.

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3

Ferris, R. H., and S. J. Saunders. "A 256 MHz Bandwidth Baseband Receiver/Spectrometer." Experimental Astronomy 17, no. 1-3 (June 2004): 269–77. http://dx.doi.org/10.1007/s10686-005-6079-9.

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4

Kharchenko, Volodymyr, Yuri Barabanov, and Andrii Grekhov. "MODELING OF ADS-B DATA TRANSMISSION VIA SATELLITE." Aviation 17, no. 3 (October 7, 2013): 119–27. http://dx.doi.org/10.3846/16487788.2013.840057.

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For modelling transmission of ADS-B messages via low-orbit satellite constellation Iridium, the original model of a communication channel “Aircraft-to-Satellite-to-Ground Station” was built using MATLAB Simulink. The model comprises “Aircraft Uplink Transmitter” (Bernoulli Random Binary Generator, Convolutional Encoder, BPSK Baseband Modulator, High Power Amplifier with a memoryless nonlinearity, Transmitter Dish Antenna Gain), “Uplink Path” (Free Space Path Loss, Phase/Frequency Offset), “Satellite Transponder” (Receiver Dish Antenna Gain, Satellite Receiver System Temperature, Complex Baseband Amplifier, Phase Noise, Transmitter Dish Antenna Gain), “Downlink Path” (Free Space Path Loss, Phase/Frequency Offset), “Ground Station Downlink Receiver” (Receiver Dish Antenna Gain, Ground Receiver System Temperature, Viterbi Decoder), “Error Rate Calculation” block and “Display”. The modelling was realized without and with convolutional coding (r = 3/4, K = 7) at different noise temperatures and free space losses. Dependencies of a Bit Error Rate on free space path losses, antenna's diameter, phase/frequency off-sets, satellite transponder linear gain, aircraft and satellite transponder high power amplifier back-off level, and phase noise were received and analysed.

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5

Kim, Seung-Geun, Chang-Ho Yun, Sea-Moon Kim, and Yong-Kon Lim. "Baseband Receiver Design for Maritime VHF Digital Communications." Journal of Korea Information and Communications Society 36, no. 8B (August 31, 2011): 1012–20. http://dx.doi.org/10.7840/kics.2011.36b.8.1012.

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6

Chen, Hsiao-Yun, Jyun-Nan Lin, Hsiang-Sheng Hu, and Shyh-Jye Jou. "STBC-OFDM Downlink Baseband Receiver for Mobile WMAN." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 1 (January 2013): 43–54. http://dx.doi.org/10.1109/tvlsi.2011.2181965.

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7

Gharaee, Hossein, and Abdolreza Nabavi. "Baseband implementation of OTR-UWB receiver using FPGA." AEU - International Journal of Electronics and Communications 64, no. 3 (March 2010): 258–66. http://dx.doi.org/10.1016/j.aeue.2009.01.001.

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8

MAHMOUD, SOLIMAN A. "A GAIN/FILTERING INTERLEAVED BASEBAND CHAIN ARCHITECTURES FOR MULTISTANDARD RECONFIGURABLE RECEIVERS." Journal of Circuits, Systems and Computers 21, no. 01 (February 2012): 1250008. http://dx.doi.org/10.1142/s0218126612500089.

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In this paper, four baseband chain architectures used in multistandard (UMTS–WLAN) reconfigurable receivers will be introduced, simulated and, compared. The architectures are realized using 0.25 μm CMOS technology operating with 1.2 V supply voltage. The baseband chain consists of three stages: the first and the last stage are programmable gain amplifiers and the intermediate stage is an active Gm-RC LPF filter. The proposed architectures are compared in terms of DC-gain, noise, linearity, SFDR, and power consumption. The best receiver architecture is then derived based on system level analysis and based on a defined figure-of-merit. The best baseband chain bandwidth is controlled by the active Gm-RC filter with a value 2.2 MHz for UMTS and 11 MHz for WLAN. The baseband gain can be programmed in the range of -6÷68 dB, while the input-referred noise density is less 20 nV/√Hz for UMTS and 25 μV/√Hz for WLAN.

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9

Pipino, Alessandra, Marcello De Matteis, Karen Wan, and Andrea Baschirotto. "A Simple Algorithm for Specs Definition in Wireless Receivers." Journal of Circuits, Systems and Computers 26, no. 04 (December 6, 2016): 1750062. http://dx.doi.org/10.1142/s0218126617500621.

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This paper presents a system-level design procedure for wireless receivers, which allows an optimum distribution of the specifications-per-stage along the receiver. The main idea hereby developed is to start from a specific set of requirements (given by the selected telecommunications standards) in terms of bit-error-rate (BER) and blocker mask scenario in frequency domain, and to finally achieve a certain set of specifications for each stage in the receiver chain (i.e., LNA, mixer, baseband and ADC). The proposed system-level design algorithm allows fixing the receiver specifications-per-stage with a reduced set of equations and successive iterations. Moreover, an optimum design for baseband section (i.e., complex filter and the ADC) is also found, by achieving an optimum trade-off between filter order and ADC equivalent-number-of-bits (ENOB). In order to validate the hereby proposed algorithm, a low-energy Bluetooth low-IF receiver has been modeled and simulated (by Simulink), and extensive time-domain simulation results have been provided, complying with the expected Bluetooth standard signal-to-noise-and-distortion ratio (SNDR).

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10

Deng, Jun, Lin Tao Liu, Yu Jing Li, Xiao Zong Huang, Xu Huang, and Lun Cai Liu. "Design of a SoC With High-Speed DDC for Software Radio Receiver." Advanced Materials Research 605-607 (December 2012): 1875–79. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.1875.

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This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications.

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11

Abu Bakar, Faizah, Qaiser Nehal, Pekka Ukkonen, Ville Saari, and Kari Halonen. "Analog baseband chain of synthetic aperture radar (SAR) receiver." Analog Integrated Circuits and Signal Processing 75, no. 1 (October 25, 2012): 41–51. http://dx.doi.org/10.1007/s10470-012-9979-4.

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12

Zervas, N. D., M. Perakis, D. Soudris, E. G. Metaxakis, A. Tzimas, G. A. Kalivas, and C. E. Goutis. "Low-power design of direct conversion baseband DECT receiver." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 48, no. 12 (2001): 1121–31. http://dx.doi.org/10.1109/82.988937.

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13

Liou, M. L., P. H. Lin, C. J. Jan, S. C. Lin, and T. D. Chiueh. "Design of an OFDM baseband receiver with space diversity." IEE Proceedings - Communications 153, no. 6 (2006): 894. http://dx.doi.org/10.1049/ip-com:20050148.

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14

E, SUJATHA, and DR C. SUBHAS. "FPGA Simulation of WCDMA Baseband Receiver Carrier Synchronization Unit." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 3, no. 7 (July 20, 2014): 10914–19. http://dx.doi.org/10.15662/ijareeie.2014.0307044.

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15

Tran, Vinh Tuan, Andrew Graham Dempster, Thuan Dinh Nguyen, and Nagaraj Channarayapatna Shivaramaiah. "A Dynamically Configurable Decimator for a GNSS Baseband Receiver." IEEE Transactions on Aerospace and Electronic Systems 53, no. 1 (February 2017): 296–309. http://dx.doi.org/10.1109/taes.2017.2650298.

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16

Cruz-Roldán, Fernando, Freddy A. Pinto-Benel, José D. Osés del Campo, and Manuel Blanco-Velasco. "A Wavelet OFDM receiver for baseband power line communications." Journal of the Franklin Institute 353, no. 7 (May 2016): 1654–71. http://dx.doi.org/10.1016/j.jfranklin.2016.02.015.

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17

Li, Xiao Wen, Mao Yue Wang, and Dan Wang. "The Research on PRACH Receiver and the DSP Implementation." Applied Mechanics and Materials 543-547 (March 2014): 2518–21. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.2518.

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In LTE system, random access plays an important role in both uplink time adjustment and initial access of UE. This paper analyzes the theory of the related signal detection and the correlation calculation, and proposes a method to detect the received sequence in the receiver. And at last, it presents the implementation on DSP including the baseband signal processing module, Local frequency domain ZC sequence generation module and Correlation calculation module. In a word, it provides a solution for implement the PRACH receiver on hardware.

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18

Bettaieb, Mouna, Ghazi Bouzid, Saif Benali, and Hatem Trabelsi. "Analysis and Optimization of Voltage-Driven Double-Balanced Passive Mixer for MICS Band Receiver." Journal of Circuits, Systems and Computers 28, no. 12 (November 2019): 1950204. http://dx.doi.org/10.1142/s0218126619502049.

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This paper presents analysis of a 25% duty-cycle fully-differential double-balanced passive mixer dedicated to medical implantable devices. The proposed passive mixer is part of a medical implant communication service (MICS) receiver front-end operating at 402–405[Formula: see text]MHz. By performing time-domain analysis, two LTI models have been developed to study the fully-differential double-balanced passive mixer: A simplified model and a complete model taking into account harmonic components. Both models account for the AC coupling capacitors at the mixer input and account for baseband voltage variation over one LO period. In this study it has been shown the ability of mixer input impedance matching by varying baseband resistor at the mixer output. The frequency of match can be controlled by varying the AC coupling capacitors and baseband capacitors. The performance of the proposed models was compared with that of the mixer and the results were very close. In particular, the results of simulations of the input impedance as a function of the baseband resistance and as a function of the IF frequency show the validity of the proposed models. The main parameters of the passive mixer such as input impedance, gain and noise figure (NF) were optimized taking into account the constraints of our application. The proposed mixer is designed to operate at LO frequency of 403.2[Formula: see text]MHz. Transistors size is optimized to meet the receiver specifications. The mixer realizes a conversion gain of 0[Formula: see text]dB and an NF of 4.8[Formula: see text]dB. Linearity simulations show 25.2[Formula: see text]dBm for IIP3 and 9.66[Formula: see text]dBm for [Formula: see text]dB. The mixer consumes 1.44[Formula: see text]pW without LO circuit.

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19

Kulkarni, Raghavendra, Jusung Kim, Hyung-Joon Jeon, Jianhong Xiao, and Jose Silva-Martinez. "UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 2 (February 2012): 197–210. http://dx.doi.org/10.1109/tvlsi.2010.2096438.

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20

Braasch, Michael, and Andrew Dempster. "Tutorial: GPS receiver architectures, front-end and baseband signal processing." IEEE Aerospace and Electronic Systems Magazine 34, no. 2 (February 2019): 20–37. http://dx.doi.org/10.1109/maes.2018.170117.

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21

Betti, S., F. Curti, G. de Marchis, and E. Iannone. "Large deviation fsk baseband receiver using an optical multiport device." Microwave and Optical Technology Letters 2, no. 12 (December 1989): 418–20. http://dx.doi.org/10.1002/mop.4650021205.

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22

Harju, L., and J. Nurmi. "Hardware platform for software-defined WCDMA/OFDM baseband receiver implementation." IET Computers & Digital Techniques 1, no. 5 (2007): 640. http://dx.doi.org/10.1049/iet-cdt:20060013.

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23

Wu, Xiang Yu, Jin Rui Liu, Hang Gong, and Gang Ou. "Software Simulation Method for Digital if GNSS Signal." Advanced Materials Research 756-759 (September 2013): 2655–59. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.2655.

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Data simulation is an important auxiliary method for baseband signal processing algorithm design of digital IF GNSS receiver. Especially when the high sensitivity and high dynamic receivers are developed, or multipath and cross correlation mitigation techniques are considered, exact and complete tests under all kinds of necessary scenes can be carried out with the IF signal data which is generated by software simulation method. With this method, the developing efficiency can be improved and the cost can be cut down. In this paper, precise model of the IF signal is given firstly through analyzing GNSS receivers RF processing flow. Then, considering the discrete characteristic of software processing, the IF signal simulation flow and block of the simulation software are designed. Finally, the specific design process is given through a design example. When the IF signal simulation software is used for testing baseband signal processing algorithms, GNSS receivers IF signal data under every necessary test scene can be generated just by parameter adjustment.

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24

Marcinek, Krzysztof, and Witold A. Pleskacz. "GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing." Sensors 20, no. 2 (January 14, 2020): 465. http://dx.doi.org/10.3390/s20020465.

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This work presents the results of research toward designing an instruction set extension dedicated to Global Navigation Satellite System (GNSS) baseband processing. The paper describes the state-of-the-art techniques of GNSS receiver implementation. Their advantages and disadvantages are discussed. Against this background, a new versatile instruction set extension for GNSS baseband processing is presented. The authors introduce improved mechanisms for instruction set generation focused on multi-channel processing. The analytical approach used by the authors leads to the introduction of a GNSS-instruction set extension (ISE) for GNSS baseband processing. The developed GNSS-ISE is simulated extensively using PC software and field-programmable gate array (FPGA) emulation. Finally, the developed GNSS-ISE is incorporated into the first-in-the-world, according to the authors’ best knowledge, integrated, multi-frequency, and multi-constellation microcontroller with embedded flash memory. Additionally, this microcontroller may serve as an application processor, which is a unique feature. The presented results show the feasibility of implementing the GNSS-ISE into an embedded microprocessor system and its capability of performing baseband processing. The developed GNSS-ISE can be implemented in a wide range of applications including smart IoT (internet of things) devices or remote sensors, fostering the adaptation of multi-frequency and multi-constellation GNSS receivers to the low-cost consumer mass-market.

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25

Guo, Li Shu, Xu You Li, and Xiao Ying Kong. "Analysis on GNSS Receiver with the Principles of Signal and Information." Applied Mechanics and Materials 328 (June 2013): 261–65. http://dx.doi.org/10.4028/www.scientific.net/amm.328.261.

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In the paper, principles of signal and information were introduced to the design of GNSS receiver. Analyze Antenna and radio frequency (RF) front-end with the perspective of transmission link, Understand the baseband processing though signal modulate and demodulate, design the navigation calculation utilized the information pick-up and disposal, and research the receiver system by the inherent connection between signal and information. New ways and means would be developed though these researches.

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26

Telagathoti, Pitchaiah, Moparthi Aparna, and P. V. Sridevi. "Design and FPGA Implementation of Digital Down Converter for LTE-SDR Receiver." International Journal of Engineering & Technology 7, no. 2-1 (March 23, 2018): 421. http://dx.doi.org/10.14419/ijet.v7i2.9242.

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Due to huge demand for high data rate transmission, there is requirement for efficient design of Digital Down Converter (DDC) in wireless communications. DDC is an indispensable part in modern communication, as for higher frequencies it is difficult to down convert the frequency directly to the baseband frequency. Hence a super heterodyne receiver is used to convert the received signal into an intermediate frequency and the intermediate frequency is then converted into the baseband frequency. The architecture of DDC mainly consists of two parts; first one is demodulation and second one is decimation system. The first stage performs the demodulation and the second stage decimation system performs the operation of filtering and decimation. This paper discusses the design and FPGA implementation of DDC for the LTE-SDR receiver for band5 in LTE(UMTS) standards. The design and FPGA implementation of DDC for LTE-SDR is developed and tested using SystemVue software and Xilinx ML507 FPGA board. The results show that simulation results and FPGA implementation results are very close to each other, so the designed DDC can be used in real time LTE SDR application with hardware as FPGA for efficient processing of data with minimum number of resources and at higher operating frequency.

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27

Guo, Benqing, Hongpeng Chen, Xuebing Wang, Lei Li, and Wanting Zhou. "A wideband receiver front-end with low noise and high linearity by exploiting reconfigurable dual paths in 180 nm CMOS." Modern Physics Letters B 35, no. 12 (February 9, 2021): 2150210. http://dx.doi.org/10.1142/s0217984921502109.

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In this paper, a wideband receiver front-end including the flexible reconfigurable main and auxiliary paths is proposed. Therein, the main path has the low-noise advantage thanks to the low-noise transconductance amplifier (LNTA) preceding the mixer and baseband. Meanwhile, by utilizing a mixer-first structure, the auxiliary path renders a high in-band and out-of-band linearity. Furthermore, an inductor resonance structure is also designed to mitigate the baseband noise crosstalk issue which is disclosed by a charging/discharging mechanism via the tail capacitance of passive mixers. Both of the receiving paths have shared a common baseband circuit while loading a commonly-shared 25% duty-cycle LO source generator. Simulation results by a 180 nm CMOS have demonstrated that the main path provides a low noise figure (NF) of 2.7 dB, while the auxiliary path obtains the in-band and out-of-band IIP3 of 9.2 and 21 dBm under typical LO excitation frequency of [Formula: see text] GHz. The power consumption of the main path of the dual-path front-end is 57 mW and that of the auxiliary path is 26 mW under a supply voltage of 1.8 V.

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28

Ding, Wei, Tao Xu, Min Song, and Wei Gu. "Parallel Channel Equalizer for Mobile OFDM Baseband Receivers." Applied Mechanics and Materials 333-335 (July 2013): 640–45. http://dx.doi.org/10.4028/www.scientific.net/amm.333-335.640.

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Mobile OFDM refers to OFDM systems with fast moving transceivers, contrastive to traditional OFDM systems whose transceivers are stationary or with a low velocity. An efficient implementation of the channel equalization for mobile OFDM is presented in this paper. Based on the particular OFDM subcarrier allocations, the channel equalizer is split into separated sub-equalizers, enabling a concurrent implementation. This parallel equalizer is implemented on an FPGA platform. The experimental results show that without an efficient design, mobile OFDM leads to an unacceptable hardware cost. The proposed parallel equalizer for mobile OFDM can compensate for time-varying channels, in which a traditional OFDM receiver fails to operate, although the paid price is that the hardware resource is reasonably increased.

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29

Salmela, Perttu, Juho Antikainen, Teemu Pitkänen, Olli Silvén, and Jarmo Takala. "3G Long Term Evolution Baseband Processing with Application-Specific Processors." International Journal of Digital Multimedia Broadcasting 2009 (2009): 1–13. http://dx.doi.org/10.1155/2009/503130.

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Data rates in the upcoming 3G long term evolution (LTE) standard will be manifold when compared to the current universal mobile telecommunications system. Implementing receivers conforming with the high-capacity transmission techniques is challenging due to the complexity and computational requirements of algorithms. In this study, the software defined radio (SDR) is targeted and the four essential baseband functions of the 3G LTE receiver, namely, list sphere decoding, fast Fourier transform, QR decomposition, and turbo decoding, are addressed and the functions are implemented as application specific processors (ASPs). As a result, the design space that describes the essential computational challenges of 3G LTE receivers is clarified and estimates of area, power, and interprocessor communication buffer requirements are presented.

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30

Duan, Mao Qiang, Xiao Li Huang, and Jian Jun Wang. "The Design and Implement for Transceiver of WIA-PA." Applied Mechanics and Materials 701-702 (December 2014): 1045–48. http://dx.doi.org/10.4028/www.scientific.net/amm.701-702.1045.

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In this paper, the system scheme and system architecture for transceiver of WIA-PA are presented. The low-IF topology and direct up conversion method are employed, corresponding to receiver part and transmitter part. And in the baseband part, differential and correlation demodulate received signals, as well as time sync, frequency offset calibrate and frame sync operations are designed for solvation the problem of real radio environmental effects. The chip implements using 0.18μm CMOS process has small chip area and low power consumption. The minimum sensitivity of receiver is less than-85dBm for 1% PER (packet error rate), which is better than the required sensitivity for specification.

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31

Raju, Kota Solomon. "Digital Multichannel GPS Receiver Baseband Modules using Model Based Design Tools." International Journal of Mobile Network Communications & Telematics 2, no. 4 (August 31, 2012): 9–18. http://dx.doi.org/10.5121/ijmnct.2012.2402.

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32

Tekin, Ahmet, Hassan Elwan, and Kenneth Pedrotti. "A universal low-noise analog receiver baseband in 65-nm CMOS." Analog Integrated Circuits and Signal Processing 65, no. 2 (May 30, 2010): 225–38. http://dx.doi.org/10.1007/s10470-010-9483-7.

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33

Elwan, H., A. Ravindran, and M. Ismail. "CMOS low power baseband chain for a GSM/DECT multistandard receiver." IEE Proceedings - Circuits, Devices and Systems 149, no. 5 (December 1, 2002): 337–47. http://dx.doi.org/10.1049/ip-cds:20020602.

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34

Chia-Sheng Peng and Yuan-Shin Chuang. "CORDIC-based architecture with channel state information for OFDM baseband receiver." IEEE Transactions on Consumer Electronics 51, no. 2 (May 2005): 403–12. http://dx.doi.org/10.1109/tce.2005.1467979.

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35

Zhuang, W., and J. Tranquilla. "Digital baseband processor for the GPS receiver (parts I and II)." IEEE Transactions on Aerospace and Electronic Systems 29, no. 4 (1993): 1343–49. http://dx.doi.org/10.1109/7.259538.

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36

Olopade, A. O., and M. Helaoui. "Performance Analysis of a Six-Port Receiver in a WCDMA Communication System including a Multipath Fading Channel." Journal of Electrical and Computer Engineering 2014 (2014): 1–7. http://dx.doi.org/10.1155/2014/198261.

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Third generation communication systems require receivers with wide bandwidth of operation to support high transmission rates and are also reconfigurable to support various communication standards with different frequency bands. An ideal software defined radio (SDR) will be the absolute answer to this requirement but it is not achievable with the current level of technology. This paper proposes the use of a six-port receiver (SPR) front-end (FE) in a WCDMA communication system. A WCDMA end-to-end physical layer MATLAB demo which includes a multipath channel distortion block is used to determine the viability of the six-port based receiver. The WCDMA signal after passing through a multipath channel is received using a constructed SPR FE. The baseband signal is then calibrated and corrected in MATLAB. The six-port receiver performance is measured in terms of bit error rate (BER). The signal-to-noise ratio (SNR) of the transmittedIQdata is varied and the BER profile of the communication system is plotted. The effect of the multipath fading on the receiver performance and the accuracy of the calibration algorithm are obtained by comparing two different measured BER curves for different calibration techniques to the simulated BER curve of an ideal receiver.

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37

CHEN, ZHIMING, YUANJIN ZHENG, and XIAOJUN YUAN. "CMOS LOW-POWER ANALOGUE BASEBAND CIRCUITS FOR A NON-COHERENT LOW DATA RATE IR-UWB RECEIVER." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 45–55. http://dx.doi.org/10.1142/s0218126611007062.

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A low-power analogue baseband circuit for a low data-rate impulse radio ultra-wideband (IR-UWB) receiver is designed and implemented in a 0.18 μm CMOS technology, including a variable-gain amplifier (VGA), a received signal strength indicator (RSSI), and a limiting amplifier (LA). The VGA has gain range from -9 to 63 dB and bandwidth from 31 to 187 MHz. An input P1dB of -15.4 dBm is achieved at 0 dB gain. The RSSI has a dynamic range of approximately 70 dB. The RSSI linearity error is within ±1.2 dB for an input power from -77.5 dBm to -36.2 dBm. By adjusting the VGA gain and the LA threshold, the LA is able to detect an input pulse as low as 0.6 mV at a data rate of 15 mega-pulse per second (MP/s). The analogue baseband circuit draws current of 6.03 mA from a single voltage supply of 1.8 V. The test chip occupies an area of 970 μm × 750 μm, including two output buffers.

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38

SAPONARA, SERGIO, and BRUNO NERI. "INTEGRATED 60 GHZ ANTENNA, LNA AND FAST ADC ARCHITECTURE FOR EMBEDDED SYSTEMS WITH WIRELESS GBIT CONNECTIVITY." Journal of Circuits, Systems and Computers 21, no. 05 (August 2012): 1250047. http://dx.doi.org/10.1142/s0218126612500478.

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With reference to an architecture for the full integration of a 60 GHz receiver in embedded systems with wireless gigabit connectivity, the paper presents the design of key building blocks such as: on-chip antenna, low noise amplifier (LNA) and a time-interleaved fast A/D converter (ADC) with AMBA AXI interface towards the digital baseband part. With respect to the state of the art the co-design of the on-chip antenna with the LNA, and the fast ADC architecture realized as a time-interleaved array of threshold-configuring SAR channels, represent new solutions optimized in terms of power consumption. Complexity and performance results in a 65-nm CMOS SOI technology, suitable also for digital systems integration, are presented. The performance and complexity results of the designed antenna, LNA and ADC are integrated in a system level simulator with those obtained by adopting known solutions for other receiver blocks (mixer, IF and baseband amplifiers and filters, frequency synthesizer) thus estimating the performance achievable with a whole 60 GHz receiver and digitization sub-system macrocell. The system-level estimated performances confirm the feasibility of a full-integrated receiver supporting short-range High Definition (HD) connectivity of several Gb/s with a Signal-to-Noise-Ratio compliant with WiGig and Wireless HD new standardization initiatives.

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Tran, Vinh T., Nagaraj C. Shivaramaiah, Thuan D. Nguyen, Joon W. Cheong, Eamonn P. Glennon, and Andrew G. Dempster. "Generalised Theory on the Effects of Sampling Frequency on GNSS Code Tracking." Journal of Navigation 71, no. 2 (November 28, 2017): 257–80. http://dx.doi.org/10.1017/s0373463317000741.

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Synchronisation of the received Pseudorandom (PRN) code and its locally generated replica is fundamental when estimating user position in Global Navigation Satellite System (GNSS) receivers. It has been observed through experiments that user position accuracy decreases if sampling frequency is an integer multiple of the nominal code rate. This paper provides an accuracy analysis based on the number of samples and the residual code phase of each code chip. The outcomes reveal that the distribution of residual code phases in the code phase range [0, 1/ns), where ns is the number of samples per code chip, is the root cause of accuracy degradation, rather than the ratio between sampling frequency and nominal code rate. Doppler frequencies, coherent integration periods, front-end filter bandwidths and received Carrier to Noise ratios (C/N0) also influence receiver accuracy. Also provided are a sampling frequency selection guideline and new proposed estimates of the correlation output and the Delay Locked Loop (DLL) tracking error, which can be applied to precisely model GNSS receiver baseband signal processing.

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Keehr, Edward A., and Ali Hajimiri. "Digitally assisted equalization of third-order intermodulation products in wideband direct conversion receivers." International Journal of Microwave and Wireless Technologies 1, no. 4 (June 22, 2009): 377–85. http://dx.doi.org/10.1017/s1759078709990341.

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An effective linearization technique capable of equalizing IM3 products resulting from an arbitrary out-of-band blocking scenario in a wideband direct conversion receiver is presented. IM3 products are regenerated in the RF analog domain of a low-power mixed-signal feedforward path and are used to cancel analogous signal terms in the original receiver at digital baseband via adaptive equalization. The composite SAW-less receiver achieves an improvement in effective IIP3 from −7.1 to +5.3 dBm under worst-case UMTS Region 1 blocking when the feedforward path is active.

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Shi, Hong Mei. "The Design and Implementation of Spread Spectrum Communication System." Advanced Materials Research 933 (May 2014): 693–97. http://dx.doi.org/10.4028/www.scientific.net/amr.933.693.

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The main research content of this article is to design a direct sequence spread spectrum communication system based on software radio technology. In this paper, design of spread spectrum receiver system directly to intermediate frequency sampling signal processing, after internal processing directly output transmission baseband signal information.

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Li, Fang Neng, Jiang Ning Xu, Hou Pu Li, and Wei Wei Yin. "Design for a Dual-System Satellite Navigation Anti-Jamming Receiver." Applied Mechanics and Materials 744-746 (March 2015): 1674–79. http://dx.doi.org/10.4028/www.scientific.net/amm.744-746.1674.

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In order to ensure that a satellite navigation receiver is able to work under the navigation warfare environment, a design for dual system anti-jamming satellite navigation receiver is proposed. Space-time anti-jamming technology is analyzed, which takes linearly constrained minimum variance (LCMV) as the optimal criterion, weighted by power inversion, enhanced anti-jamming capability of the receiver. Digital beam forming technology with a stronger anti-jamming performance is realized by feedback of satellite orientation information from baseband. Simulations show that traditional space-time interference suppression technology can realize 70dB anti-jamming capability for an interference, and by introduction of the beam forming technology, the anti-jamming capability for an interference can achieved 85dB.

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Juang, Jyh-Ching, Chiu-Teng Tsai, and Yu-Hsuan Chen. "Development of a PC-Based Software Receiver for the Reception of Beidou Navigation Satellite Signals." Journal of Navigation 66, no. 5 (June 12, 2013): 701–18. http://dx.doi.org/10.1017/s0373463313000271.

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Beidou is the Global Navigation Satellite System (GNSS) being developed in China, with the aim to provide a global navigation service that is similar to the Global Positioning System (GPS) and Galileo navigation systems. In this paper, it is demonstrated that through the flexibility and re-configurability of a PC-based software receiver in which the baseband operations are realized in terms of software, it is possible to acquire, track, and demodulate Beidou satellite signals even when only a limited amount of information is known. Further, with the Beidou interface control document now available, the proposed PC-based software receiver can be easily adapted to perform navigation functions. This research lays the foundation for the further development of navigation receivers and exploration of multi-GNSS applications.

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OHTA, Tomoya, Satoshi DENNO, and Masahiro MORIKURA. "A Low Complexity Heterodyne Multiband MIMO Receiver with Baseband Automatic Gain Control." IEICE Transactions on Communications E96.B, no. 12 (2013): 3124–34. http://dx.doi.org/10.1587/transcom.e96.b.3124.

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WANG, Sen-Hung, Chih-Peng LI, Chao-Tang YU, Jian-Ming HUANG, and Chua-Chin WANG. "Baseband Receiver Design for the MBOA Ultra Wideband Wireless Personal Area Networks." IEICE Transactions on Communications E92-B, no. 1 (2009): 143–49. http://dx.doi.org/10.1587/transcom.e92.b.143.

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Hsi-Pin Ma, Ming-Luen Liou, and Tzi-Dar Chiueh. "A 123-mW W-CDMA uplink baseband receiver IC with beamforming capability." IEEE Journal of Solid-State Circuits 39, no. 5 (May 2004): 785–94. http://dx.doi.org/10.1109/jssc.2004.826346.

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Abdulaziz, Mohammed, Eric A. M. Klumperink, Bram Nauta, and Henrik Sjoland. "Improving Receiver Close-In Blocker Tolerance by Baseband $G_m-C$ Notch Filtering." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 3 (March 2019): 885–96. http://dx.doi.org/10.1109/tcsi.2018.2872469.

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An, Sining, Zhongxia Simon He, Jingjing Chen, Hangcheng Han, Jianping An, and Herbert Zirath. "A Synchronous Baseband Receiver for High-Data-Rate Millimeter-Wave Communication Systems." IEEE Microwave and Wireless Components Letters 29, no. 6 (June 2019): 412–14. http://dx.doi.org/10.1109/lmwc.2019.2910661.

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Huan-Chang Liu, J. S. Min, and H. Samueli. "A low-power baseband receiver IC for frequency-hopped spread spectrum communications." IEEE Journal of Solid-State Circuits 31, no. 3 (March 1996): 384–94. http://dx.doi.org/10.1109/4.494200.

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An, Sining, Zhongxia Simon He, Jianguo Li, Xiangyuan Bu, and Herbert Zirath. "Coded Pilot Assisted Baseband Receiver for High Data Rate Millimeter-Wave Communications." IEEE Transactions on Microwave Theory and Techniques 68, no. 11 (November 2020): 4719–27. http://dx.doi.org/10.1109/tmtt.2020.2993789.

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