Log in

Relevant bibliographies by topics / Baugh-Wooley / Journal articles

To see the other types of publications on this topic, follow the link: Baugh-Wooley.

Journal articles on the topic 'Baugh-Wooley'

Author: Grafiati

Published: 4 June 2021

Last updated: 18 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 18 journal articles for your research on the topic 'Baugh-Wooley.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Rajmohan, V., and O. Uma Maheswari. "Improved Baugh Wooley Multiplier Using Cadence Register Transfer Level Logic for Power Consumption." Journal of Computational and Theoretical Nanoscience 14, no. 1 (2017): 277–83. http://dx.doi.org/10.1166/jctn.2017.6317.

Full text

Abstract:

In modern days of VLSI design, speedy operations and low-power consumption is a key requirement for any circuits. When it comes to multipliers, the power efficient multiplier plays an important role. The main aim of this work is to develop the system with faster and less power multiplier for an efficient process by using Baugh-Wooley multipliers. The optimized Baugh-Wooley multiplier consumes least power, area and produces less delay. The proposed architecture is 193× times faster than Conventional array multiplier in the practical applications and 213× times faster than a conventional Baugh-Wooley multiplier. The Improved Baugh-Wooley multiplier consumes the power of 09.02 mW and area of 52426 μm2.

APA, Harvard, Vancouver, ISO, and other styles

2

Ramkumar, B., and Harish M. Kittur. "Faster and Energy-Efficient Signed Multipliers." VLSI Design 2013 (June 2, 2013): 1–12. http://dx.doi.org/10.1155/2013/495354.

Full text

Abstract:

We demonstrate faster and energy-efficient column compression multiplication with very small area overheads by using a combination of two techniques: partition of the partial products into two parts for independent parallel column compression and acceleration of the final addition using new hybrid adder structures proposed here. Based on the proposed techniques, 8-b, 16-b, 32-b, and 64-b Wallace (W), Dadda (D), and HPM (H) reduction tree based Baugh-Wooley multipliers are developed and compared with the regular W, D, H based Baugh-Wooley multipliers. The performances of the proposed multipliers are analyzed by evaluating the delay, area, and power, with 65 nm process technologies on interconnect and layout using industry standard design and layout tools. The result analysis shows that the 64-bit proposed multipliers are as much as 29%, 27%, and 21% faster than the regular W, D, H based Baugh-Wooley multipliers, respectively, with a maximum of only 2.4% power overhead. Also, the power-delay products (energy consumption) of the proposed 16-b, 32-b, and 64-b multipliers are significantly lower than those of the regular Baugh-Wooley multiplier. Applicability of the proposed techniques to the Booth-Encoded multipliers is also discussed.

APA, Harvard, Vancouver, ISO, and other styles

3

P, Karuppusamy. "DESIGN AND ANALYSIS OF LOW-POWER, HIGH-SPEED BAUGH WOOLEY MULTIPLIER." December 2019 2019, no. 02 (2019): 60–70. http://dx.doi.org/10.36548/jei.2019.2.001.

Full text

Abstract:

The fundamental operations of the communication are the multiplication and division. The multiplier usually consumes a larger area and power and poses a very high latency. As all the above mentioned characteristics of the multiplier depends on the techniques utilized for the multiplication. It becomes necessary to put into effect a proper multiplier that reduces both the latency and the power consumption. So the paper analysis the performance of the various multipliers and scopes to develop a low power high speed multiplier based on the Baugh Wooley algorithm. The Performance analysis of the Baugh Wooley multiplier and the other existing multipliers is done and was found that the performance of the Baugh Wooley in terms of the latency and the power consumption was convincing compared to the other existing methods.

APA, Harvard, Vancouver, ISO, and other styles

4

Prasada G.S, Sai Venkatramana, G. Seshikala, and S. Niranjana. "Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 13, no. 6 (2020): 864–70. http://dx.doi.org/10.2174/2352096513666200107091932.

Full text

Abstract:

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

APA, Harvard, Vancouver, ISO, and other styles

5

Rajmohan, V., and O. Uma Maheswari. "Design of Compact Baugh-Wooley Multiplier Using Reversible Logic." Circuits and Systems 07, no. 08 (2016): 1522–29. http://dx.doi.org/10.4236/cs.2016.78133.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

B, Maha Lakshmi, and Bhavani M. "Design and Implementation of 16-Bit Baugh-Wooley Multiplier." International Journal of Electronics and Communication Engineering 5, no. 12 (2018): 1–5. http://dx.doi.org/10.14445/23488549/ijece-v5i12p101.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Lan-Da Van and Jin-Hao Tu. "Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers." IEEE Transactions on Computers 58, no. 10 (2009): 1346–55. http://dx.doi.org/10.1109/tc.2009.89.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Patle, Indrayani. "Implementation of Baugh-Wooley Multiplier Based on Soft-Core Processor." IOSR Journal of Engineering 3, no. 10 (2013): 01–07. http://dx.doi.org/10.9790/3021-031030107.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Kiran, Ananda, and Navdeep Prashar. "FPGA Implementation of High Speed Baugh-Wooley Multiplier Using Decomposition Logic." Emerging Trends in Electrical, Electronics & Instrumentation Engineering : An International Journal 2, no. 3 (2015): 1–7. http://dx.doi.org/10.5121/eeiej.2015.2301.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

SIRIPURAPU, SRIDAR, BINDHU HIMA, and P. PAXANI. "130 NM CMOS TECHNOLOGY BASED BAUGH-WOOLEY AND WALLACE-TREE-MULTIPLIER ARCHITECTURES." i-manager's Journal on Circuits and Systems 7, no. 3 (2019): 17. http://dx.doi.org/10.26634/jcir.7.3.16455.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

., Jipsa Antony. "DESIGN AND IMPLEMENTATION OF HIGH SPEED BAUGH WOOLEY AND MODIFIED BOOTH MULTIPLIER USING CADENCE RTL." International Journal of Research in Engineering and Technology 03, no. 08 (2014): 56–63. http://dx.doi.org/10.15623/ijret.2014.0308011.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Rais. "Design and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley Multipliers." American Journal of Engineering and Applied Sciences 3, no. 2 (2010): 307–11. http://dx.doi.org/10.3844/ajeassp.2010.307.311.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Prabhu, B. M., and S. Padma. "Optimization of Partial Products in Low Power Baugh Wooley Multiplier using Modified Shannon Adder Cell for Efficient ALU Design." Asian Journal of Research in Social Sciences and Humanities 7, no. 3 (2017): 1503. http://dx.doi.org/10.5958/2249-7315.2017.00258.1.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Pfänder, O. A., R. Nopper, H. J. Pfleiderer, S. Zhou, and A. Bermak. "Comparison of reconfigurable structures for flexible word-length multiplication." Advances in Radio Science 6 (May 26, 2008): 113–18. http://dx.doi.org/10.5194/ars-6-113-2008.

Full text

Abstract:

Abstract. Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

APA, Harvard, Vancouver, ISO, and other styles

15

Murty, M. N., S. S. Nayak, Binayak Padhy, and S. N. Panda. "Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier." International Journal of Electronics and Electical Engineering, July 2012, 61–67. http://dx.doi.org/10.47893/ijeee.2012.1013.

Full text

Abstract:

Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with small computational time. In this paper, a 4-bit serial - parallel multiplier, which can perform both positive and negative multiplications, is presented. Baugh-Wooley algorithm necessitates complementation of last bit of each partial product except the last partial product in which all but the last bit are complemented. In the proposed algorithm all bits of the last partial product are complemented. This modification results in considerable reduction in hardware compared to Baugh-Wooley multiplier. This multiplier can be used for implementation of discrete orthogonal transforms, which are used in many applications, including image and signal processing. This paper presents a 2D bit-level systolic architecture for a matrixmatrix multiplier. A comparison with similar structures has shown that the proposed structure performs better.

APA, Harvard, Vancouver, ISO, and other styles

16

Gomes, Emmanuel Prince, Ankita Saha, Madhavika Agarwal, and V. S. Kanchana Bhaaskaran. "Baugh Wooley Multiplier Using Carry Save Addition for Enhanced PDP." SSRN Electronic Journal, 2019. http://dx.doi.org/10.2139/ssrn.3356212.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Thota, Thanmai, Nandini Chaganti, Pooja Reddy Nedhunuri, and Jayanthi V. R. Ravindra. "LI-PAMB: Low Complexity Implementation of Power and Area-efficient Modified Baugh Wooley Multiplier Using Exact Computing." International journal of simulation: systems, science & technology, January 30, 2019. http://dx.doi.org/10.5013/ijssst.a.20.06.09.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Gudivada, A. Arunkumar, and Gnanou Florence Sudha. "Design of Baugh–Wooley multiplier in quantum-dot cellular automata using a novel 1-bit full adder with power dissipation analysis." SN Applied Sciences 2, no. 5 (2020). http://dx.doi.org/10.1007/s42452-020-2595-5.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!