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1
Eckhardt, James P. "An investigation of high-performance logic circuitry in BiCMOS." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/15759.
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Varelas, Theodoros Carleton University Dissertation Engineering Electrical. "A monolithic BiCMOS power amplifier for low power digital radio transmitter." Ottawa, 1992.
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3
Subramanian, Viswanathan. "Enabling techniques for Si integrated transceiver circuits." Berlin mbv, 2009. http://d-nb.info/998051705/04.
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Ting, Goodwin. "An integrated BiCMOS driver chip for medium power applications /." Online version of thesis, 1991. http://hdl.handle.net/1850/11291.
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Narayanan, Prakash. "Analytical modeling and simulation of bicmos for VLSI circuits." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/42199.
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Interest in BiCMOS technology has been generated recently due to the potential advantages this technology offers over conventional CMOS which enjoys widespread use in today’s semiconductor industry. However, before BiCMOS can be readily adopted by the VLSI community, an understanding of the design issues and tradeoffs involved when utilizing it, must be achieved. The principal focus of this research is to move towards such an understanding through the means of analytical modeling and circuit simulation using PSPICE [1].
The device chosen for the modeling approach is the basic BiCMOS Inverting Buffer Driver. The model yields equations that characterize output rise and fall transients and quantify the delays incurred therein. At the end of the analysis, we have a composite set of delay equations that are a measure of the total gate delay and reflect the importance of individual device and circuit parameters in determining this delay. Further investigations conducted to determine the influence of device, circuit and process parameters on BiCMOS, indicate that this technology is far more resilient to variations in such parameters than CMOS. At the end of this research, we are able to make a definitive judgement about BiCMOS performance and its superiority over CMOS in the switching speed domain.Master of Science
6
Leite, Bernardo. "Design and modeling of mm-wave integrated transformers in CMOS and BiCMOS technologies." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2011. http://tel.archives-ouvertes.fr/tel-00667744.
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Les systèmes de communication sans fil en fréquences millimétriques ont gagné considérablement en importance au cours des dernières années. Des applications comme les réseaux WLAN et WPAN à 60 GHz, le radar automobile autour de 80 GHz ou l'imagerie à 94 GHz sont apparues, demandant un effort conséquent pour la conception des circuits intégrés émetteurs et récepteurs sur silicium. Dans ce contexte, les transformateurs intégrés sont particulièrement intéressants. Ils peuvent réaliser des fonctions comme l'adaptation d'impédance, la conversion du mode asymétrique au différentiel et la combinaison de puissance. La conception et la modélisation de ce type de transformateur font le sujet de cette thèse. Une étude détaillée des topologies de transformateurs est présentée, concernant le dessin des inductances, leur position relative, leurs dimensions géométriques, le blindage du substrat et l'obtention de rapports importants de transformation. Leur modélisation par des simulations électromagnétiques et par un circuit électrique à éléments discrets est également discutée. Le modèle présente une topologie 2-π et une série d'équations analytiques dépendant de ses caractéristiques technologiques et géométriques pour évaluer tous ses composants. Un très bon accord entre les simulations et les mesures est observé pour des transformateurs en technologies CMOS 65 nm et BiCMOS 130 nm jusqu'à 110 GHz. Finalement, les transformateurs sont appliqués à la conception d'un mélangeur BiCMOS à 77 GHz et un amplificateur de puissance CMOS à 60 GHz.
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Pickles, Neil S. (Neil Stuart) Carleton University Dissertation Engineering Electrical. "Design, modeling, and optimization of ECL interface circuits for BiCMOS integrated systems." Ottawa, 1993.
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8
Severino, Raffaele Roberto. "Design methodology for millimeter wave integrated circuits : application to SiGe BiCMOS LNAs." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14284/document.
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Grace aux récents développements des technologies d’intégration, il est aujourd’hui possible d’envisager la réalisation de circuits et systèmes intégrés sur Silicium fonctionnant à des fréquences auparavant inatteignables. Par conséquence, depuis quelques années, on assiste à la naissance de nouvelles applications en bande millimétrique, comme la communication sans fil à haut-débit à 60GHz, les radars automobiles à 76-77 et 79-82GHz, et l’imagerie millimétrique à 94GHz.Cette thèse vise, en premier lieu, à la définition d’une méthodologie de conception des circuits intégrés en bande millimétrique. Elle est par la suite validée au travers de son application à la conception des amplificateurs faible-bruit en technologie BiCMOS SiGe. Dans ce contexte, une attention particulière a été portée au développement d’une stratégie de conception et de modélisation des inductances localisées. Plusieurs exemples d’amplificateurs faible-bruit ont été réalisés, à un ou deux étages, employant des composants inductifs localisés ou distribués, à 60, 80 et 94 GHz. Tous ces circuits présentent des caractéristiques au niveau de l’état de l’art dans le domaine, ainsi en confirmant l’exactitude de la méthodologie de conception et son efficacité sur toute la planche de fréquence considérée. En outre, la réalisation d’un récepteur intégré pour applications automobiles à 80GHz est aussi décrite comme exemple d’une possible application système, ainsi que la co-intégration d’un amplificateur faible-bruit avec une antenne patch millimétrique intégrée sur SiliciumThe interest towards millimeter waves has rapidly grown up during the last few years, leading to the development of a large number of potential applications in the millimeter wave band, such as WPANs and high data rate wireless communications at 60GHz, short and long range radar at 77-79GHz, and imaging systems at 94GHz.Furthermore, the high frequency performances of silicon active devices (bipolar and CMOS) have dramatically increased featuring both fT and fmax close or even higher than 200GHz. As a consequence, modern silicon technologies can now address the demand of low-cost and high-volume production of systems and circuits operating within the millimeter wave range. Nevertheless, millimeter wave design still requires special techniques and methodologies to overcome a large number of constraints which appear along with the augmentation of the operative frequency.The aim of this thesis is to define a design methodology for integrated circuits operating at millimeter wave and to provide an experimental validation of the methodology, as exhaustive as possible, focusing on the design of low noise amplifiers (LNAs) as a case of study.Several examples of LNAs, operating at 60, 80, and 94 GHz, have been realized. All the tested circuits exhibit performances in the state of art. In particular, a good agreement between measured data and post-layout simulations has been repeatedly observed, demonstrating the exactitude of the proposed design methodology and its reliability over the entire millimeter wave spectrum. A particular attention has been addressed to the implementation of inductors as lumped devices and – in order to evaluate the benefits of the lumped design – two versions of a single-stage 80GHz LNA have been realized using, respectively, distributed transmission lines and lumped inductors. The direct comparison of these circuits has proved that the two design approaches have the same potentialities. As a matter of fact, design based on lumped inductors instead of distributed elements is to be preferred, since it has the valuable advantage of a significant reduction of the circuit dimensions.Finally, the design of an 80GHz front-end and the co-integration of a LNA with an integrated antenna are also considered, opening the way to the implementation a fully integrated receiver
9
Long, John R. (John Robert) Carleton University Dissertation Engineering Electrical. "High frequency integrated circuit design in BICMOS for monolithic timing recovery." Ottawa, 1992.
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10
Hirschman, Karl D. "Process development of an analog/digital mixed-mode BiCMOS system at RIT /." Online version of thesis, 1992. http://hdl.handle.net/1850/11238.
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Howard, Duane Clarence. "Reconfigurable amplifiers and circuit components for built-in-self testing and self-healing in SiGe BiCMOS technology." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51823.
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The design of reconfigurable microwave and millimeter-wave circuit components and on-chip testing circuitry are demonstrated. These components are designed to enable the mitigation of process faults, aging, radiation effects, and other mechanisms that lead to performance degradation in circuits and systems. The presented work is primarily based on SiGe HBTs in BiCMOS technology and harnesses the inherent resilience of SiGe to mechanisms that degrade transistor performance. However, CMOS FETs are also used in limited applications, such as in the design of switches, op-amps, and DACs. Individual circuit blocks and circuit systems are characterized with the aim of evaluating their performance under nominal conditions as well as in the context of extreme environments and other deleterious phenomena.
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Lee, Wai Kit. "Modeling the distributed RC effects of BiCMOS technology at high frequency operations /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20LEE.
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Guidash, R. Michael. "Development of a modular 2-micron BiCMOS process from an existing 2-micron n-well CMOS process /." Online version of thesis, 1991. http://hdl.handle.net/1850/11234.
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Madan, Anuj. "Design and reliability of high dynamic range RF building blocks in SOI CMOS and SiGe BiCMOS technologies." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/45853.
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The objective of the proposed research is to understand the design and reliability of RF front-end building blocks using SOI CMOS and SiGe BiCMOS technologies for high dynamic-range applications. This research leads to a comprehensive understanding of dynamic range in SOI CMOS devices and contributes to knowledge leading to improvement in overall dynamic range and reliability of RF building blocks. While the performance of CMOS transistors has been improving naturally with scaling, this work aims to explore the possibilities of improvement in RF performance and reliability using standard layouts (that don't need process modifications). The total-ionizing dose tolerance of SOI CMOS devices has been understood with extensive measurements. Furthermore, the role of body contacts in SOI technology is understood for dynamic range performance improvement. In this work, CMOS low-noise amplifier design for high linearity WLAN applications and its integration with RF switch on the same chip is presented. The LNA and switches designed provide state-of-the-art performance in silicon based technologies. Further, the work aims to explore applications of SiGe HBT in the context of highly linear and reliable RF building blocks. The RF reliability of SiGe HBT based RF switches is investigated and compared with CMOS counterparts. The inverse-mode operation of SiGe HBT based switches is understood to give considerably higher linearity.
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Giuglea, Alexandru, Guido Belfiore, Mahdi Khafaji, Ronny Henker, and Frank Ellinger. "A 30 Gb/s High-Swing, Open-Collector Modulator Driver in 250 nm SiGe BiCMOS." Institute of Electrical and Electronics Engineers Incorporated (IEEE), 2018. https://tud.qucosa.de/id/qucosa%3A33809.
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This paper presents a modulator driver realized as a breakdown voltage doubler which can provide a high output swing of 7.6 Vpp,diff for load impedances as low as 30 Ω, thus overcoming the limitation imposed by the collector-emitter breakdown voltage. The open-collector design gives an important degree of freedom regarding the modulator load to be driven, while significantly reducing the circuit's power consumption. The driver is capable of running at 30 Gb/s while dissipating 1 W of DC power. Thanks to the inductorless design, the active area occupied by the circuit is only 0.28 mm × 0.23 mm. The driver was realized in a 250 nm SiGe BiCMOS technology.
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Erkens, Holger [Verfasser]. "Analysis and Design of SiGe BiCMOS Integrated Circuits for Commercial Maritime Phased Array Radar Systems / Holger Erkens." München : Verlag Dr. Hut, 2010. http://d-nb.info/1009095250/34.
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Bethel, Ryan H. "Low Voltage BiCMOS Circuit Topologies for the Design of a 19GHz, 1.2V, 4-Bit Accumulator in Silicon-Germanium." Fogler Library, University of Maine, 2007. http://www.library.umaine.edu/theses/pdf/BethelRH2007.pdf.
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Kenyon, Eleazar Walter. "Low-noise circuitry for extreme environment detection systems implemented in SiGe BiCMOS technology." Thesis, Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44873.
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This work evaluates two SiGe BiCMOS technology platforms as candidates for implementing extreme environment capable circuitry, with an emphasis on applications requiring high sensitivity and low noise.
In Chapter 1, applications requiring extreme environment sensing circuitry are briefly reviewed and the motivation for undertaking this study is outlined. A case is then presented for the use of SiGe BiCMOS technology to meet this need, documenting the benefits of operating SiGe HBTs at cryogenic temperatures. Chapter 1 concludes with a brief description of device radiation effects in bipolar and CMOS devices, and a basic overview of noise in semiconductor devices and electronic components.
Chapter 2 further elaborates on a specific application requiring low-noise circuitry capable of operating at cryogenic temperatures and proposes a number of variants of band-gap reference circuits for use in said system. Detailed simulation and theoretical analysis of the proposed circuits are presented and compared with measurements, validating the techniques used in the proposed designs and emphasizing the need for further understanding of device level low-temperature noise phenomena.
Chapter 3 evaluates the feasibility of using a SiGe BiCMOS process, whose response to ionizing radiation was previously uncharacterized, for use in unshielded electronic systems needed for exploration of deep space planets or moons, specifically targeting Europa mission requirements. Measured total ionizing dose (TID) responses for both CMOS and bipolar SiGe devices are presented and compared to similar technologies. The mechanisms responsible for device degradation are outlined, and an explanation of unexpected results is proposed.
Finally, Chapter 4 summarizes the work presented and understanding provided by this thesis, concluding by outlining future research needed to build upon this study and fully realize SiGe based extreme environment capable precision electronic systems.
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Valliarampath, J. T. (Joe). "Improving linearity utilising adaptive predistortion for power amplifiers at mm-wave frequencies." Thesis, University of Pretoria, 2014. http://hdl.handle.net/2263/43266.
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The large unlicensed 3 GHz overlapping bandwidth that is available worldwide at 60 GHz has resulted in renewed interest in 60 GHz technology. This frequency band has made it attractive for short-range gigabit wireless communication. The power amplifier (PA) directly influences the performance and quality of this entire communication chain, as it is one of the final subsystems in the transmitter. Spectral efficient modulation schemes used at 60 GHz pose challenging requirements for the linearity of the PA. To improve the linearity, several external linearisation techniques currently exist, such as feedback, feedforward, envelope elimination and restoration, linear amplification with non-linear components and predistortion.
This thesis is aimed at investigating and characterising the distortion components found in PAs at mm-wave frequencies and evaluating whether an adaptive predistortion (APD) linearisation technique is suitable to reduce these distortion components. After a thorough literature study and mathematical analysis, it was found that the third-order intermodulation distortion (IMD3) components were the most severe distortion components. Predistortion was identified as the most effective linearisation technique in terms of minimising these IMD3 components and was therefore proposed in this research. It does not introduce additional complexity and can easily be integrated with the PA. Furthermore, the approach is stable and has lower power consumption when compared to the aforementioned linearisation techniques. The proposed predistortion technique was developed compositely through this research by making it a function of the PA’s output power that was measured using a power detector. A comparator was used with the detected output power and the reference voltages to control the dynamic bias circuit of the variable gain amplifier. This provided control and flexibility on when to apply the predistortion to the PA and therefore allowing the linearity of the PA to be optimised. Three-stage non-linear and linear PAs were also designed at 60 GHz and implemented to compare the performance of the APD technique and form part of the hypothesis verification process.
The 130 nm silicon-germanium (SiGe) bipolar and complementary metal oxide semiconductor (BiCMOS) technology from IBM was used for the simulation of the entire APD and PA design and for the fabrication of the prototype integrated circuits (ICs). This technology has the advantage of integrating the high performance, low power intensive SiGe heterojunction bipolar transistors (HBTs) with the CMOS technology. The SiGe HBTs have a high cut-off frequency ( > 200 GHz), which is ideal for mm-wave PA applications and the CMOS components were integrated in the control logic of the digital circuitry. The simulations and IC layout were accomplished with Cadence Virtuoso. The implemented IC occupies an area of 1.8 mm by 2.0 mm.
The non-linear PA achieves a of 11.97 dBm and an of -10 dBm. With the APD technique applied, the linearity of the PA is significantly improved with an of -6 dBm and an optimum IMD3 reduction of 10 dB. Based on the findings and results of the applied APD technique, APD reduced intermodulation distortion (especially the IMD3) and is thus suitable to improve the linearity of PAs at mm-wave frequencies. To the knowledge of this author, no APD technique has been applied for PAs at 60 GHz, therefore the contribution of this research will assist future PA designers to characterise and optimise the reduction of the IMD3 components. This will result in improved linear output power from the PA and the use of complex modulation schemes at 60 GHz. ## Die groot ongelisensieerde oorvleuelde bandwydte van 3 GHz wat wêreldwyd by 60 GHz beskikbaar is, het hernude belangstelling in 60 GHz-tegnologie tot gevolg gehad. Hierdie frekwensieband het dit aantreklik gemaak vir kortafstand-gigabis draadlose kommunikasie. Aangesien die drywingsversterker een van die finale subsisteme in die seintoestel is, het dit ’n direkte invloed op die werkverrigting en kwaliteit van die hele kommunikasieketting. Spektraaldoeltreffende modulasieskemas wat by 60 GHz gebruik word, stel uitdagende vereistes vir die lineariteit van die drywingsversterker. Om die lineariteit te verbeter, is daar tans verskeie eksterne linearisasietegnieke beskikbaar, soos terugvoer, vooruitvoer, omhullende eliminasie en -restorasie, lineêre versterking met nie-lineêre komponente en predistorsie.
Hierdie tesis het ten doel om die distorsiekomponente wat by millimetergolffrekwensies in drywingsversterkers gevind word, te ondersoek en te karakteriseer en om te bepaal of ’n aanpassende predistorsielinearisasietegniek geskik is om hierdie distorsiekomponente te verminder. Na ’n deeglike literatuurstudie en wiskundige analise is gevind dat die derde-orde-intermodulasiedistorsiekomponente (IMD3) die ergste distorsiekomponente was. Predistorsie is geïdentifiseer as die mees effektiewe linearisasietegniek om hierdie IMD3-komponente te minimeer en die gebruik daarvan is gevolglik in hierdie navorsing voorgestel. Dit bring nie addisionele kompleksiteit mee nie en kan maklik met die drywingsversterker geïntegreer word. Daarbenewens is die benadering stabiel, met laer kragverbruik in vergelyking met die linearisasietegnieke wat voorheen genoem is. Die voorgestelde predistorsietegniek is in hierdie navorsing ontwikkel deur dit ’n funksie van die drywingsversterker se uitsetkrag te maak, wat gemeet is deur ’n kragdetektor te gebruik. ’n Vergelyker is saam met die gemete uitsetkrag en die verwysingspannings gebruik om die dinamiese voorspanningsbaan van die veranderlike winsversterker te beheer. Dit het toegelaat vir beheer en buigsaamheid in die aanwending van die predistorsie op die drywingsversterker en gevolglik vir die optimering van die lineêriteit van die drywingsversterker. Driefase- nie-lineêre en lineêre drywingsversterkers is ook by 60 GHz ontwerp en geïmplementeer om die werkverrigting van die aanpassende predistorsietegniek te vergelyk en dit vorm deel van die verifikasieproses van die hipotese.
Die 130 nm-silikon-germanium (SiGe) bipolêre en metaaloksiedhalfgeleier- (BiCMOS) tegnologie van IBM is gebruik vir die simulasie van die hele aanpassende predistorsietegniek- en drywingsversterkerontwerp en vir die vervaardiging van die prototipe- geïntegreerde stroombane. Hierdie tegnologie het die voordeel dat dit die hoë werkverrigting en lae krag-intensiewe SiGe-heterovoegvlak-bipolêre transistors (HBTs) met die CMOS-tegnologie integreer. Die SiGe-HBTs het ’n hoë afsnyfrekwensie ( > 200 GHz), wat ideaal is vir mm-golfdrywingsversterkeraanwendings en die CMOS-komponente is in die beheer-logika van die digitale stroombaan geïntegreer. Die geïntegreerde stroombaan beslaan ’n area van 1.8 mm by 2.0 mm.
Die nie-lineêre drywingsversterker behaal ’n van 11.97 dBm en ’n van -10 dBm. As die APD-tegniek toegepas word, word die lineariteit van die drywingsversterker beduidend verbeter tot ’n van -6 dBm en ’n optimum-IMD3-vermindering van 10 dB. Volgens die bevindings en resultate van die APD-tegniek wat toegepas is, verminder APD intermodulasiedistorsie (veral die IMD3) en is gevolglik geskik om die lineariteit van drywingsversterkers by mm-golffrekwensies te verbeter. Na die wete van hierdie skrywer is daar nie voorheen enige APD tegniek toegepas vir drywingsversterkers by 60 GHz nie, gevolglik sal die bydrae van hierdie navorsing toekomstige drywingsversterkerontwerpers help om die vermindering van die IMD3-komponente te karakteriseer en optimeer. Dit sal verbeterde lineêre uitsetkrag van die drywingsversterker tot gevolg hê, asook meer komplekse modulasieskemas by 60 GHz toelaat.Thesis (PhD)--University of Pretoria, 2014.
lk2014
Electrical, Electronic and Computer Engineering
PhD
unrestricted
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Larsen, Frode. "Bipolar device characterization and design in CMOS technologies for the design of high-performance low-cost BiCMOS analog integrated circuits /." The Ohio State University, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487857546387163.
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Liu, Haitao. "Novel 3-D CMOS and BiCMOS devices for high-density and high-speed ICs /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20LIU.
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Vieira, Rito Pedro Filipe [Verfasser], Dietmar [Akademischer Betreuer] Kissinger, Dietmar [Gutachter] Kissinger, Ahmet Cagri [Gutachter] Ulusoy, and Friedel [Gutachter] Gerfers. "SiGe BiCMOS integrated circuits for optical communication transmitters / Pedro Filipe Vieira Rito ; Gutachter: Dietmar Kissinger, Ahmet Cagri Ulusoy, Friedel Gerfers ; Betreuer: Dietmar Kissinger." Berlin : Technische Universität Berlin, 2019. http://d-nb.info/1197124799/34.
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Wu, Qiyang. "Analysis and Design of Wide Tuning Range Low Phase Noise mm-wave LC-VCOs." The Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1357243308.
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Wipf, Christian [Verfasser], Dietmar [Akademischer Betreuer] Kissinger, Dietmar [Gutachter] Kissinger, Friedel [Gutachter] Gerfers, and Peter [Gutachter] Weger. "Fully integrated BiCMOS high-voltage driver circuits for on-chip RF-MEMS switch matrices / Christian Wipf ; Gutachter: Dietmar Kissinger, Friedel Gerfers, Peter Weger ; Betreuer: Dietmar Kissinger." Berlin : Technische Universität Berlin, 2019. http://d-nb.info/1202071422/34.
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Mathieu, Brandon Lee. "Capacitively-Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver." The Ohio State University, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=osu1543502773721236.
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Lauterbach, Adam Peter. "Low-cost SiGe circuits for frequency synthesis in millimeter-wave devices." Australia : Macquarie University, 2010. http://hdl.handle.net/1959.14/76626.
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"2009"Thesis (MSc (Hons))--Macquarie University, Faculty of Science, Dept. of Physics and Engineering, 2010.
Bibliography: p. 163-166.
Introduction -- Design theory and process technology -- 15GHz oscillator implementations -- 24GHz oscillator implementation -- Frequency prescaler implementation -- MMIC fabrication and measurement -- Conclusion.
Advances in Silicon Germanium (SiGe) Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technology has caused a recent revolution in low-cost Monolithic Microwave Integrated Circuit (MMIC) design. -- This thesis presents the design, fabrication and measurement of four MMICs for frequency synthesis, manufactured in a commercially available IBM 0.18μm SiGe BiCMOS technology with ft = 60GHz. The high speed and low-cost features of SiGe Heterojunction Bipolar Transistors (HBTs) were exploited to successfully develop two single-ended injection-lockable 15GHz Voltage Controlled Oscillators (VCOs) for application in an active Ka-Band antenna beam-forming network, and a 24GHz differential cross-coupled VCO and 1/6 synchronous static frequency prescaler for emerging Ultra Wideband (UWB) automotive Short Range Radar (SRR) applications. -- On-wafer measurement techniques were used to precisely characterise the performance of each circuit and compare against expected simulation results and state-of-the-art performance reported in the literature. -- The original contributions of this thesis include the application of negative resistance theory to single-ended and differential SiGe VCO design at 15-24GHz, consideration of manufacturing process variation on 24GHz VCO and prescaler performance, implementation of a fully static multi-stage synchronous divider topology at 24GHz and the use of differential on-wafer measurement techniques. -- Finally, this thesis has llustrated the excellent practicability of SiGe BiCMOS technology in the engineering of high performance, low-cost MMICs for frequency synthesis in millimeterwave (mm-wave) devices.
Mode of access: World Wide Web.
xxii, 166 p. : ill (some col.)
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Cardoso, Adilson S. "Design of high-isolation and wideband RF switches in SiGe BiCMOS technology for radar applications." Thesis, Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/43694.
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RF switches are an essential building block in numerous applications, including tactical radar systems, satellite communications, global positioning systems (GPS), automotive radars, wireless communications, radio astronomy, radar transceivers, and various instrumentation systems. For many of these applications the circuits have to operate reliably under extreme operating conditions, including conditions outside the domain of commercial military specifications. The objective of this thesis is to present the design procedure, simulation, and measurement results for Radio Frequency (RF) switches in 130 nm Silicon Germanium (SiGe) BiCMOS process technology. The novelty of this work lies in the proposed new topology of an ultrahigh-isolation single-pole, single-throw (SPST) and a single pole, four-throw (SP4T) nMOS based switch for multiband microwave radar systems. The analysis of cryogenic temperature effects on these circuits and devices are discussed in this work. The results shows that several key-figures-of-merits of a switch, like insertion loss, isolation, and power handling capability (P1dB) improve at cryogenic temperatures. These results are important for several applications, including space-based extreme environment application where FET based circuits would need to operate reliably across a wide-range of temperature.
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Giuglea, Alexandru, Guido Belfiore, Mahdi Khafaji, Ronny Henker, Despoina Petousi, Georg Winzer, Lars Zimmermann, and Frank Ellinger. "Comparison of Segmented and Traveling-Wave Electro-Optical Transmitters Based on Silicon Photonics Mach-Zehnder Modulators." Institute of Electrical and Electronics Engineers (IEEE), 2018. https://tud.qucosa.de/id/qucosa%3A35393.
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This paper presents a brief study of the two most commonly used topologies - segmented and traveling-wave - for realizing monolithically integrated electro-optical transmitters consisting of Si-photonics Mach-Zehnder modulators and their electrical drivers. To this end, two new transmitters employing high swing breakdown voltage doubler drivers were designed in the aforementioned topologies and compared with regard to their extinction ratio and DC power consumption at the data rate of 30 Gb/s. It is shown that for the targeted data rate and extinction ratio, a considerably lower power consumption can be achieved with the traveling-wave topology than with its segmented counterpart. The transmitters were realized in a 250 nm SiGe BiCMOS electronic-photonic integrated technology.
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Moon, Sung Tae. "Design of high performance frequency synthesizers in communication systems." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2329.
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Frequency synthesizer is a key building block of fully-integrated wireless communication
systems. Design of a frequency synthesizer requires the understanding of
not only the circuit-level but also of the transceiver system-level considerations. This
dissertation presents a full cycle of the synthesizer design procedure starting from the
interpretation of standards to the testing and measurement results.
A new methodology of interpreting communication standards into low level circuit
specifications is developed to clarify how the requirements are calculated. A
detailed procedure to determine important design variables is presented incorporating
the fundamental theory and non-ideal effects such as phase noise and reference
spurs. The design procedure can be easily adopted for different applications.
A BiCMOS frequency synthesizer compliant for both wireless local area network
(WLAN) 802.11a and 802.11b standards is presented as a design example. The two
standards are carefully studied according to the proposed standard interpretation
method. In order to satisfy stringent requirements due to the multi-standard architecture,
an improved adaptive dual-loop phase-locked loop (PLL) architecture is
proposed. The proposed improvements include a new loop filter topology with an
active capacitance multiplier and a tunable dead zone circuit. These improvements
are crucial for monolithic integration of the synthesizer with no off-chip components.
The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time
performance while making it more suitable for monolithic integration. It opens a
new possibility of using an integer-N architecture for various other communication
standards, while maintaining the benefit of the integer-N architecture; an optimal
performance in area and power consumption.
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Opperman, Tjaart Adriaan Kruger. "A 5 GHz BiCMOS I/Q VCO with 360° variable phase outputs using the vector sum method." Diss., Pretoria : [s.n.], 2009. http://upetd.up.ac.za/thesis/available/etd-04082009-171225/.
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Thesis (M.Eng.(Microelectronic Engineering))--University of Pretoria, 2009.Includes summaries in Afrikaans and English. Includes bibliographical references (leaves [74]-78). Mode of access: World Wide Web.
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Aouimeur, Walid. "Systèmes de mesure intégré sub-millimétrique en bande G (140-220 GHz) en technologie BiCMOS 55 nm." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT046.
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Les applications microélectroniques telles que les communications sans fil ou les radars nécessitent des traitements d’information avec des débits ou des résolutions de plus en plus élevés. Cela implique de travailler à des fréquences millimétriques voir sub-millimétriques. Grâce aux progrès des technologies silicium, des circuits intégrés travaillant dans les gammes de fréquences millimétriques émergent mais souffrent d'un manque de solution de caractérisation complète. Par exemple, il n’existe à ce jour aucun analyseur vectoriel de réseaux commercial qui soit capable de mesurer les paramètres S dans la bande G (140-220 GHz) en 4 ports. La caractérisation classique des circuits millimétriques en n ports (avec n>2) consiste alors à utiliser un analyseur vectoriel de réseaux 2 ports et à adapter les autres ports non utilisés à 50Ω. Par permutation circulaire, on arrive ainsi à extraire la matrice S d’un dispositif à n ports (avec n>2). Ce protocole de mesure est très long et délicat à mettre en place car il nécessite d’une part un investissement en appareil de mesure très couteux aux fréquences millimétriques et d’autre part de mettre en œuvre des méthodes de calibrage et de de-embedding précises et dédiées.Le travail développé dans le cadre de cette thèse a visé à intégrer dans la puce, des systèmes de caractérisation petits signaux (paramètres S) au plus près du Dispositif Sous Test (DST). Le fait d’être au plus près du DST permet de réduire les pertes d’insertion, de réduire l’amplitude des vecteurs d’erreurs et donc les erreurs résiduelles après calibrage. Par ailleurs, il est possible de mieux contrôler la puissance du signal envoyé et de considérer des méthodes de calibrage utilisant des charges intégrées, ce qui permet de réduire le temps de traitement et le cout. La technologie utilisée est la technologie SiGe BiCMOS 55 nm développée par la société STMicroelectronics, technologie particulièrement adaptée aux circuits en bande millimétrique. La solution développée dans cette thèse consiste à connecter le wafer avec des pointes de mesure qui amènent un signal hyperfréquence balayant le spectre 35-55 GHz. Une fois dans la puce, ce signal hyperfréquence est quadruplé en fréquence et amplifié afin d’atteindre des niveaux de puissance suffisant (bon rapport Signal/bruit) dans la bande G aux bornes du DST. Les paramètres de réflexion (S11 et S22) sont ensuite extraits grâce à deux coupleurs très directifs, placés sur l’entrée et la sortie du DST respectivement. Les sorties du coupleur sont ensuite ramenées en basse fréquence (0.5GHz < IF < 2.4 GHz) par l’intermédiaire de mélangeurs de fréquence.L’approche choisie est argumentée en se basant sur une étude des systèmes de mesures existant présentée dans la première partie de ce manuscrit. Puis la conception et la caractérisation de chacun des blocs composant le système sont détaillées : le quadrupleur de fréquence en bande G (constitué d’un doubleur de fréquence en bande W cascadé avec un doubleur de fréquence en bande G), le transfert switch en bande G permettant de commuter entre l’entrée et la sortie du DST, le coupleur directif à ondes lentes, les mélangeurs permettant de ramener les mesures en basse fréquence, etc…. Une fois tous les différents blocs présentés, le manuscrit aborde les deux systèmes de mesure conçus. Un premier système un port a été développé pour valider cette approche. Le second système conçu permet de mesurer un DST à deux ports (HBT). Ce second système conserve l’architecture hétérodyne du premier, intégrant en plus un transfert switch en bande G qui dirige le signal incident vers l’un des deux ports du DSTMicroelectronic applications such as wireless communications, radar or space detections require higher data rate resolutions, implying the use of millimeter wave and submillimeter frequencies. Thanks to the silicon technologies improvement, some microelectronic circuits are emerging working in the frequency range of 140-220 GHz (G-band) but they suffer from a lack of complete characterization tools involving costly investment. For example, there is currently no commercial vectorial network analyser (VNA) that can measure S parameters in the 4-ports G-band. The classical characterization of millimeter wave circuits in n ports (with n> 2) consists in using a vectorial analyzer of 2-ports networks and matching the other unused ports to 50Ω. By circular permutation, one thus manages to extract the S matrix from a device with n ports (with n> 2). This set up induces very long and difficult measurements and it requires on the one hand some very expensive measuring equipment at millimeter frequencies and on the other hand to implement accurate and dedicated calibration and de-embedding methods.Therefore, the work developed into this PhD study aimed to integrate in the die the measurement systems that would measure small signals "S-parameters" of the device under test (DUT). Being closer to the DST makes it possible to reduce the insertion losses, to reduce the amplitude of the error vectors and thus the residual errors after calibration. Moreover, it is possible to better control the power of the signal sent and to consider calibration methods using integrated loads, which reduces the time and cost processing. The technology used is the SiGe BiCMOS 55 nm technology developed by STMicroelectronics, a technology dedicated to RF and millimeter wave’s circuits.The system developed is a 1-port system. The solution developed consists on connecting the wafer with some probes and driving it with an external signal that spans the 35-55 GHz band. Once into the die, this signal is then quadrupled in frequency and amplified to reach good power level in G band at the DUT inputs. Some S-parameters (S11 and S22) are extracted from the DUT thanks to some very directive couplers designed respectively at the input and at the output of the DUT. The outputs of the couplers are then converted to low frequencies (IF =0.5-2.4 GHz) through passive frequency mixers.In a first part of the thesis manuscript, the way to work is argued, supported by a study of the state of the art concerning the measurement systems. Then, design and characterization of each blocks of the system are detailed: the frequency quadrupler in G band (composed of a W band frequency doubler, followed with a G band frequency doubler), the fully integrated transfer switch in G-band allowing driving the millimeter waves signal to the DUT input or to the DUT output, the directive couplers based on the slow wave lines, the frequency mixers used to bring back the results in base band frequency, etc… All the different blocks detailed, the measurement systems can be introduced. A first system, a one-port measurement system, has been designed as a proof of concept. Once the approach validated, a second system, two-ports measurement system, has been developed presenting an heterodyne architecture and a transfer switch in G band driving the input signal toward the DUT input or output
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El, Agroudy Naglaa, Mohammed El-Shennawy, Niko Joram, and Frank Ellinger. "Design of a 24 GHz FMCW radar system based on sub-harmonic generation." The Institution of Engineering and Technology (IET), 2018. https://tud.qucosa.de/id/qucosa%3A33989.
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This study presents a novel frequency modulated continuous wave (FMCW) radar system based on sub-harmonic generation, where a 24 GHz frequency divider-by-10 is used as an active reflector tag. A practical prototype is designed and fabricated on a GF45nm-Silicon on Insulator (SOI) technology for the 24 GHz building blocks, while a GF0.18 μm 7WL Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technology was used for the 2.4 GHz receiver and baseband. System measurement results show that as opposed to conventional primary radars, the proposed system is immune to strong multi-path interferences resulting from direct reflections of the interrogating signal. The system achieves a ranging precision of 3.7 mm with loop measurements. Moreover, when measured in an indoor environment, the ranging results show a ranging precision and accuracy of 5.8 and 22.3 cm, respectively, which outperform other FMCW radars in the literature.
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Bosley, Ryan Travis. "A VHF/UHF Voltage Controlled Oscillator in 0.5um BiCMOS." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/31452.
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The dramatic increase in market demand for wireless products has inspired a trend for new designs. These designs are smaller, less expensive, and consume less power. A natural result of this trend has been the push for components that are more highly integrated and take up less real estate on the printed circuit board (PCB). Major efforts are underway to reduce the number of integrated circuits (ICs) in newer designs by incorporating several functions into a single chip. Availability of newer technologies such as silicon bipolar with complementary metal oxide semiconductor (BiCMOS) has helped facilitate this move toward more complex circuit topologies onto one die. BiCMOS achieves efficient chip area utilization by combining bipolar transistors, suited for higher frequency analog circuits with CMOS transistors that are useful for digital functions and lower frequency analog circuits. A voltage controlled oscillator (VCO) is just one radio frequency (RF) circuit block that can benefit from a more complex semiconductor process like BiCMOS.
This thesis presents the design and evaluation of an integrated VCO in the IBM 5S BiCMOS process. IBM 5S is a 0.5 um, single poly, five-metal process with surface channel PFETs and NFETs. The process also features self-aligned extrinsic base NPN bipolar devices exhibiting ft of up to 24 GHz.
The objective of this work is to obtain a VCO design that provides a high degree of functionality while maximizing performance over environmental conditions. It is shown that an external feedback and resonator network as well as a bandgap voltage referenced bias circuit help to achieve these goals. An additional objective for this work is to highlight several pragmatic issues associated with designing an integrated VCO capable of high volume production.
The Clapp variant of the Colpitts topology is selected for this application for reasons of robust operation, frequency stability, and ease of implementing in integrated form. Design is performed at 560 MHz using the negative resistance concept. Simulation results from Pspice and the Agilent ADS are presented. Implementation related issues such as bondwire inductances and layout details are covered. The VCO characterization is shown over several environmental conditions. The final nominal design is capable of: tuning over 150 MHz (22%) and delivering â 4.2 dBm into a 50 Ohm load while consuming only 9mA from a 3.0V supply. The phase noise at these conditions is
-92.5 dBc/Hz at a frequency offset of 10 kHz from the carrier. Finally, the conclusion of this work lists some suggestions for potential future research.Master of Science
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Torres, Erick Omar. "An electrostatic CMOS/BiCMOS Li ion vibration-based harvester-charger IC." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/34823.
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The primary objective of this research was to investigate and develop an electrostatic energy-harvesting voltage-constrained CMOS/BiCMOS integrated circuit (IC) that harnesses ambient kinetic energy from vibrations with a vibration-sensitive variable capacitor and channels the extracted energy to charge an energy-storage device (e.g., battery). The proposed harvester charges and holds the voltage across the vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). To that end, the research developed an energy-harvesting system that synchronizes to variable capacitor's state as it cycles between maximum and minimum capacitance by controlling each functional phase of the harvester and adjusting to different voltages of the on-board battery. One of the major challenges of the system was performing all of these duties without dissipating the energy harnessed and gained from the environment. Consequently, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during each vibration cycle.
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Svitek, Richard M. "SiGe BiCMOS RF ICs and Components for High Speed Wireless Data Networks." Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/27375.
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The advent of high-fT silicon CMOS/BiCMOS technologies has led to a dramatic upsurge in the research and development of radio and microwave frequency integrated circuits (ICs) in silicon. The integration of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) into established "digital" CMOS processes has provided analog performance in silicon that is not only competitive with III-V compound-semiconductor technologies, but is also potentially lower in cost. Combined with improvements in silicon on-chip passives, such as high-Q metal-insulator-metal (MIM) capacitors and monolithic spiral inductors, these advanced RF CMOS and SiGe BiCMOS technologies have enabled complete silicon-based RF integrated circuit (RFIC) solutions for emerging wireless communication standards; indeed, both the analog and digital functionalities of an entire wireless system can now be combined in a single IC, also known as a wireless "system-on-a-chip" (SoC). This approach offers a number of potential benefits over multi-chip solutions, such as reductions of parasitics, size, power consumption, and bill-of-materials; however, a number of critical challenges must be considered in the integration of such SoC solutions.
The focus of this research is the application of SiGe BiCMOS technology to on-going challenges in the development of receiver components for high speed wireless data networks. The research seeks to drive SoC integration by investigating circuit topologies that eliminate the need for off-chip components and are amenable to complete on-chip integration. The first part of this dissertation presents the design, fabrication, and measurement of a 5--6GHz sub-harmonic direct-conversion-receiver (DCR) front-end, implemented in the IBM 0.5um 5HP SiGe BiCMOS process. The design consists of a fully-differential low-noise amplifier (LNA), a set of quadrature (I and Q)x~2 sub-harmonic mixers, and an LO conditioning chain. The front-end design provides a means to address performance limitations of the DCR architecture (such as DC-offsets, second-order distortion, and quadrature phase and amplitude imbalances) while enabling the investigation of high-frequency IC design complications, such as package parasitics and limited on-chip isolation. The receiver front-end has a measured conversion gain of ~18dB, an input second-order intercept point of +17.5dBm, and a noise figure of 7.2dB. The quadrature phase balance at the sub-harmonic mixer IF outputs was measured in the presence of digital switching noise; 90Ph. D.
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Janse, van Rensburg Christo. "A SiGe BiCMOS LNA for mm-wave applications." Diss., University of Pretoria, 2012. http://hdl.handle.net/2263/26501.
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A 5 GHz continuous unlicensed bandwidth is available at millimeter-wave (mm-wave) frequencies around 60 GHz and offers the prospect for multi gigabit wireless applications. The inherent atmospheric attenuation at 60 GHz due to oxygen absorption makes the frequency range ideal for short distance communication networks. For these mm-wave wireless networks, the low noise amplifier (LNA) is a critical subsystem determining the receiver performance i.e., the noise figure (NF) and receiver sensitivity. It however proves challenging to realise high performance mm-wave LNAs in a silicon (Si) complementary metal-oxide semiconductor (CMOS) technology. The mm-wave passive devices, specifically on-chip inductors, experience high propagation loss due to the conductivity of the Si substrate at mm-wave frequencies, degrading the performance of the LNA and subsequently the performance of the receiver architecture. The research is aimed at realising a high performance mm-wave LNA in a Si BiCMOS technology. The focal points are firstly, the fundamental understanding of the various forms of losses passive inductors experience and the techniques to address these issues, and secondly, whether the performance of mm-wave passive inductors can be improved by means of geometry optimising. An associated hypothesis is formulated, where the research outcome results in a preferred passive inductor and formulates an optimised passive inductor for mm-wave applications. The performance of the mm-wave inductor is evaluated using the quality factor (Q-factor) as a figure of merit. An increased inductor Q-factor translates to improved LNA input and output matching performance and contributes to the lowering of the LNA NF. The passive inductors are designed and simulated in a 2.5D electromagnetic (EM) simulator. The electrical characteristics of the passive structures are exported to a SPICE netlist which is included in a circuit simulator to evaluate and investigate the LNA performance. Two LNAs are designed and prototyped using the 13μ-m SiGe BiCMOS process from IBM as part of the experimental process to validate the hypothesis. One LNA implements the preferred inductor structures as a benchmark, while the second LNA, identical to the first, replaces one inductor with the optimised inductor. Experimental verification allows complete characterization of the passive inductors and the performance of the LNAs to prove the hypothesis. According to the author's knowledge, the slow-wave coplanar waveguide (S-CPW) achieves a higher Q-factor than microstrip and coplanar waveguide (CPW) transmission lines at mm-wave frequencies implemented for the 130 nm SiGe BiCMOS technology node. In literature, specific S-CPW transmission line geometry parameters have previously been investigated, but this work optimises the signal-to-ground spacing of the S-CPW transmission lines without changing the characteristic impedance of the lines. Optimising the S-CPW transmission line for 60 GHz increases the Q-factor from 38 to 50 in simulation, a 32 % improvement, and from 8 to 10 in measurements. Furthermore, replacing only one inductor in the output matching network of the LNA with the higher Q-factor inductor, improves the input and output matching performance of the LNA, resulting in a 5 dB input and output reflection coefficient improvement. Although a 5 dB improvement in matching performance is obtained, the resultant noise and gain performance show no significant improvement. The single stage LNAs achieve a simulated gain and NF of 13 dB and 5.3 dB respectively, and dissipate 6 mW from the 1.5 V supply. The LNA focused to attain high gain and a low NF, trading off linearity and as a result obtained poor 1 dB compression of -21.7 dBm. The LNA results are not state of the art but are comparable to SiGe BiCMOS LNAs presented in literature, achieving similar gain, NF and power dissipation figures.Dissertation (MEng)--University of Pretoria, 2012.
Electrical, Electronic and Computer Engineering
unrestricted
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Germain, Yves phaede. "Méthode de conception des systèmes différentiels RF utilisant le formalisme des Modes Mixtes." Thesis, Limoges, 2015. http://www.theses.fr/2015LIMO0010/document.
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Ces travaux de recherche visent à introduire et à généraliser l'utilisation des systèmes différentiels dans les applications RF et Micro-ondes. En particulier, dans la conception de dispositifs pour les fonctions d'amplification à faible bruit. Pour cela, il est indispensable de développer des outils fiables et rigoureux tels que le formalisme des modes mixtes introduit par Bockelman. C'est dans cet esprit que s'inscrit la première phase de l'étude. Le but étant de développer un outil pour l'analyse de la stabilité linéaire des systèmes différentiels à trois et quatre accès. Par ailleurs, les interfaces des circuits numériques ultra-rapides (CNA) sont de topologie différentielle. Ce qui augmente encore l'intérêt de disposer de méthodes rigoureuses pour la conception des systèmes différentiels. Dans la deuxième phase de l'étude la problématique de l'intégration système des CNAs dans les nouvelles générations des chaines de transmission RF des satellites de télécommunications est traitée. La conception d'un balun actif large bande capable d'assurer la conversion de la sortie analogique différentielle du CNA en sortie simple accès (Single-ended) référencée par rapport à la masse est détaillée. Afin de répondre aux contraintes d'intégration, une technologie BiCMOS SiGe 0.25 μm est utilisée pour son implémentation. Les performances obtenues par la mesure de la puce Silicium réalisée respectent les spécifications techniques initiales de l'application. Ce qui permet de valider la méthodologie de conception utilisée. L'objectif final est d'être capable d'intégrer sur un même substrat monolithique le CNA et le balun actif large bande de conversion de modesThis research work aims to develop analytical tools for the analysis and design of differential systems. While the use of differential circuits in RF reception/transmission chains is increasingly growing, there is no accurate method to study their stability. First the common tools to study RF differential components are introduced. Then, the development of a CAD tool that can be rigorously used to investigate the extrinsic stability of linear differential systems is presented. Finally this tool is applied to study the stability of in a real case. The design addresses a three port component that aims to convert the differential output of digital to analog converter into a single-ended access for a spatial application purpose. This broadband active balun is designed using BiCMOS technology. Measurements are performed and the results are in good agreement with the simulation. All the initial specications are achieved, which validate the approach developed in this study
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Carbonero, Jean-Louis. "Développement des méthodes de mesures en hyperfréquences sur tranches de silicium et application à la caractérisation des technologies CMOS et BICMOS sub-microniques." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0051.
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La reduction spectaculaire des dimensions des transistors bipolaires et mosfet en technologies cmos et bicmos s'est accompagnee d'une croissance des densites d'integration et surtout d'une augmentation tout aussi spectaculaire des performances de ces transistors. Des frequences de transition de 20 ghz sont aujourd'hui atteintes pour des technologies silicium sub-microniques en phase industrielle. Ces technologies sont appelees a jouer un role important pour la realisation de circuits integres radiofrequences et hyperfrequences. En raison des performances dynamiques toujours plus grandes de ces transistors, les mesures de parametres s et du facteur de bruit, dans le domaine des hyperfrequences ont ete introduites pour le developpement de ces nouvelles technologies et la construction des modeles de dispositifs passifs et actifs, indispensables a la conception des circuits integres analogiques hyperfrequences. Les methodes de mesures hyperfrequences, realisees a l'aide d'analyseurs vectoriels de reseaux, et de caracterisation du facteur de bruit des transistors sont presentees dans une approche de test industriel. Les etapes de mesure, de calibrage et de correction, specifiquement appliquees a la caracterisation des technologies cmos et bicmos sur tranche de silicium, ont ete automatisees et decrites ainsi que les outils necessaires a cette caracterisation. Les resultats d'extraction des frequences de transition, des frequences maximales d'oscillation et des parametres de modeles des dispositifs actifs tels que les transistors bipolaires et mosfet, mais aussi les resultats de caracterisation d'elements passifs tels que les inductances ou les lignes de transmission sont presentes pour les technologies avancees cmos et bicmos 0,7 et 0,5 um
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Inanlou, Farzad Michael-David. "Innovative transceiver approaches for low-power near-field and far-field applications." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/52245.
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Wireless operation, near-field or far-field, is a core functionality of any mobile or autonomous system. These systems are battery operated or most often utilize energy scavenging as a means of power generation. Limited access to power, expected long and uninterrupted operation, and constrained physical parameters (e.g. weight and size), which limit overall power harvesting capabilities, are factors that outline the importance for innovative low-power approaches and designs in advanced low-power wireless applications. Low-power approaches become especially important for the wireless transceiver, the block in charge of wireless/remote functionality of the system, as this block is usually the most power hungry component in an integrated system-on-chip (SoC). Three such advanced applications with stringent power requirements are examined including space-based exploratory remote sensing probes and their associated radiation effects, millimeter-wave phased-array radar for high-altitude tactical and geological imaging, and implantable biomedical devices (IMDs), leading to the proposal and implementation of low-power wireless solutions for these applications in SiGe BiCMOS and CMOS and platforms.
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Ameziane, El Hassani Chama. "Contribution à la réalisation d’un oscillateur push-push 80GHz synchronisé par un signal subharmonique pour des applications radars anticollisions." Thesis, Bordeaux 1, 2010. http://www.theses.fr/2010BOR14025/document.
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Ce travail de thèse s’inscrit dans le cadre d’un projet Français « VéLo » qui est une collaboration entre l’industriel STMicroelectronics et plusieurs laboratoires dont les laboratoires IMS-bordeaux et LAAS. Le but du projet est de concevoir un prototype de radar anticollision millimétrique. Dans ce travail un synthétiseur de fréquence est implémenté. Ce dernier sera intégré dans la chaine de réception du démonstrateur. Une étude bibliographique des architectures classiques de système de radiocommunication a été réalisée. Des exemples d’architectures rencontrées dans le domaine millimétrique ont été étudiés.L’objet principal de cette thèse est l’étude des oscillateurs synchronisés par injection ILO. L’objectif est de réaliser un oscillateur verrouillé par injection qui sera piloté par un oscillateur de fréquence plus basse possédant des caractéristiques de stabilité et de bruit meilleures.Dans ce travail de thèse, le mécanisme de verrouillage des oscillateurs par injection a été décrit. Un modèle de synchronisation par injection série, basé sur la théorie de Huntoon Weiss et inspiré du travail de Badets réalisé sur les oscillateurs synchrones verrouillés par injection parallèle, est proposé. La théorie établie a permis d’exprimer la plage de synchronisation en fonction de la topologie utilisée et des composants de la structure. La validité de la théorie a été évaluée par la simulation de la structure. Les résultats présentés montrent une bonne concordance entre la simulation et la théorie et permettent de valider le principe de synchronisation par injection. La faisabilité de l’intégration d’un ILO millimétrique synchronisé par l’harmonique d’un signal de référence de fréquence plus basse a été démontrée expérimentalement. Le synthétiseur de fréquence est réalisé en technologie BiCMOS 130nm pour des applications millimétriques de STMicroelectronics. Ce dernier opère dans une plage de 2GHz autour de la fréquence 82,5GHz. Les performances en bruit du synthétiseur sont satisfaisantes. Le bruit de phase de l’ILO recopie celui du signal injecté. Les équipements de mesures utilisés, le bruit de phase de l’oscillateur atteint des valeurs inférieures à -110dBc/Hz à 1MHz de la porteuseThis thesis is a part of a French project "VELO". The project is collaboration between STMicroelectronics and several laboratories including IMS-Bordeaux and LAAS laboratories. The aim of this project is to achieve a prototype of millimeter anti-collision radar. In this work a frequency synthesizer is implemented. This circuit will be incorporated in the reception chain of the demonstrator. A bibliographical study of classical architecture was completed. Examples of architectures encountered in the millimeter frequency range have been studied. The purpose of this thesis is to study the phenomena of synchronization in oscillators. The objective is to design an injection locked oscillator ILO driven by another oscillator, the second oscillator operates at lower frequency and offers better stability and noise characteristics.In this thesis, the injection locking mechanism of the oscillators has been described. A model of synchronization by series injection is proposed. The model is based on the theory of Huntoon and Weiss and inspired by Badets’ work performed on parallel injection. The theory expresses the synchronized frequency range depending on the used topology and the values of the components. The validity of the theory was evaluated by simulation. The results show good agreement between simulation and theory and validate the principle of synchronization by injection.The feasibility of a millimeter ILO synchronized by the harmonic of a reference signal operating at lower frequency has been demonstrated experimentally. The synthesizer was implemented in BiCMOS technology for 130nm applications millimeter of STMicroelectronics. The oscillator operates at 82.5 GHz and performs a frequency range of 2GHz. The noise performance of the synthesizer is satisfactory. The phase noise of the ILO depends on the reference phase noise, and reaches values of -110dBc/Hz at 1MHz from the carrier frequency
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"BICMOS implementation of UAA 4802." Chinese University of Hong Kong, 1989. http://library.cuhk.edu.hk/record=b5886230.
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Han, Jin Si, and 金思漢. "A Study of Electromagnetic Interference effects on BiCMOS Integrated Circuits." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/42534788525333561066.
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碩士國立臺灣科技大學
電子工程技術研究所
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Today, the microprocessor has been continuously improved. Digital electronic devices are commonplace in small businesses, homes, and even toys. And, the problem of EMC in digital electronic devices becomes important. A study of EMI effects in low-voltage BiCMOS integrated circuits is presented in this paper. Suppose that EMI signals have been coupled into a terminal of BiCMOS integrated circuits by some mechanisms, the EMI suscepti-bility of BiCMOS IC is studied experimentally. Moreover, the vari-ety of DC characteristic and AC characteristic under different EMI frequencies and powers are investigated. We have also simulated the device behavior, with the aid of the SPICE software. According to the result of experiments and simulations, it is possible that the out-put signal is affected by the EMI, as the input signal changes from low level to high level near the transition region. Besides, consider-ing the clock, it is possible that the jittering of the output pulse signal results from the effect of EMI. Finally, the effect of the device package is discussed. The EMI can result in ringing and signal delay of the output voltage.
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Reddy, Reeshen. "Spurious free dynamic range enhancement of high-speed integrated digital to analogue converters using bicmos technology." Diss., 2015. http://hdl.handle.net/2263/48947.
Full textAbstract:
High-speed digital to analogue converters (DAC), which are optimised for large bandwidth signal synthesis applications, are a fundamental building block and enabling technology in industrial instrumentation, military, communication and medical applications. The spurious free dynamic range (SFDR) is a key specification of high-speed DACs, as unwanted spurious signals generated by the DAC degrades the performance and effectiveness of wideband systems. The focus of this work is to enhance the SFDR performance of high-speed DACs.
As bandwidth requirements increase, meeting the desired SFDR performance is further complicated by the increase in dynamic non-linearity. The most widely used architecture in high-speed applications is the current-steering DAC fabricated on CMOS technology. The current source finite output impedance, switch distortion and clock feedthrough are the greatest contributors to dynamic non-linearity and are difficult to improve with the use of MOS devices alone. This research proposes the use of BiCMOS technology that offers high performance, using heterojunction bipolar transistors (HBT) that, when combined with MOS devices, are able to improve on the linearity of the current-steering DAC and hence improve the SFDR.
A design methodology is introduced based on BiCMOS fabrication technology to improve SFDR performance and places emphasis on the constraints of modern fabrication processes. A six-bit current-steering application-specific integrated circuit DAC is designed based on the proposed design methodology, which optimises the SFDR performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect to verify the hypothesis experimentally.
A novel current source cell is implemented that comprises HBT current switches, negative channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. A switch driver and low-voltage differential signalling receiver to achieve high-speed DAC performance and their influence on the SFDR performance are designed and discussed.
The DAC is implemented using the International Business Machines Corporation (IBM) 8HP silicon germanium (SiGe) BiCMOS 130 nm technology. The DAC achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm2 and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in much larger power dissipation.Dissertation (MEng)--University of Pretoria, 2015.
Electrical, Electronic and Computer Engineering
MEng
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Beck, Jeffery S. "A programmable BiCMOS transconductance-capacitor filter for high frequencies." Thesis, 1993. http://hdl.handle.net/1957/36089.
Full textAbstract:
With advancements in CMOS technology, high speed analog circuits that were
traditionally implemented with discrete circuit components can now be made monolithically.
Antialiasing filters for video signals as well as signal conditioning filters in high
speed communication channels are examples of applications where high frequency integrated
circuits are now feasible. Transconductance-Capacitor or Gm-C filters are well
suited to these applications as they operate in the continuous-time domain and are able to
overcome the high-frequency and noise limitations imposed by clocked filter topologies.
This thesis covers the design of a programmable fourth-order Chebychev filter
with a 50MHz passband using the transconductance-C technique. A previously proposed
transconductor based upon a CMOS inverter is used to implement the filter. Since this
transconductor has no internal nodes, it can achieve extremely high bandwidths. However,
it requires a variable power source for programming. Thus, a wide-band, on-chip,
variable-BiCMOS power supply is presented as the method for setting the transconductance.
Practical design issues are addressed as well as many methods for compensating
non-idealities. Simulations of the filter as well as some parametric measurement of the
filter structures are presented.Graduation date: 1994
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Rezaei, Farshid. "Realizing vertical bipolar transistors in a standard CMOS technology for the design of low-cost BiCMOS integrated circuits." 2004. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=95041&T=F.
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Lambrechts, Johannes Wynand. "Modelling of transceiver propagation characteristics through an analogue SiGe BiCMOS integrated circuit." Thesis, 2013. http://hdl.handle.net/2263/32461.
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Bethel, Ryan H. "Low voltage BiCOMS circuit topologies for the design of a 19GHz, 1.2V, 4-Bit accumulator in silicon-germanium /." 2007. http://www.library.umaine.edu/theses/pdf/BethelRH2007.pdf.
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Lambrechts, Johannes Wynand. "Phase noise reduction of a 0.35 μm BiCMOS SiGe 5 GHz Voltage Controlled Oscillator." Diss., 2009. http://hdl.handle.net/2263/29413.
Full textAbstract:
The research conducted in this dissertation studies the issues regarding the improvement of phase noise performance in a BiCMOS Silicon Germanium (SiGe) cross-coupled differential-pair voltage controlled oscillator (VCO) in a narrowband application as a result of a tail-current shaping technique. With this technique, low-frequency noise components are reduced by increasing the signal amplitude without consuming additional power, and its effect on overall phase noise performance is evaluated. The research investigates effects of the tail-current as a main contributor to phase noise, and also other effects that may influence the phase noise performance like inductor geometry and placement, transistor sizing, and the gain of the oscillator. The hypothesis is verified through design in a standard 0.35 μm BiCMOS process supplied by Austriamicrosystems (AMS). Several VCOs are fabricated on-chip to serve for a comparison and verify that the employment of tail-current shaping does improve phase noise performance. The results are then compared with mathematical models and simulated results, to confirm the hypothesis. Simulation results provided a 3.3 dBc/Hz improvement from -105.3 dBc/Hz to -108.6 dBc/Hz at a 1 MHz offset frequency from the 5 GHz carrier when employing tail-current shaping. The relatively small increase in VCO phase noise performance translates in higher modulation accuracy when used in a transceiver, therefore this increase can be regarded as significant. Parametric analysis provided an additional 1.8 dBc/Hz performance enhancement in phase noise that can be investigated in future works. The power consumption of the simulated VCO is around 6 mW and 4.1 mW for the measured prototype. The circuitry occupies 2.1 mm2 of die area. CopyrightDissertation (MEng)--University of Pretoria, 2010.
Electrical, Electronic and Computer Engineering
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