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Journal articles on the topic 'BiCMOS integrated circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 11 February 2022

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1

Jensen, Thomas, Thualfiqar Al-Sawaf, Marco Lisker, Srdjan Glisic, Mohamed Elkhouly, Tomas Kraemer, Ina Ostermay, et al. "Millimeter-wave hetero-integrated sources in InP-on-BiCMOS technology." International Journal of Microwave and Wireless Technologies 6, no. 3-4 (May 12, 2014): 225–33. http://dx.doi.org/10.1017/s1759078714000579.

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The paper presents millimeter-wave (mm-wave) signal sources using a hetero-integrated InP-on-BiCMOS semiconductor technology. Mm-wave signal sources feature fundamental frequency voltage-controlled oscillators (VCOs) in BiCMOS, which drive frequency multiplier–amplifier chains in transferred-substrate (TS) InP-DHBT technology, heterogeneously integrated on top of the BiCMOS wafer in a wafer-level bonding process. Both circuits are biased through a single set of bias pads and compact low-loss transitions from BiCMOS to InP circuits and vice versa have been developed, which allows seamless signal routing through both technologies exhibiting 0.5 dB insertion loss up to 200 GHz. One VCO operates at 82 GHz with a tuning range of 600 MHz and an output power of approximately 8 dBm. A frequency doubler combined with this VCO circuit delivers 0 dBm at 164 GHz and a frequency tripler with a similar VCO delivers −10 dBm at 246 GHz. Another hetero-integrated W-band doubler–amplifier circuit demonstrates 12.9 dBm saturated output power with 5.9 dB conversion gain at 96 GHz. A direct comparison of the TS InP-DHBT MMIC with either silicon or traditional AlN carrier substrates shows the favorable properties of the hetero-integrated process discussed here. The results demonstrate the feasibility of hetero-integrated circuits operating well above 100 GHz.
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2

Kazior, Thomas E. "Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130105. http://dx.doi.org/10.1098/rsta.2013.0105.

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Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.
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3

Joardar, Kuntal. "Substrate crosstalk in BiCMOS mixed mode integrated circuits." Solid-State Electronics 39, no. 4 (April 1996): 511–16. http://dx.doi.org/10.1016/0038-1101(95)00189-1.

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4

Lahbib, Imene, Mohamed Aziz Doukkali, Philippe Descamps, Patrice Gamand, Christophe Kelma, and Olivier Tesson. "Design and characterization of an integrated microwave generator for BIST applications." International Journal of Microwave and Wireless Technologies 6, no. 2 (February 27, 2014): 195–200. http://dx.doi.org/10.1017/s1759078714000105.

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This paper presents a circuit architecture for a new integrated on chip test method for microwave circuits. The proposed built-in-self-test (BIST) cell targets a direct low-cost measurement technique of the gain and the 1 dB input compression point (CP1) of a K-band satellite receiver in the 18–22 GHz frequency bandwidth. A signal generator at the radiofrequency (RF) front end input of the device under test (DUT) has been integrated on the same chip. To inject this RF signal, a loopback technique has been used and the design has been accommodated for it. This paper focuses on the design of the most sensitive block of the BIST circuit, i.e. the RF signal generator. This circuit, fabricated in a SIGe:C BiCMOS process, consumes 10 mA. It presents a dynamic power range of 17 dB (−41; −24 dBm) and operates in a frequency range of 5.6 GHz (17.5; 23 GHz). This BIST circuit gives new perspectives in terms of test strategy, cost reduction, and measurement accuracy for microwave-integrated circuits and could be adapted for mm-wave circuits.
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5

Filippov, Ivan, Nikolay Duchenko, and Yuri Gimpilevich. "Particularities of complex-functional monolithic integrated circuits post-layout simulation." ITM Web of Conferences 30 (2019): 01003. http://dx.doi.org/10.1051/itmconf/20193001003.

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This paper presents a silicon-based complex-functional monolithic microwave integrated circuits (MMICs) design methodology. Post-layout simulation stage particularities are discussed. Pre-tapeout functionality verification results of the C-band phase and amplitude control MMIC based on 0.18 μm SiGe BiCMOS technology are also presented.
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6

Friedman, D. J., M. Meghelli, B. D. Parker, J. Yang, H. A. Ainspan, A. V. Rylyakov, Y. H. Kwark, et al. "SiGe BiCMOS integrated circuits for high-speed serial communication links." IBM Journal of Research and Development 47, no. 2.3 (March 2003): 259–82. http://dx.doi.org/10.1147/rd.472.0259.

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7

FRITZ, KARL E., BARBARA A. RANDALL, GREGG J. FOKKEN, MICHAEL J. DEGERSTROM, MICHAEL J. LORSUNG, JASON F. PRAIRIE, ERIC L. H. AMUNDSEN, et al. "HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY." International Journal of High Speed Electronics and Systems 13, no. 01 (March 2003): 221–37. http://dx.doi.org/10.1142/s0129156403001582.

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Under the auspices of Defense Advanced Research Project Agency's Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology, simulations and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS 5HP (50 GHz fT HBTs with 0.5 μm CMOS) and 7HP (120 GHz fT HBTs with 0.18 μm CMOS) technologies will be presented.
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8

Fujishima, Minoru. "Key Technologies for THz Wireless Link by Silicon CMOS Integrated Circuits." Photonics 5, no. 4 (November 23, 2018): 50. http://dx.doi.org/10.3390/photonics5040050.

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In terahertz-band communication using ultra-high frequencies, compound semiconductors with superior high-frequency performance have been used for research to date. Terahertz communication using the 300 GHz band has nonetheless attracted attention based on the expectation that an unallocated frequency band exceeding 275 GHz can be used for communication in the future. Research into wireless transceivers using BiCMOS integrated circuits with silicon germanium transistors and advanced miniaturized CMOS integrated circuits has increased in this 300 GHz band. In this paper, we will outline the terahertz communication technology using silicon integrated circuits available from mass production, and discuss its applications and future.
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9

Lee, Chan-Soo, Young-Jin Oh, Kee-Yeol Na, Yeong-Seuk Kim, and Nam-Soo Kim. "Integrated BiCMOS Control Circuits for High-Performance DC–DC Boost Converter." IEEE Transactions on Power Electronics 28, no. 5 (May 2013): 2596–603. http://dx.doi.org/10.1109/tpel.2012.2217156.

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10

Klatser, Paul, Marc Van Der Vossen, Gerard Voshaar, Rinus Boot, Adriaan Hulzinga, Maikel Iven, and Chris Roeloffzen. "An ultra flat phased array Ku-band antenna with integrated receivers in SiGe BiCMOS." International Journal of Microwave and Wireless Technologies 7, no. 3-4 (June 2015): 379–89. http://dx.doi.org/10.1017/s1759078715000999.

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A highly integrated Ku-band (10.7–12.75 GHz) planar phased array receiver of 64 antenna elements is presented. It features instantaneous reception of the full Ku-band (2.05 GHz wide) in two orthogonal polarizations with wide scan angles by using time delay instead of phase shift. The receiver is part of a system for satellite broadcast TV reception on board of moving vehicles. Two SiGe radio frequency integrated circuits (RFICs) were developed, packaged in ceramic BGAs and assembled onto a 15-layer printed circuit board (PCB) which integrates the antenna elements. An outline of the system is given along with a detailed description. It sets a new standard in integration density. The receiver has extensive analog signal processing at intermediate frequency (IF)-level. A novel bipolar implementation for true time delay is proposed, with a continuous programmable delay range of 0…80 ps with less than 2.5 ps group-delay variation in 2 GHz bandwidth (BW). The wide BW calls for a constant group-delay implementation in the IF chain. The receiver (RFIC) consumes only 132 mW per channel. Each channel has 40 dB gain.
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11

Lee, Chan-Soo, Eui-Jin Kim, Munkhsuld Gendensuren, Nam-Soo Kim, and Kee-Yeol Na. "High Performance Current-Mode DC-DC Boost Converter in BiCMOS Integrated Circuits." Transactions on Electrical and Electronic Materials 12, no. 6 (December 25, 2011): 262–66. http://dx.doi.org/10.4313/teem.2011.12.6.262.

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12

Kieschnick, K., H. Zimmermann, and P. Seegebrecht. "Silicon-based optical receivers in BiCMOS technology for advanced optoelectronic integrated circuits." Materials Science in Semiconductor Processing 3, no. 5-6 (October 2000): 395–98. http://dx.doi.org/10.1016/s1369-8001(00)00062-7.

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13

Ellinger, Frank, David Fritsche, Gregor Tretter, Jan Dirk Leufker, Uroschanit Yodprasit, and C. Carta. "Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications." Frequenz 71, no. 1-2 (January 1, 2017): 1–9. http://dx.doi.org/10.1515/freq-2016-0119.

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Abstract In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.
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14

Lee, Changyeop, Gyuseong Cho, Troy Unruh, Seop Hur, and Inyong Kwon. "Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad." Sensors 20, no. 10 (May 12, 2020): 2765. http://dx.doi.org/10.3390/s20102765.

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.
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15

Božanić, Mladen, and Saurabh Sinha. "Emerging Transistor Technologies Capable of Terahertz Amplification: A Way to Re-Engineer Terahertz Radar Sensors." Sensors 19, no. 11 (May 29, 2019): 2454. http://dx.doi.org/10.3390/s19112454.

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This paper reviews the state of emerging transistor technologies capable of terahertz amplification, as well as the state of transistor modeling as required in terahertz electronic circuit research. Commercial terahertz radar sensors of today are being built using bulky and expensive technologies such as Schottky diode detectors and lasers, as well as using some emerging detection methods. Meanwhile, a considerable amount of research effort has recently been invested in process development and modeling of transistor technologies capable of amplifying in the terahertz band. Indium phosphide (InP) transistors have been able to reach maximum oscillation frequency (fmax) values of over 1 THz for around a decade already, while silicon-germanium bipolar complementary metal-oxide semiconductor (BiCMOS) compatible heterojunction bipolar transistors have only recently crossed the fmax = 0.7 THz mark. While it seems that the InP technology could be the ultimate terahertz technology, according to the fmax and related metrics, the BiCMOS technology has the added advantage of lower cost and supporting a wider set of integrated component types. BiCMOS can thus be seen as an enabling factor for re-engineering of complete terahertz radar systems, for the first time fabricated as miniaturized monolithic integrated circuits. Rapid commercial deployment of monolithic terahertz radar chips, furthermore, depends on the accuracy of transistor modeling at these frequencies. Considerations such as fabrication and modeling of passives and antennas, as well as packaging of complete systems, are closely related to the two main contributions of this paper and are also reviewed here. Finally, this paper probes active terahertz circuits that have already been reported and that have the potential to be deployed in a re-engineered terahertz radar sensor system and attempts to predict future directions in re-engineering of monolithic radar sensors.
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16

Dolny, G. "Design and Characterization of High Performance Power Integrated Circuits in a BiCMOS Technology." ECS Proceedings Volumes 1989-15, no. 1 (January 1989): 479–89. http://dx.doi.org/10.1149/198915.0479pv.

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17

Mesadri, Conrado K., Aziz Doukkali, Philippe Descamps, and Christophe Kelma. "A new methodology for optimal RF DFT sensor design." International Journal of Microwave and Wireless Technologies 4, no. 5 (July 3, 2012): 515–21. http://dx.doi.org/10.1017/s1759078712000499.

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In this paper, a new methodology to compare the robustness of sensor structures employed in radiofrequency design for test (RF DFT) architectures for RF integrated circuits (ICs) is proposed. First, the yield loss and defect level of the test technique is evaluated using a statistical model of the Circuit under Test (obtained through non-parametric statistics and copula theory). Then, by carrying out the dispersion analysis of the sensor architecture, a figure of merit is established. This methodology reduces the number of iterations in the design flow of RF DFT sensors and makes it possible to evaluate process dispersion. The case study is a SiGe:C BiCMOS LNA tested by a single-probe measurement.
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18

Zhao, Xianghong, Jieyu Zhao, and WeiMing Cai. "A General Structure and High-Performance Dual-Edge Triggered Level Converting Flip–Flop Based on BiCMOS." Journal of Nanoelectronics and Optoelectronics 15, no. 1 (January 1, 2020): 136–41. http://dx.doi.org/10.1166/jno.2020.2702.

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Dual supply voltage scheme provides very effective solution to cut down power consumption in digital integrated circuits design, where level converting flip–flops (LCFF) are the key component circuits. In this paper, a new general structure and design method for dual-edge triggered LCFF based on BiCMOS is proposed, according to that PNP-PNP-DELCFF and NPN-NPN-DELCFF are designed. The experiments carried out by Hspice using TSMC 180 nm show proposed circuits have correct logic functions. Compared to counterparts, proposed PNP-PNP-DELCFF gains improvements of 6.7%, 96.0%, 86.0% and 28.5% in D-Q Delay, 50.0%, 16.0%, 12.6% and 10.8% in product of delay and power (PDP), respectively. NPN-NPN-DELCFF gains improvements of 5.1%, 93.0%, 83.2% and 26.5% in D-Q Delay, 39.7%, 7.9%, 5.0% and 3.4% in PDP, respectively. Furthermore, proposed circuits have better drive ability.
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19

Ahlgren, D. C., S. J. Jeng, D. Nguyen-Ngoc, K. Stein, D. Sunderland, M. Gilbert, J. Malinowski, et al. "Si-Ge heterojunction bipolar technology for high-speed integrated circuits." Canadian Journal of Physics 74, S1 (December 1, 1996): 159–66. http://dx.doi.org/10.1139/p96-851.

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This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of the graded base SiGe HBT are reviewed. These principles are then used to explore the design optimization for analog applications. Device results are presented that illustrate some important trade-offs in device design. A discussion of the use of UHV/CVD for the deposition of the epitaxial base profile is followed by an overview of the integrated process. This process, which has been installed on 200 mm wafers in IBM's Advanced Semiconductor Technology Center in Hopewell Junction, N.Y., also includes a full range of support devices. The process has demonstrated SiGe HBT performance, reliability, and yield in a CMOS fabrication with the addition of only one tool for UHV/CVD deposition of the epi-base and, with minimal additional process steps, can be used to fabricate full BiCMOS designs. This paper concludes with a discussion of high-performance circuits fabricated to date, including ECL ring'oscillators, power amplifiers, low-noise amplifiers, voltage-controlled oscillators, and finally a 12-bit DAC that features nearly 3000 SiGe HBT devices demonstrating medium-scale integration.
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20

Carpenter, Sona, Zhongxia Simon He, and Herbert Zirath. "Multi-functional D-bandI/Qmodulator/demodulator MMICs in SiGe BiCMOS technology." International Journal of Microwave and Wireless Technologies 10, no. 5-6 (April 3, 2018): 596–604. http://dx.doi.org/10.1017/s1759078718000338.

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AbstractThis paper presents the design and characterization of a D-band (110–170 GHz) monolithic microwave integrated direct carrier quadrature modulator and demodulator circuits with on-chip quadrature local oscillator (LO) phase shifter and radio frequency (RF) balun fabricated in a 130 nm SiGe BiCMOS process withft/fmaxof 250 GHz/400 GHz. These circuits are suitable for low-power ultra-high-speed wireless communication and can be used in both homodyne and heterodyne architectures. In single-sideband operation, the modulator demonstrates a maximum conversion gain of 9.8 dB with 3-dB RF bandwidth of 33 GHz (from 119 GHz to 152 GHz). The measured image rejection ratio (IRR) and LO suppression are 19 dB and 31 dB, respectively. The outputP1dBis −4 dBm at 140 GHz RF and 1 GHz intermediate frequency (IF) and the chip consumes 53 mW dc power. The demodulator, characterized as an image reject mixer, exhibits 10 dB conversion gain with 23-dB IRR. The measured 3-dB RF bandwidth is 36 GHz and the IF bandwidth is 18 GHz. The active area of both the chips is 620 µm × 480 µm including the RF and LO baluns. A 12-Gbit/s QPSK data transmission using 131-GHz carrier signal is demonstrated on modulator with measured modulator-to-receiver error vector magnitude of 21%.
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21

Елесина, В. В., and И. О. Метелкин. "ТИРИСТОРНЫЙ ЭФФЕКТ В СВЧ ИС, ИЗГОТОВЛЕННЫХ ПО SIGE БИКМОП-ТЕХНОЛОГИЯМ." NANOINDUSTRY Russia 96, no. 3s (June 15, 2020): 612–14. http://dx.doi.org/10.22184/1993-8578.2020.13.3s.612.614.

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Проведен анализ случаев возникновения тиристорного эффекта в СВЧ ИС, изготовленных по технологии SiGe БиКМОП, при воздействии ионизирующего излучения. Рассмотрены области СВЧ ИС, чувствительные к возникновению ТЭ, определены основные параметры тиристорных структур. Проведена апробация подхода к восстановлению параметров схемно-топологической радиационно-ориентированной модели тиристорной структуры для САПР. The paper analyzes ionizing radiation induced latchup in microwave SiGe BiCMOS integrated circuits (ICs). Critical parts of ICs sensitive to latchup have been identified and basic parameters of corresponding parasitic thyristor structures have been determined. An approach has been approved to the thyristor structure compact model parameters extraction procedure intended for use in CAD systems.
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22

Fan, X., G. Fischer, and B. Dietrich. "An integrated 3.1–5.1 GHz pulse generator for ultra-wideband wireless localization systems." Advances in Radio Science 4 (September 6, 2006): 247–50. http://dx.doi.org/10.5194/ars-4-247-2006.

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Abstract. This paper presents an implementation of an integrated Ultra-wideband (UWB), Binary-Phase Shift Keying (BPSK) Gaussian modulated pulse generator. VCO, multiplier and passive Gaussian filter are the key components. The VCO provides the carrier frequency of 4.1 GHz, the LC Gaussian filter is responsible for the pulse shaping in the baseband. Multiplying the baseband pulse and the VCO frequency shifts the pulse to the desired center frequency. The generated Gaussian pulse ocupppies the frequency range from 3.1 to 5.1 GHz with the center frequency at 4.1 GHz. Simulations and measured results show that this spectrum fulfills the mask for indoor communication systems given by the FCC (Federal Communications Commission, 2002). The total power consumption is 55 mW using a supply voltage of 2.5 V. Circuits are realized using the IHP 0.25 μm SiGe:C BiCMOS technology.
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Berg, Håkan, Heiko Thiesies, and Niklas Billström. "Low-cost TRM technologies for phased array radars." International Journal of Microwave and Wireless Technologies 1, no. 4 (June 19, 2009): 369–75. http://dx.doi.org/10.1017/s1759078709990304.

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Low-cost enabling technologies for T/R modules (TRMs) in phased array radars are proposed and analyzed in terms of technology, performance, and cost aspects. Phase and amplitude controlling integrated circuits (ICs) realized in a low-cost standard silicon process are demonstrated. The design of several ICs at the S-, C-, on X-band has shown that silicon germanium is a strong contender for gallium arsenide. This also applies to TRMs suited for military active phased array antenna (AESA) radars. The circuits presented in this paper are manufactured by austriamicrosystems in their 0.35 µm SiGe-BiCMOS process with an fT of around 70 GHz. A TRM packaging concept based on soldered surface-mount technology and organic substrates is also demonstrated. A cost analysis concludes that by using the proposed packaging concept and the SiGe core-chip technology, the TRM production cost can be potentially reduced by 70% compared to traditional ceramic hermetic packaging with core chip in GaAs technology.
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24

Gnana Prakash, A. P., and N. Pushpa. "Application of Pelletron Accelerator to Study High Total Dose Radiation Effects on Semiconductor Devices." Solid State Phenomena 239 (August 2015): 37–71. http://dx.doi.org/10.4028/www.scientific.net/ssp.239.37.

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Silicon bipolar junction transistors (BJTs), Silicon-germanium heterojunction bipolar transistors (SiGe HBTs) and metal oxide semiconductor (MOS) devices are the key components of BiCMOS integrated circuits. The semiconductor devices need to withstand very high total doses (100’s of Mrad) for reliable operation of electronic circuits for 8-10 years of LHC operation. The study of radiation tolerance of semiconductor devices up to 100 Mrad of total dose takes longer time with conventional 60Co gamma, proton and electron irradiation facilities and the effects due to these radiations are well understood. Hence it is important to study the effects of heavy ion irradiation on various semiconductor devices. The irradiation time decreases with increasing linear energy transfer (LET) of incident radiation and LET increases with atomic number of the impinging ions. But it is essential to understand the mechanism of energy transfer by different heavy ions in semiconductor devices. Therefore, here we give an overview of different heavy ion interactions with Si BJTs, MOSFETs and SiGe HBTs by primarily focusing on the electrical characteristics of these devices before and after ion irradiation. We show that the irradiation time needed to reach very high total dose can be reduced by using Pelletron accelerator facilities instead of conventional irradiation facilities.
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Lahbib, Insaf, Sidina Wane, Aziz Doukkali, Dominique Lesénéchal, Thanh Vinh Dinh, Laurent Leyssenne, Rosine Coq Germanicus, et al. "Reliability analysis of BiCMOS SiGe:C technology under aggressive conditions for emerging RF and mm-wave applications: proposal of reliability-aware circuit design methodology." International Journal of Microwave and Wireless Technologies 10, no. 5-6 (June 2018): 690–99. http://dx.doi.org/10.1017/s1759078718000624.

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AbstractIn this contribution, the impact of extreme environmental conditions in terms of energy-level radiation of protons on silicon–germanium (SiGe)-integrated circuits is experimentally studied. Canonical representative structures including linear (passive interconnects/antennas) and non-linear (low-noise amplifiers) are used as carriers for assessing the impact of aggressive stress conditions on their performances. Perspectives for holistic modeling and characterization approaches accounting for various interaction mechanisms (substrate resistivity variations, couplings/interferences, drift in DC and radio frequency (RF) characteristics) for active samples are down to allow for optimal solutions in pushing SiGe technologies toward applications with harsh and radiation-intense environments (e.g. space, nuclear, military). Specific design prototypes are built for assessing mission-critical profiles for emerging RF and mm-wave applications.
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26

Jones, Simon. "Digital BiCMOS Integrated Circuit Design." Microprocessors and Microsystems 18, no. 1 (January 1994): 55. http://dx.doi.org/10.1016/0141-9331(94)90024-8.

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27

Benko, Pedro Luiz, Milene Galeti, Cleiton Fidelix Pereira, Julio Cesar Lucchi, and Renato Camargo Giacomini. "Bio-Amplifier based on MOS bipolar Pseudo-Resistors: A New Approach using its non-linear characteristic." Journal of Integrated Circuits and Systems 11, no. 2 (December 28, 2016): 132–39. http://dx.doi.org/10.29292/jics.v11i2.437.

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This paper proposes a new and refined bio-amplifier design, which associates DC offset cancellation, adequate frequency response and buffered outputs to a significant reduction of the signal recovery time. A MOS-Bipolar pseudo-resistor integrated to the feedback network of a single-stage Operational Transconductance Amplifier and the source-follower buffers give to the new topology its main advantages. This architecture makes use of the high resistance values of these pseudo-resistors to eliminate the offset DC level input preserving the low cut-off frequency, without the need of high capacitances, thereby significantly reducing the active die area, which enables its use as a front-end pre-amplifier assembled directly on the acquisition probes. The recovery time after an input voltage transitory of high-amplitude is an important characteristic of the bio-potential amplifiers due to their very low cut-off frequency. The proposed bio-amplifier utilizes the non-linear characteristics of the pseudo-resistor in the recovery time reduction. This time was evaluated and the topology presented a significant contribution in this aspect, assuming values 90% lower when compared with the same topology using a constant resistance. The new amplifier allows voltage gain of 30dB from 0.6 Hz to 2 kHz, and Total Harmonic Distortion (THD) of 0.19% for an input signal of 10Hz. This work also provides a behavioral spice model for MOS-Bipolar pseudo-resistor, which allows an accurate simulation of the linear and nonlinear pseudo-resistor characteristics, obtained through an experimental method of indirect characterization. This method is based on the transitory response from a first order RC low pass filter. The experimental characterization method is of fundamental importance, due to the absence of appropriate SPICE models that describe with precision the pseudo-resistance behavior. The circuits were manufactured by MOSIS on 8HP SiGe BiCmos Global Foundries 0.13μm technology.
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28

Hatfield, John. "Book Review: Digital BiCMOS Integrated Circuit Design:." International Journal of Electrical Engineering & Education 32, no. 1 (January 1995): 86. http://dx.doi.org/10.1177/002072099503200112.

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29

Hossain, Maruf, Ina Ostermay, Nils G. Weimann, Franz Josef Schmueckle, Johannes Borngraeber, Chafik Meliani, Marco Lisker, et al. "Performance study of a 248 GHz voltage controlled hetero-integrated source in InP-on-BiCMOS technology." International Journal of Microwave and Wireless Technologies 9, no. 2 (November 13, 2015): 259–68. http://dx.doi.org/10.1017/s1759078715001634.

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This paper presents the performance study of a 248 GHz voltage-controlled hetero-integrated signal source using indium phosphide (InP)-on-bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The source consists of a voltage controlled oscillator (VCO) in 0.25 µm BiCMOS technology and a frequency multiplier in 0.8 µm transferred-substrate InP-heterojunction bipolar transistor technology, which is integrated on top of the BiCMOS monolithic microwave integrated circuit in a wafer-level based benzocyclobutene bonding process. The vertical transitions from BiCMOS to InP in this process exhibit broadband properties with insertion losses below 0.5 dB up to 325 GHz. The VCO operates at 82.7 GHz with an output power of 6 dBm and the combined circuit delivers −9 dBm at 248 GHz with 1.22% tuning range. The phase noise of the combined circuit is −85 dBc/Hz at 1 MHz offset. The measured output return loss of the hetero-integrated source is >10 dB within a broad frequency range. This result shows the potential of the hetero integrated process for THz frequencies.
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30

Yu, Bing Liang, Xiao Ning Xie, and Wen Yuan Li. "A Full Integrated LNA in 0.18μm SiGe BiCMOS Technology." Applied Mechanics and Materials 380-384 (August 2013): 3287–91. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3287.

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A fully integrated low noise amplifier (LNA) for wireless local area network (WLAN) application is presents. The circuit is fabricated in 0.18μm SiGe BiCMOS technology. For the low noise figure, a feedback path is introduced into the traditional inductively degenerated common emitter cascade LNA, which decreases the inductance for input impedance matching, therefore reduces the thermal noise caused by loss resistor. Impedance matching and noise matching are achieved at the same time. Measured results show that the resonance point of the output resonance network shifts from 2.4GHz to 2.8GHz, due to the parasitic effects at the output. At the frequency of 2.8GHz, the LNA achieves 2.2dB noise figure, 19.4dB power gain. The core circuit consumes only 13mW from a 1.8V supply and occupies less than 0.5mm2.
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31

Hervé, C., D. Dzahini, T. Le Caër, J. P. Richer, and K. Torki. "BiCMOS amplifier–discriminator integrated circuit for gas-filled detector readout." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 540, no. 2-3 (March 2005): 437–47. http://dx.doi.org/10.1016/j.nima.2004.11.037.

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32

Baschirotto, A., M. Cassis, P. Kirchlechner, F. Montecchi, G. Palmisano, and D. Rossi. "An analog BiCMOS integrated circuit for front-end RDS decoder." IEEE Transactions on Consumer Electronics 37, no. 3 (1991): 585–91. http://dx.doi.org/10.1109/30.85571.

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33

Dondon, Ph, Ch Zardini, and J. L. Aucouturier. "BiCMOS integrated circuit for capacitive pressure sensors in automotive applications." Sensors and Actuators A: Physical 37-38 (June 1993): 596–99. http://dx.doi.org/10.1016/0924-4247(93)80102-m.

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34

Snegur, Dmitriy, and Andrey Schekaturin. "Design of patch active electronically scanned antenna for 5G communication system." ITM Web of Conferences 30 (2019): 05014. http://dx.doi.org/10.1051/itmconf/20193005014.

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The article deals with the research and design results of an active electronically scanned antenna (AESA) based on beamforming BiCMOS monolithic integrated circuit (MIC) and patch antenna radiators. The operating frequency band is sub-6 GHz. MIC design is at the stage of transferring files to the manufacture and verification of integrated circuit parameters. In this regard, the current task is the antenna radiators design, that is the main focus of this paper.
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35

Winkler, W., J. Borngräber, B. Heinemann, H. Rücker, R. Barth, J. Bauer, D. Bolze, et al. "Circuit applications of high-performance SiGe:C HBTs integrated in BiCMOS technology." Applied Surface Science 224, no. 1-4 (March 2004): 297–305. http://dx.doi.org/10.1016/j.apsusc.2003.08.058.

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36

PAVAN, SHANTHI, MAURICE TARSIA, STEFFEN KUDSZUS, and DAVID PRITZKAU. "DESIGN CONSIDERATIONS FOR INTEGRATED MODULATOR DRIVERS IN SILICON GERMANIUM TECHNOLOGY." International Journal of High Speed Electronics and Systems 15, no. 03 (September 2005): 477–95. http://dx.doi.org/10.1142/s0129156405003284.

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We present design considerations for high speed high swing differential modulator drivers in SiGe BiCMOS technology. Trade-offs between lumped and distributed designs, and linear and limiting amplifiers are examined. The design of a 6 V output modulator driver is discussed in detail. The driver features a unique bias generation and distribution circuit that enables low power-supply operation. Simulation results and measurements are given.
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37

MCPHERSON, D. S., H. TRAN, and P. POPESCU. "A 10 GB/S EQUALIZER WITH INTEGRATED CLOCK AND DATA RECOVERY FOR OPTICAL COMMUNICATION SYSTEMS." International Journal of High Speed Electronics and Systems 15, no. 03 (September 2005): 525–48. http://dx.doi.org/10.1142/s0129156405003314.

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A 10 Gb/s analog continuous-time equalizer with integrated clock and data recovery circuit is presented. It is designed to recover signals degraded by chromatic and polarization mode dispersion. The key components in the design are a feedforward equalizer and a decision feedback equalizer, the parameters of which are electronically adjustable. Both circuit blocks are fully described and characterized with emphasis on minimizing self-induced distortion and maximizing high-speed performance. In addition to the equalizer and the clock and data recovery, the circuit also includes an integrated automatic gain control. The circuit is implemented in a commercial 0.18 μm SiGe BiCMOS technology and consumes 900 mW. The capacity of the equalizer to mitigate signal impairments is demonstrated using three electrically generated channels.
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38

Savchenko, E. M., A. S. Budiakov, P. S. Budiakov, and N. N. Prokopenko. "The Method of Bandwidth Extension of SiGe BiCMOS Microwave Variable-Gain Amplifier Integrated Circuit." Visnyk NTUU KPI Seriia - Radiotekhnika Radioaparatobuduvannia, no. 69 (June 30, 2017): 5–10. http://dx.doi.org/10.20535/radap.2017.69.5-10.

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39

Krupar, Joerg, Heiko Hauswald, and Ronny Naumann. "A Substrate Current Less Control Method for CMOS Integration of Power Bridges." Advances in Power Electronics 2010 (September 23, 2010): 1–11. http://dx.doi.org/10.1155/2010/909612.

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Modern electronical devices use high integration to decrease device size and cost and to increase reliability. More and more devices appear that integrate even power devices into VLSI circuits. When driving inductive loads, this is a critical step because freewheeling at a power device appears. In these applications usually special technologies with extra wells for the power devices, SOI technologies, or BiCMOS technologies are required to suppress any substrate current. However, the use of these technologies results in higher production cost for the device. We present a method to control the freewheeling actively. Using this approach we are able to integrate the power devices using a normal CMOS technology.
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40

Pinto, Yenny, Christian Person, Daniel Gloria, Andreia Cathelin, Didier Belot, Sébastien Pruvost, and Robert Plana. "SIP antenna on 0.13 µm SiGe technology at 79 GHz for SRR automotive radar." International Journal of Microwave and Wireless Technologies 1, no. 6 (December 2009): 529–36. http://dx.doi.org/10.1017/s175907870999081x.

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This paper describes the analysis and the design of an integrated antenna on 0.13 µm SiGe BICMOS technology. A non-resonant dipole antenna integrated on SiGe is electromagnetically coupled to a radiating element reported on a printed circuit board (PCB) substrate. This integrated solution, also compatible with system in package (SIP) concept, provides significant improvements with respect to direct System On Chip (SoC) integration. The main objective of this SIP antenna lies on the optimization of integrated millimeter wave front-ends modules, considering the immediate antenna environment (especially the lossy substrate and technological dielectric/metallic levels), in order to achieve performances compatible with short range radar specifications at 79–81 GHz. One solution, using a RT/Rogers Duroid 6006 PCB (er = 6, thickness h = 127 µm), is presented, providing a 2.93 dBi gain, and 45% radiation efficiency antenna.
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41

Han, Jingyu, Yu Jiang, Guiliang Guo, and Xu Cheng. "A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process." Electronics 9, no. 5 (May 18, 2020): 831. http://dx.doi.org/10.3390/electronics9050831.

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A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable Gm-C low pass filter, a DC offset cancellation circuit, two fixed gain amplifiers with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. The noise figure is reduced with the help of a low noise pre-amplifier stage, while the linearity is enhanced with a power-efficient buffer and a novel high linearity Gm-C filter. Specifically, the Gm-C filter improves its linearity specification with no increase in power consumption, thanks to an alteration of the trans-conductor/capacitor connection style, instead of pursuing high linearity but power-hungry class-AB trans-conductors. In addition, the logarithmic bandwidth tuning technique is adopted for capacitor array size minimization. The linear-in-dB and DAC gain control topology facilitates the analog baseband gain tuning accuracy and stability, which also provides an efficient access to digital baseband automatic gain control. The analog baseband chip is fabricated using 130-nm SiGe BiCMOS technology. With a power consumption of 5.9~8.8 mW, the implemented circuit achieves a tunable gain range of −30~27 dB (DAC linear gain step guaranteed), a programmable −3 dB bandwidth of 18/19/20/21/22/23/24/25 MHz, a filter order of 3/6 and a gain resolution of better than 0.07 dB.
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42

Smith, M. J. S., C. Portmann, C. Anagnostopoulos, P. S. Tschang, R. Rao, P. Valdenaire, and H. Ching. "Cell libraries and assembly tools for analog/digital CMOS and BiCMOS application-specific integrated circuit design." IEEE Journal of Solid-State Circuits 24, no. 5 (October 1989): 1419–32. http://dx.doi.org/10.1109/jssc.1989.572628.

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43

Wang, Defu, Klaus Schmalz, Mohamed Hussein Eissa, Johannes Borngraber, Maciej Kucharski, Mohamed Elkhouly, Minsu Ko, Herman Jalli Ng, and Dietmar Kissinger. "Integrated 240-GHz Dielectric Sensor With dc Readout Circuit in a 130-nm SiGe BiCMOS Technology." IEEE Transactions on Microwave Theory and Techniques 66, no. 9 (September 2018): 4232–41. http://dx.doi.org/10.1109/tmtt.2018.2839104.

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44

Šotner, Roman, Norbert Herencsár, Jan Jeřábek, Radek Dvořák, Aslihan Kartci, Tomáš Dostál, and Kamil Vrba. "New Double Current Controlled CFA (DCC–CFA) Based Voltage–Mode Oscillator with Independent Electronic Control of Oscillation Condition and Frequency." Journal of Electrical Engineering 64, no. 2 (March 1, 2013): 65–75. http://dx.doi.org/10.2478/jee-2013-0010.

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In this paper, a new electronically tunable quadrature oscillator (ETQO) based on two modified versions of current feedback amplifiers (CFAs), the so called double current controlled CFA (DCC-CFAs) is presented. The frequency of oscillation (FO) of the proposed voltage-mode (VM) ETQO is electronically adjustable by current gain or by varying the intrinsic resistance of the X terminal of the active element used. The condition of oscillation (CO) is adjustable by current gain independently with respect to frequency of oscillation. Simultaneous control of current gain and intrinsic resistance allows linear control of FO and provides extension of frequency tuning range. In the proposed circuit all the capacitors are grounded. The use of only grounded capacitors makes the proposed circuit ideal for integrated circuit implementation. The presented active element realized by using BiCMOS technology and the behavior of proposed circuit are discussed in details. The theoretical results are verified by SPICE simulations based on CMOS ON-Semi C5 0.5 μm and bipolar ultra high frequency transistor arrays Intersil HFA 3096 process parameters.
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45

Li, Xiao Gang, Yong Mei, Wen Gang Huang, Zheng Yuan Zhang, Jian Gen Li, and Zhi Cheng Feng. "A Monolithic MEMS Accelerometer Process." Key Engineering Materials 483 (June 2011): 70–74. http://dx.doi.org/10.4028/www.scientific.net/kem.483.70.

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A monolithic MEMS accelerometer process was established. This process successfully combines our standard BiCMOS technology and MEMS surface micromachining technique. The acceleration sensing element is a kind of comb-finger structure which is built by polysilicon surface micromachining technique. The polysilicon structure is designed to form two capacitors for acceleration sensing. The external acceleration will cause the value of two capacitors to vary in different direction. That means one reduces if the other increases. It was integrated with the signal conditioning circuit. In a single die, the active devices including vertical NPN, lateral PNP, PMOS and passive devices such as capacitors, resistors were fabricated which was followed by the steps to form the acceleration sensing structure. The experiment indicates that the fabricated circuit has the function of sensing capacitive variation and with a scale factor of 100mV/g.
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46

Barghouthi, Atheer, Marcu Hellfeld, Corrado Carta, and Frank Ellinger. "Optimization of a 61.44 GHz BiCMOS HBT integrated PLL for ultra-fast settling time." International Journal of Microwave and Wireless Technologies 4, no. 4 (February 16, 2012): 441–46. http://dx.doi.org/10.1017/s1759078712000025.

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The design of a 61.44 GHz integrated Phase-locked loop (PLL) on a 180 GHz BiCMOS technology is presented. The PLL was optimized for a very fast settling time of 4 µs as required by the system specifications. Because the receiver is using a carrier recovery circuit that can follow the slow changes of the carrier such as phase noise, the sensitivity of the bit error rate to phase noise at the receiver end is very low. As a result, to achieve the required dynamic behavior, the phase noise performance could be sacrificed and the loop bandwidth was increased until the needed settling time was achieved, while taking the suppression of the reference spurs into consideration. Capacitor multiplication was used to enable the integration of the loop filter (LF) on chip and the effect of the capacitor multiplier on the total PLL phase noise performance was quantified and evaluated. In addition, a very close matching between the measured and simulated phase noise of the system was achieved. The PLL consumes a power of 200 mW from 2 and 3 V supply voltages, while delivering a differential output power of −7 dBm, sufficient to drive the following I/Q modulator without additional amplification.
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47

Park, Jung-Dong, Shinwon Kang, and Ali M. Niknejad. "A 0.38 THz Fully Integrated Transceiver Utilizing a Quadrature Push-Push Harmonic Circuitry in SiGe BiCMOS." IEEE Journal of Solid-State Circuits 47, no. 10 (October 2012): 2344–54. http://dx.doi.org/10.1109/jssc.2012.2211156.

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48

Lambrechts, Johannes W., and Saurabh Sinha. "Estimation of signal attenuation in the 60 GHZ band with an analog BiCMOS passive filter." International Journal of Microwave and Wireless Technologies 7, no. 6 (July 17, 2014): 645–53. http://dx.doi.org/10.1017/s1759078714000956.

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Prediction of millimeter(mm)-wave radio signals can be beneficial in recreating and repeating atmospheric conditions in a controlled, laboratory environment. A path-loss model has been proposed that accounts for free-space losses, oxygen absorption, reflection and diffraction losses, and rain-rate attenuation at mm-wave frequencies. Two variable passive low-pass-integrated circuit filter structures for attenuation in the 57–64 GHz unlicensed frequency band have been proposed, designed, simulated, prototyped in a 130-nm SiGe bipolar complementary metal-oxide semiconductor process, and measured. The filters are based on the Butterworth and Chebyshev low-pass filter topologies and investigate the possibility of using the structures to perform amplitude attenuation of mm-wave frequencies over a short distance. Both filters are designed and matched for direct coupling with equivalent circuit models of dipole antennas operating in this frequency band. Full integration therefore allows prediction of atmospheric losses on an analog, real-time, basis without the requirement of down-converting (sampling) to analyze high-frequency signals through a digital architecture. On-wafer probe measurements were performed to limit parasitic interference from bonding wires and enclosed packaging.
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49

Filippov, Ivan. "Phase and Amplitude Control Integrated Circuit in 0.18 μm SiGe BiCMOS for Sub-6 GHz Phased Array Applications." Journal of Integrated Circuits and Systems 16, no. 2 (August 15, 2021): 1–6. http://dx.doi.org/10.29292/jics.v16i2.229.

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This paper presents simulation results of the C-band transmit/receive (Tx/Rx) phased-arrays integrated circuit (IC) for sub-6 GHz communication links. It is based on 0.18 μm SiGe BiCMOS technology. Phase and amplitude control IC consists of one Tx/Rx channel. Digitally controlled phase shifter allows adjusting relative phase of the output microwave signal in the range from 0 to 360 degrees with 5.625 degree step (6-bit resolution). Digitally controlled active attenuator provides the transfer ratio adjusting in the range from 0 to –31 dB with 1 dB step (5 bit resolution). Amplitude and phase correction system based on integrated temperature sensor, auxiliary 4-bit phase shifter, 4-bit attenuator and digital control unit is implemented. Correction in –60—85 °C temperature range with 5-bit resolu-tion is provided. The root mean square (rms) phase adjustment error does not exceed 1.6 degree. The rms attenuation error does not exceed 0.37 dB. The noise figure in Rx mode is below 6.5 dB. The output power in Tx mode is above 6 dBm at P1dB. The power consumption is 375 mW and 525 mW in Rx and Tx modes respectively.
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50

Tang, Tony, Bridger Wray, and Rajen Murugan. "System Co-Design Modeling Methodology of a High Speed (25Gbps) Multi-Rate 4-Channel Retimer: Simulation to Measurement Correlation." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000180–85. http://dx.doi.org/10.4071/2380-4505-2018.1.000180.

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Abstract In this paper we detail the system (viz. silicon-package-pcb) electrical co-design of a 130nm BiCMOS high-speed (25Gbps) 4-channel multi-rate retimer, packaged in a small 6-mm × 6-mm FC BGA package, with integrated advanced signal conditioning circuitries. Electrical optimization of the silicon-package-pcb over the high speed channels, to achieve desired performance, was achieved through a coupled circuit-to-electromagnetic co-design modeling and simulation methodology. Key figure of merits for system electrical performance (viz. insertion loss, return loss, crosstalk/isolation, jitter, and power supply inductance and resistance parasitics, among others) are modeled and analyzed. Laboratory measurements on a retimer are presented that validate the integrity of the modeling methodology. Good correlation between modeling methodology and laboratory measurements is achieved.
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