Relevant bibliographies by topics / Binary adder

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Binary adder'

Author: Grafiati
Published: 4 June 2021
Last updated: 12 June 2025

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Journal articles on the topic "Binary adder"

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Krasnobayev, V., S. Koshman, and D. Kovalchuk. "SYNTHESIS OF STRUCTURE OF THE ADDER BY MODULE." Системи управління, навігації та зв’язку. Збірник наукових праць 1, no. 63 (2021): 96–99. http://dx.doi.org/10.26906/sunz.2021.1.096.

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The subject of the article is the study of the structure of low-bit binary adders for an arbitrary modulus of the residual class system (RCS). The purpose of this article is to develop an algorithm for synthesizing the structure of the adder of two residuals of numbers by an arbitrary value of the RCS module, by organizing inter-bit connections between the binary digits of the adder, the combination of which determines the structure of the adder modulo. Tasks: to investigate the possibility of performing the operation of addition of two residuals in RCS based on positional binary adders; to analyze the influence of additionally introduced interdigit connections into the positional binary adder on the value of the contents of this adder; to develop an algorithm for the synthesis of an adder by an arbitrary RCS module. Research methods: methods of analysis and synthesis of computer systems, number theory, coding theory in RCS. The following results were obtained. It is shown in the work that the introduction of additional interdigit connections in a positional binary adder allows changing the contents of this adder. The rules for the introduction of these additional links are formulated, on the basis of which an algorithm for the synthesis of an adder by an arbitrary RCS modulus is obtained. Specific examples of the synthesis of structures of binary adders for various values of the RCS modules are given. Conclusions. Thus, the paper proposes an algorithm for the synthesis of an adder by an arbitrary RCS module, which is based on the use of positional binary adders, by introducing additional inter-bit connections. The application of the considered algorithm expands the functionality of positional binary adders
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ZHANG, MINGDA, and SHUGANG WEI. "HIGH-SPEED MODULAR MULTIPLIERS BASED ON A NEW BINARY SIGNED-DIGIT ADDER TREE STRUCTURE." Journal of Circuits, Systems and Computers 22, no. 06 (2013): 1350043. http://dx.doi.org/10.1142/s0218126613500436.

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Modular multiplication is a very important arithmetic operation in residue-based real-time computing systems. In this paper, we present multipliers using a modified binary tree of the modulo m signed-digit (SD) number adders where m = 2n + μ(μ = ±1, 0). To simplify the residue SD adder, new addition rules are used for generating the intermediate sum and carry with an 1-bit binary encoded number representation. By using the new encoding method, the proposed residue addition requires less hardware and shorter delay time than previous one. A modulo m multiplier can be implemented by a binary modulo m adder tree which has a depth of log 2 n. In order to introduce a binary SD adder tree with the new addition rules, two novel modulo m adders have been proposed in this paper. Finally, the evaluation apparently shows that the proposed two kinds of modulo m adders are performed more efficiency by comparing with the modulo SD adder which is mentioned in our previous work, and a new binary SD adder tree structure has been proposed.
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Poustie, A. J., K. J. Blow, A. E. Kelly, and R. J. Manning. "All-optical binary half-adder." Optics Communications 156, no. 1-3 (1998): 22–26. http://dx.doi.org/10.1016/s0030-4018(98)00349-6.

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Ericson, T. "The noncooperative binary adder channel." IEEE Transactions on Information Theory 32, no. 3 (1986): 365–74. http://dx.doi.org/10.1109/tit.1986.1057190.

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Tanaka, Yuuki, Yuuki Suzuki, and Shugang Wei. "Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation." Journal of Circuits, Systems and Computers 29, no. 09 (2019): 2050136. http://dx.doi.org/10.1142/s0218126620501364.

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Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.
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Ms. Mayuri Ingole. "Modified Low Power Binary to Excess Code Converter." International Journal of New Practices in Management and Engineering 4, no. 03 (2015): 06–10. http://dx.doi.org/10.17762/ijnpme.v4i03.38.

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Utilization of power is a major aspect in the design of integrated circuits. Since, adders are mostly employed in these circuits, we should design them effectively. Here, we propose an easy and effective method in decreasing the maximum consumption of power. Carry Select Adder is the one which is dependent on the design of two adders. We present a high performance low-power adder that is implemented. Also, here in Carry Select Adder, Binary Excess Code-1is replaced by Ripple Carry Adder. After analyzing the results, we can come to a conclusion that the architecture which is proposed will have better results in terms of consumption of power compared to conventional techniques.
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Kumar Saxena, Rakesh, Neelam Sharma, and A. K. Wadhwani. "Fast Adder Design using Redundant Binary Numbers with Reduced Chip Complexity." International Journal of Engineering and Technology 3, no. 3 (2011): 274–78. http://dx.doi.org/10.7763/ijet.2011.v3.237.

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V J, Ylaya. "Improved Design of Binary Full Adder." International Journal of Advanced Trends in Computer Science and Engineering 9, no. 3 (2020): 4113–16. http://dx.doi.org/10.30534/ijatcse/2020/239932020.

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Clur, A. W. Barker, and J. Talbot. "Binary half adder based on diffraction." Journal of Optics 22, no. 4 (1991): 193–99. http://dx.doi.org/10.1088/0150-536x/22/4/004.

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Shirazi, Behrooz, David Y. Y. Yun, and Chang N. Zhang. "RBCD: redundant binary coded decimal adder." IEE Proceedings E Computers and Digital Techniques 136, no. 2 (1989): 156. http://dx.doi.org/10.1049/ip-e.1989.0021.

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Dissertations / Theses on the topic "Binary adder"

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Zimmermann, Reto. "Binary adder architectures for cell-based VLSI and their synthesis /." Zürich, 1997. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=12480.

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Benachour, Phillip. "Trellis decoding techniques for the multiple access binary adder channel." Thesis, Lancaster University, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.314240.

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Manjuladevi, Rajendraprasad Akshay. "High-Speed Testable Radix-2 N-Bit Signed-Digit Adder." Wright State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1566226346050539.

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Franck, Helen de Souza. "Avaliação de atraso, consumo e proteção de somadores tolerantes a falhas." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2011. http://hdl.handle.net/10183/49071.

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Nos últimos anos, os sistemas integrados em silício (SOCs - Systems-on-Chip) têm se tornado menos imunes a ruído, em decorrência dos ajustes necessários na tecnologia CMOS (Complementary Metal-Oxide-Silicon) para garantir o funcionamento dos transistores com dimensões nanométricas. Dentre tais ajustes, a redução da tensão de alimentação e da tensão de limiar (threshold) tornam os SOCs mais suscetíveis a falhas transientes, principalmente aquelas provocadas pela colisão de partículas energéticas que provêm do espaço e encontram-se presentes na atmosfera terrestre. Quando uma partícula energética de alta energia colide com o dreno de um transistor que está desligado, ela perde energia e produz pares elétron-lacuna livres, resultando em uma trilha de ionização. A ionização pode gerar um pulso transiente de tensão que pode ser interpretado como uma mudança no sinal lógico. Em um circuito combinacional, o pulso pode propagar-se até ser armazenado em um elemento de memória. Tal fenômeno é denominado Single-Event Transient (SET). Como a tendência é que as dimensões dos dispositivos fabricados com tecnologia CMOS continuem reduzindo por mais alguns anos, a ocorrência de SETs em SOCs operando na superfície terrestre tende a aumentar, exigindo a adoção de técnicas de tolerância a falhas no projeto de SOCs. O presente trabalho tem por objetivo avaliar circuitos somadores tolerantes a falhas transientes encontrados na literatura. Duas arquiteturas de somadores foram escolhidas: Ripple Carry Adder (RCA) e Binary Signed Digit Adder (BSDA). O RCA foi escolhido por ser o tipo de somador de menor custo e por isso, amplamente utilizado em SOCs. Já o BSDA foi escolhido porque utiliza o sistema numérico de dígito binário com sinal (Binary Signed Digit – BSD). Por ser um sistema de representação redundante, o uso de BSD facilita a aplicação de técnicas de tolerância a falhas baseadas em redundância de informação. Os somadores protegidos avaliados foram projetados com as seguintes técnicas: Redundância Modular Tripla (Triple Modular Redundancy - TMR) e Recomputação com Entradas e Saídas Invertidas (RESI), no caso do RCA, e codificação 1 de 3 e verificação de paridade, no caso do BSDA. As 9 arquiteturas de somadores foram simuladas no nível elétrico usando o Modelo Tecnológico Preditivo (Predictive Technology Model - PTM) de 45nm e considerando quatro comprimentos de operandos: 4, 8, 16 e 32 bits. Os resultados obtidos permitiram quantificar o número de transistores, o atraso crítico e a potência média consumida por cada arquitetura protegida. Também foram realizadas campanhas de injeção de falhas, por meio de simulações no nível elétrico, para estimar o grau de proteção de cada arquitetura. Os resultados obtidos servem para guiar os projetistas de SOCs na escolha da arquitetura de somador tolerante a falhas mais adequada aos requisitos de cada projeto.<br>In the past recent years, integrated systems on a chip (Systems-on-chip - SOCs) became less immune to noise due to the adjusts in CMOS technology needed to assure the operation of nanometric transistors. Among such adjusts, the reductions in supply voltage and threshold voltage make SOSs more susceptible to transient faults, mainly those provoked by the collision of charged particles coming from the outer space that are present in the atmosphere. When a heavily energy charged particle hits the drain region of a transistor that is at the off state it produces free electron-hole pairs, resulting in an ionizing track. The ionization may generate a transient voltage pulse that can be interpreted as a change in the logic signal. In a combinational circuit, the pulse may propagate up to the primary outputs and may be captured by the output storage element. Such phenomenon is referred to as Single-Event Transient (SET). Since it is expected that transistor dimensions will continue to reduce in the next technological nodes, the occurrence of SETs at Earth surface will increase and therefore, fault tolerance techniques will become a must in the design of SOSs. The present work targets the evaluation of transient fault-tolerant adders found in the literature. Two adder architectures were chosen: the Ripple-Carry Adder (RCA) and the Binary Signed Digit Adder (BSDA). The RCA was chosen because it is the least expensive and therefore, the most used architecture for SOS design. The BSDA, in turn, was chosen because it uses the Binary Signed Digit (BSD) system. As a redundant number system, the BSD paves the way to the implementation of fault-tolerant adders using information redundancy. The evaluated fault-tolerant adders were implemented by using the following techniques: Triple Module Redundancy (TMR) and Recomputing with Inverted Inputs and Outputs (RESI), in the case of the RCA, and 1 out of 3 coding and parity verification, in the case of the BSDA. A total of 9 adder architectures were simulated at the electric-level using the Predictive Technology Model (PTM) for 45nm in four different bitwidths: 4, 8, 16 and 32. The obtained results allowed for quantifying the number of transistors, critical delay and average power consumption for each fault-tolerant architecture. Fault injection campaigns were also accomplished by means of electric-level simulations to estimate the degree of protection of each architecture. The results obtained in the present work may be used to guide SOS designers in the choice of the fault-tolerant adder architecture that is most likely to satisfy the design requirements.
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Hojný, Ondřej. "Evoluční návrh kombinačních obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2021. http://www.nusl.cz/ntk/nusl-442801.

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This diploma thesis deals with the use of Cartesian Genetic Programming (CGP) for combinational circuits design. The work addresses the issue of optimizaion of selected logic circuts, arithmetic adders and multipliers, using Cartesian Genetic Programming. The implementation of the CPG is performed in the Python programming language with the aid of NumPy, Numba and Pandas libraries. The method was tested on selected examples and the results were discussed.
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Kocina, Filip. "Moderní metody modelování a simulace elektronických obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-412585.

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Disertační práce se zabývá simulací elektronických obvodů. Popisuje metodu kapacitorové substituce (CSM) pro převod elektronických obvodů na elektrické obvody, jež mohou být následně řešeny pomocí numerických metod, zejména Moderní metodou Taylorovy řady (MTSM). Tato metoda se odlišuje automatickým výběrem řádu, půlením kroku v případě potřeby a rozsáhlou oblastí stability podle zvoleného řádu. V rámci disertační práce bylo autorem disertace vytvořeno specializované programové vybavení pro řešení obyčejných diferenciálních rovnic pomocí MTSM, s mnoha vylepšeními v algoritmech (v porovnání s TKSL/386). Tyto algoritmy zahrnují zjednodušování obecných výrazů na polynomy, paralelizaci nezávislou na integrační metodě atp. Tento software běží na linuxovém serveru, který komunikuje pomocí protokolu TCP/IP. Toto vybavení bylo úspěšně použito pro simulaci VLSI obvodů, jejichž řešení pomocí CSM bylo značně rychlejší a spotřebovávalo méně paměti než state-of-the-art SPICE.
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Lynch, Thomas Walker. "Binary adders." 1996. http://hdl.handle.net/2152/13960.

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This thesis focuses on the logical design of binary adders. It covers topics extending from cardinal numbers to carry skip optimization. The conventional adder designs are described in detail, including: carry completion, ripple carry, carry select, carry skip, conditional sum, and carry lookahead. We show that the method of parallel prefix analysis can be used to unify the conventional adder designs under one parameterized model. The parallel prefix model also produces other useful configurations, and can be used with carry operator variations that are associative. Parallel prefix adder parameters include group sizes, tree shape, and device sizes. We also introduce a general algorithm for group size optimization. Code for this algorithm is available on the World Wide Web. Finally, the thesis shows the derivation for some carry operator variations including those originally given by Majerski and Ling.<br>text
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Tzeng, Yu-Hau, and 曾于豪. "Design of High Performance Binary Signed-Digit Adder." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/59050694178419002052.

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碩士<br>國立勤益科技大學<br>電子工程系<br>100<br>Binary Signed-Digit (BSD) number representation has inherently carry-free (CF) addition. Hence, it is widely applied in design of parallel arithmetic and high performance processor. The structure of a BSD adder design is mainly composed of three blocks including binary-to-BSD conversion, BSD computing unit and BSD-to-binary conversion. In design of each block, we find that the binary-to-BSD conversion can be done in constant time. In addition, the performance of BSD-to-binary conversion almost dominates the whole performance of a BSD-based arithmetic system. In this thesis, a high performance BSD adder design is proposed to have the capability of on-line detection all single stuck-at fault and repairing in normal operation mode. The tree-structure two-rail code checker (TRC) is chosen in our self-checking and repair circuits design due to its simple and easier implementation. The BSD adder with self-repair capability can provides higher reliability. The validations and realizations of our design are based on TSMC 0.18μm process technology, and the experimental results have proved our design is valid and can effectively reduce the transistor count, carry propagation delay and power consumption.
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Su, Bo-Chyuan, and 蘇柏全. "Parallel Adder Design Based on Binary Signed-Digit Representation." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/79158682409003906822.

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碩士<br>國立勤益科技大學<br>電子工程系<br>99<br>In this thesis, we propose a completely parallel adder design based on BSD (Binary Signed-Digit) representation. The binary signed-digit number representation has inherently carry-free property. Therefore, binary signed-digit number representation is widely used to implement parallel arithmetic and high performance processor. The thesis focuses on the key issues of parallel adder design based on binary signed-digit representation. The proposed parallel adder designs can efficiently reduce the carry propagation delay. Realization and simulation are based on both TSMC 0.35um process technology and TSMC 0.18um process technology, and the experimental results have proved our proposed structure being with high performance and reliability. The structure of a BSD adder design is mainly composed of three blocks including Binary to BSD conversion, BSD Unit and BSD to binary conversion. In design of each block, efforts are focused on functional realization, schematics design, analysis, and comparison of performance. Finally, the checking circuits are partly added for achieving higher reliability. The tree-structure two-rail code checker is chosen in our design due to its simple structure and easier implementation. It is more suitable for high bit-count design than non-tree structure two-rail code checker.
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Lai, Jui-Chang, and 賴瑞昌. "Design of a Fast Signed Binary Adder with Error Detection." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/09740687812920260811.

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碩士<br>中正理工學院<br>電機工程研究所<br>87<br>Most of the cryptosystem, which implemented in software or hardware methods, need modular multiplication and modular exponentiation. In the hardware design of a good cryptosystem, the basic circuit should not include any error. The adder, which constructs the basic device of the cryptosystem, should operate fast and provide the ability of error detection. The traditional binary adder has the carry propagation delay so it is slow. The carry look-ahead adder improves the carry propagation delay but it has another disadvantage, i.e., more bits size of the circuit involves the more complexity of the circuit. It is unrealistic that very large fan-in are required by the carry look-ahead adder. One of the valid way to solve the carry propagation delay is using the signed binary digit (SBD) system. In this thesis, we propose a SBD based adder, which is fast and error detection. Base on this adder, the cryptosystem is more robust.
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Books on the topic "Binary adder"

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Zimmermann, Reto. Binary adder architectures for cell-based VLSI and their synthesis. Hartung-Gorre, 1998.

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Majerski, Stanisław. Economical and optimal carry-lookahead (CLA) units for high-speed binary adders. Institute of Computer Science, Polish Academy of Sciences, 1988.

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Catherine A, Rogers. Part I Mapping the Terrain, 2 Arbitrators, Barbers, and Taxidermists. Oxford University Press, 2014. http://dx.doi.org/10.1093/law/9780198713203.003.0003.

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This chapter discusses the debates on arbitrator regulation — more specifically, the ways in which international arbitration is over-regulated, under-regulated, less regulated than others, or not regulated at all. The issue in itself is a complex one, uniquely interwoven into the procedures and market conditions under which arbitrators are selected and appointed, therefore categorizing these procedures into an easy binary of over-regulated and under-regulated cannot suffice. In a way, the processes are both over- and under-regulated. The highly strategic nature of the selection process, combined with imperfections in the market for arbitrator services present added complications for effectively regulating the professional conduct of arbitrators. Despite these challenges, the current forms of arbitrator regulation are at least generally more effective than might be supposed in the absence of traditional forms of professional regulation.
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Book chapters on the topic "Binary adder"

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Weik, Martin H. "binary adder." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_1517.

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Weik, Martin H. "binary half-adder." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_1542.

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Renaud, N., and C. Joachim. "Binary Full-Adder in a Single Quantum System." In Architecture and Design of Molecule Logic Gates and Atom Circuits. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-33137-4_17.

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Rangaraju, H. G., U. Venugopal, K. N. Muralidhara, and K. B. Raja. "Design of Efficient Reversible Parallel Binary Adder/Subtractor." In Computer Networks and Information Technologies. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19542-6_14.

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Neuhäuser, David. "Exploring the Design Space of Signed-Binary Adder Cells." In Lecture Notes in Electrical Engineering. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-15765-8_21.

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Bhuvaneswary, N., S. Prabu, S. Karthikeyan, R. Kathirvel, and T. Saraswathi. "Low Power Reversible Parallel and Serial Binary Adder/Subtractor." In Intelligent Systems Reference Library. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-57835-0_12.

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da Rocha, Valdemar C., and Maria de Lourdes M. G. Alcoforado. "Trellis Code Construction for the 2-User Binary Adder Channel." In Telecommunications and Networking - ICT 2004. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-27824-5_18.

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Jovanović, Bojan, and Milun Jevtić. "Optimization of the Binary Adder Architectures Implemented in ASICs and FPGAs." In Soft Computing Applications. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-33941-7_27.

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Kantabutra, Vitit, Stefania Perri, and Pasquale Corsonello. "Tradeoffs in Digital Binary Adder Design: the effects of floorplanning, number of levels of metals, and supply voltage on performance and area." In Network Theory and Applications. Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3415-7_8.

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James, Rekha K., K. Poulose Jacob, and Sreela Sasi. "Reversible Binary Coded Decimal Adders using Toffoli Gates." In Lecture Notes in Electrical Engineering. Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-1-4020-8919-0_9.

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Conference papers on the topic "Binary adder"

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El-Slehdar, A. A., A. H. Fouad, and A. G. Radwan. "Memristor-based redundant binary adder." In 2014 International Conference on Engineering and Technology (ICET). IEEE, 2014. http://dx.doi.org/10.1109/icengtechnol.2014.7016820.

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Nagamani, A. N., S. Ashwin, and Vinod Kumar Agrawal. "Design of optimized reversible binary adder/subtractor and BCD adder." In 2014 International Conference on Contemporary Computing and Informatics (IC3I). IEEE, 2014. http://dx.doi.org/10.1109/ic3i.2014.7019664.

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Kharbash, F., and G. M. Chaudhry. "Reliable Binary Signed Digit Number Adder Design." In IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07). IEEE, 2007. http://dx.doi.org/10.1109/isvlsi.2007.88.

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Grad, Johannes, and James E. Stine. "A Multi-Mode Low-Energy Binary Adder." In 2006 Fortieth Asilomar Conference on Signals, Systems and Computers. IEEE, 2006. http://dx.doi.org/10.1109/acssc.2006.355130.

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Zadeh, Somayeh Hossein, Trond Ytterdal, and Snorre Aunet. "Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder." In 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE, 2019. http://dx.doi.org/10.1109/norchip.2019.8906917.

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Alcoforado, M. L. M. G., V. C. da Rocha, and G. Markarian. "Turbo block codes for the binary adder channel." In Proceedings. International Symposium on Information Theory, 2005. ISIT 2005. IEEE, 2005. http://dx.doi.org/10.1109/isit.2005.1523672.

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Baqueta, Jeferson J., Felipe S. Marranghello, Vinicius N. Possani, Augusto Neutzling, Andre I. Reis, and Renato P. Ribas. "Binary adder circuit design using emerging MIGFET devices." In 2017 18th International Symposium on Quality Electronic Design (ISQED). IEEE, 2017. http://dx.doi.org/10.1109/isqed.2017.7918304.

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Bhuvaneswari, T., Lim Way Soong, Ajay Kumar Singh, and V. C. Prasad. "Design of binary decision diagram (BDD) optical adder." In 2014 International Conference on Advances in Engineering and Technology Research (ICAETR). IEEE, 2014. http://dx.doi.org/10.1109/icaetr.2014.7012834.

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Varma, Ch Santosh, Syed Ershad Ahmed, and M. B. Srinivas. "A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter." In 2014 27th International Conference on VLSI Design. IEEE, 2014. http://dx.doi.org/10.1109/vlsid.2014.69.

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Singh, Anshul, Aman Gupta, Sreehari Veeramachaneni, and M. B. Srinivas. "A High Performance Unified BCD and Binary Adder/Subtractor." In 2009 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2009. http://dx.doi.org/10.1109/isvlsi.2009.40.

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