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Relevant bibliographies by topics / Binary to Excess-1 CONVERTER(BEC)

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Academic literature on the topic 'Binary to Excess-1 CONVERTER(BEC)'

Author: Grafiati

Published: 2 June 2025

Last updated: 22 June 2025

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Journal articles on the topic "Binary to Excess-1 CONVERTER(BEC)"

1

B.BHUPAL and S.K.SATYANARAYANA. "Design and Simulation of Low Power and Area Efficient SQRT Carry Select Adder with Modified Binary to Excess-1 Converter." International Journal of Scientific Engineering and Technology Research 3, no. 44 (2014): 8927–32. https://doi.org/10.5281/zenodo.33084.

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In the design of Integrated circuits, area occupancy and power consumption plays a vital role because of increasing necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient transistor level modification of EX-OR gate used in BEC-1 converter to significantly reduce the area and power of the CSLA. Based on this modification 4, 8, 16-bit SQRT CSLA architecture have been developed and compared with the SQRT CSLA architecture using AND, OR, INVERTER (AOI) implementation of EX-OR gate used in BEC-1 converter. The proposed SQRT CSLA is designed in 130 nm technology. The proposed design has reduced area and power as compared with the SQRT CSLA using ordinary BEC-1 converter. This work evaluates the performance of the proposed designs in terms of area and power. The results analysis shows that the proposed SQRT CSLA structure is better than the regular SQRT CSLA.

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M, Syed Mustafaa, Sathish M, Nivedha S, Magribatul Noora A K, and Safrin Sifana T. "Design of Carry Select Adder using BEC and Common Boolean Logic." Indian Journal of VLSI Design 1, no. 3 (2022): 5–9. http://dx.doi.org/10.54105/ijvlsid.c1205.031322.

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Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and power consumption in a great way we proposed a design using binary to excess 1 converter (BEC). This paper proposes an dynamic method which replaces a BEC using Common Boolean Logic.

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Syed, Mustafaa M., M. Sathish, S. Nivedha, Magribatul Noora A. K. Mohammed, and Sifana T. Safrin. "Design of Carry Select Adder using BEC and Common Boolean Logic." Indian Journal of VLSI Design (IJVLSID) 1, no. 3 (2022): 5–9. https://doi.org/10.54105/ijvlsid.C1205.031322.

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Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and power consumptionin a great way we proposed a design using binary to excess 1 converter (BEC). This paper proposes an dynamic method which replaces a BEC using Common Boolean Logic.

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4

Priya, Meshram, and Sarode Prof.Mamta. "Designing of Modified Area Efficient Square Root Carry Select Adder(SQRT CSLA)." Journal of Emerging Technologies and Innovative Research 2, no. 3 (2015): 530–33. https://doi.org/10.5281/zenodo.33087.

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In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed by using CBl. The proposed design has reduced area as well as power,but in this we study only for area with a slight increase in the delay.

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Priya, Meshram, and Sarode Prof.Mamta. "Design of Modified Area Efficient Square Root Carry Select Adder (SQRT CSLA)." International Journal of Industrial Electronics and Electrical Engineering, no. 4 (June 17, 2015): 216–19. https://doi.org/10.5281/zenodo.33098.

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In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed by using CBl. The proposed design has reduced area as well as power,but in this we study only for area with a slight increase in the delay.

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6

E.Kumar, M.Surekha, B.Jagadeesh, P.Venkata Sai Ramakrishna, N.V.S.S Sujith, and B.Manjunadha. "Design and Implementation of Area Efficient 16-bit Carry Skip Adder." international journal of engineering technology and management sciences 7, no. 2 (2023): 339–44. http://dx.doi.org/10.46647/ijetms.2023.v07i02.041.

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Adders are fundamental unit in many computer systems. One of the most efficient adder architectures in terms of delay and area is the carry-skip adder. In this paper an area efficient 16-bit carry-skip adder to achieve high speed and low area were designed. CSA is a rapid adder that is used in data processing systems to execute quick arithmetic operations. As a result, a Modified Carry Skip Adder (MCSA) is developed using a single Ripple Carry Adder (RCA) and a Binary to Excess-1 Converter (BEC) instead of twin RCAs to save size while sacrificing speed. The design is coded in VHDL and its area and delay are analyzed using Xilinx ISE 14.7. The hardware simulation is done in Xilinx Spartan 3E FPGA.

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Ravichandran, S., M. Umamaheswari, and R. Benjohnson. "Design and Development of Revolve Rescheduling Technique for Hash Event Blake Overshadowing Carry Select Adder thru Binary to Excess Converter." Asian Journal of Computer Science and Technology 5, no. 2 (2016): 5–12. http://dx.doi.org/10.51983/ajcst-2016.5.2.1771.

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Cryptographic hash events remain consumed broadly appearing in numerous concentrations mostly for the situation high-pitched hustle then safety. NIST prepared SHA- 3 struggle then the last ring-shaped contestants are BLAKE, KECCAK, SKEIN, JH THEN GROSTL. Amongst the five contestants enterprise besides planning of BLAKE remains evaluated in this manuscript. Hash event BLAKE remains the single-way cryptography which requires no key is consumed though referring and getting the communication. Inside the area of cryptography swiftness and privacy are the transactions. To achieve excessive swiftness then proficiency, Circumnavigate Reorganizing Procedure remains combined. Toward create BLAKE additional proficient, flexible calculation is swapped through Carry Select Adders (CSA) consuming Binary amongst the five contestants enterprise besides planning of BLAKE remains evaluated in this manuscript. Hash event BLAKE remains the single-way cryptography which requires no key is consumed though referring and getting the communication. Inside the area of cryptography swiftness and privacy are the transactions. To achieve excessive swiftness then proficiency, Circumnavigate Reorganizing Procedure remains combined. Toward create BLAKE additional proficient, flexible calculation is swapped through Carry Select Adders (CSA) consuming Binary to Excess Converter (BEC). The surviving then future design of BLAKE is invented consuming CSA while altered BLAKE is intended consuming CSA through BEC. Therefore, the range and capacity devoted in future technique is fewer evaluated thru surviving techniques. BLAKE-32, 64 remain implied in VHDL language then replicated in Modalism. Range and Capacity consequences remain exposed here Xilinx ISE simulant.

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Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Design of Low Power, Area-Efficient Carry Select Adder." International Journal of Engineering Research & Technology 2, no. 10 (2013): 3582–86. https://doi.org/10.5281/zenodo.32569.

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Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is designed by using single Ripple Carry Adder(RCA) and Binary to Excess-1 Converter (BEC) instead of dual RCAs in order to reduce the area and power consumption with small speed penalty. CSA and MCSA structures are designed for 8-bit, 16-bit, 32- bit and 64-bit. Result analysis shows that MCSA is better than CSA.

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Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Design of Low Power, Area-Efficient Carry Select Adder." International Journal of Engineering Research & Technology 2, no. 10 (2013): 3582–86. https://doi.org/10.5281/zenodo.33081.

Full text

Abstract:

Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is designed by using single Ripple Carry Adder(RCA) and Binary to Excess-1 Converter (BEC) instead of dual RCAs in order to reduce the area and power consumption with small speed penalty. CSA and MCSA structures are designed for 8-bit, 16-bit, 32- bit and 64-bit. Result analysis shows that MCSA is better than CSA.

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10

A., Mounika, and Srinivasa Reddy K. "Designing and Performance Evaluation of Carry Select Adder." International Journal of VLSI System Design and Communication systems 3, no. 5 (2015): 0754–57. https://doi.org/10.5281/zenodo.48670.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSA) is one of the fastest adder in processor architectures. This paper presents a modified carry select adder(CSA) that operates at low power and proves more area and delay efficient. Validation of the logic is done through extensive simulations for measuring the power and delay. Simple and efficient gate level modification is used in order to reduce the area, delay and power of CSA.The result analysis shows that the proposed structure(CSA CBL) is better than the conventional CSA and CSA with BEC. 

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Book chapters on the topic "Binary to Excess-1 CONVERTER(BEC)"

1

Lyn, Poh Yuin, Nor Azlin Ghazali, Mohamed Fauzi Packeer Mohamed, and Muhammad Firdaus Akbar. "Design of Low-Power and Area-Efficient Square Root Carry Select Adder Using Binary to Excess-1 Converter (BEC)." In Proceedings of the 12th International Conference on Robotics, Vision, Signal Processing and Power Applications. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-99-9005-4_18.

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Arunakumari, S., K. Rajasekahr, S. Sunithamani, and D. Suresh Kumar. "Carry Select Adder Using Binary Excess-1 Converter and Ripple Carry Adder." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2308-1_30.

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Srividhya, G., T. Sivasakthi, R. Srivarshini, P. Varshaa, and S. Vijayalakshmi. "Enhanced and Efficient Carry Select Adder with Minimal Delay." In Advances in Parallel Computing. IOS Press, 2021. http://dx.doi.org/10.3233/apc210102.

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In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improved model of Carry Select Adder has been designed that uses Binary to Excess – 1 Converter. Instead of using multiple blocks of Ripple Carry Adders (RCAs), it is efficient and effective if one of the blocks is replaced with Binary to Excess – 1 Converter. As a result, we can achieve a high speed adder with minimal delay, minimal power, and reduced area.

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Conference papers on the topic "Binary to Excess-1 CONVERTER(BEC)"

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Ram, G. Challa, M. Venkata Subbarao, D. Ramesh Varma, and M. Prema Kumar. "Delay Enhancement of Wallace Tree Multiplier with Binary to Excess-1 Converter." In 2023 5th International Conference on Smart Systems and Inventive Technology (ICSSIT). IEEE, 2023. http://dx.doi.org/10.1109/icssit55814.2023.10061043.

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Raavi, Srinith, and T. Satyanarayana. "Implementation of High-Speed Hybrid Carry Select Adder using Binary to Excess-1 Converter." In 2022 International Conference on Augmented Intelligence and Sustainable Systems (ICAISS). IEEE, 2022. http://dx.doi.org/10.1109/icaiss55157.2022.10010750.

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Munawar, Muteen, Talha Khan, Muhammad Rehman, et al. "Low Power and High Speed Dadda Multiplier using Carry Select Adder with Binary to Excess-1 Converter." In 2020 International Conference on Emerging Trends in Smart Technologies (ICETST). IEEE, 2020. http://dx.doi.org/10.1109/icetst49965.2020.9080739.

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Kesava, R. Bala Sai, B. Lingeswara Rao, K. Bala Sindhuri, and N. Udaya Kumar. "Low power and area efficient Wallace tree multiplier using carry select adder with binary to excess-1 converter." In 2016 Conference on Advances in Signal Processing (CASP). IEEE, 2016. http://dx.doi.org/10.1109/casp.2016.7746174.

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Petrov, A., N. Belayouni, M. Belouahchia, L. Xin, Y. Fan, and A. Noufal. "Deep Learning Algorithms Based Approach for AI Derived Borehole Images Automatic Interpretation." In ADIPEC. SPE, 2023. http://dx.doi.org/10.2118/216488-ms.

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Abstract Borehole image interpretation aims to evaluate the dip, azimuth and aperture of natural fractures and mechanical features detected along the well such as, drilling induced fractures, breakouts, etc. and to classify them based on their characteristics. Traditionally, the rule-based approaches are used for handling this task, which use manually engineered features as image representation and give a set of rules to infer the understanding of fractures and breakouts structural parameters from borehole images. However, traditional approaches can only handle ‘simple-and-easy’ cases in borehole image interpretation. Digging geological knowledge from data to gain a more comprehensive understanding of structural features remains un-solved problem. We introduce a dip picking approach based on deep neural networks. Compared to conventional data-driven approaches, like SVM or AdaBoost, deep models can better handle the complex borehole image interpretation. This is because: Deep networks generalize well even while being over-parameterized, un-regularized and fitting the training data to zero error, while traditional machine learning approaches suffer from severe overfitting.Deep networks allow computational models that are composed of multiple processing layers to learn representations of data with multiple levels of abstraction, thus they can best capture the high-level semantics, which should be the key for borehole image interpretation. Generally, we convert the single-step dip picking from borehole images into a two-stage approach, including scene parsing and interpretation. In the first stage, rather than directly using exiting deep models for scene parsing (e.g., U-Net or HR-Net), we design a novel multi-branch parsing model to better handle the data imbalance problem in borehole data. Our core idea is to use a shared backbone network for common feature extraction, and task-specific branches for specific classes, such as stylolite, natural fractures, drilling induced fractures and breakout. Moreover, a reverse attention module is used for information propagation across different branches. In this way, the network parameters in each branch can be trained with different number of data, and importantly, the useful information from other branches can be easily utilized through reverse attention without extra manual labels. In the second stage, we use traditional curve fitting techniques for achieving an automatic dip picking. Our model is trained iteratively using a binary mask as a ground truth for each image, with "0" representing background and "1" pixels belonging to the class, using a loss function that penalizes the mismatch between the binary mask and the map produced by the CNN. At the end of training, the CNN module infers the best probability for each pixel in the image. A class-specific threshold is defined such that pixels above the thresholds are assigned to the class, while pixels below the thresholds are assigned to the background. We used the Binary Cross Entropy (BCE) loss to optimize our model such that it can best distill the geological knowledge from data. Our novelty lies in a novel multi-branch deep model with reverse attention module. This is the first time to mine the geological knowledge using a task-specific deep branches and employ the reverse attention for information communication. Once the backbone is trained, the parameters of task-specific branches can be updated with limited data without suffering from the data imbalance issue. Such network architecture has not been explored before in borehole images interpretation. Comprehensive experiments and visualizations confirm that our model can achieve state-of-the-art performance. Specifically, according to the AUC score, our model achieves the average of 81.7% on our household dataset (11 features and 6 wells), greatly outperforming U-Net by 8.4% and HR-Net by 7.9%.

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