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Journal articles on the topic 'Bit CSLA'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

You, Yuan, Tang, and Qiao. "An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell." Electronics 8, no. 10 (2019): 1129. http://dx.doi.org/10.3390/electronics8101129.

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In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed C

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2

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Analysis of Low Power, Area- Efficient and High Speed Fast Adder." International Journal of Advanced Research in Computer and Communication Engineering 2, no. 9 (2013): 3705–10. https://doi.org/10.5281/zenodo.32567.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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3

J.Ponmalar, T.R.Sureshkumar, and T.Kowsalya. "Low Power, Area- Efficient and High Speed Fast Adder for Processing Element." International Journal of Innovative Research in Science, Engineering and Technology 4, no. 6 (2015): 946–54. https://doi.org/10.5281/zenodo.33096.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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4

Singh, Gagandeep, and Chakshu Goel. "Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate." Advances in Electronics 2014 (September 22, 2014): 1–6. http://dx.doi.org/10.1155/2014/564613.

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In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA.

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Balasubramanian, Padmanabhan, and Nikos Mastorakis. "Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions." Electronics 7, no. 12 (2018): 369. http://dx.doi.org/10.3390/electronics7120369.

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Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing bi

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Aditya, Srinivas, and Ramesh K.B. "Design and Implementation of an Optimized ALU using a Square Root Carry Select Adder." Journal of Optoelectronics and Communication 6, no. 3 (2024): 18–26. https://doi.org/10.5281/zenodo.12720733.

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<em>Arithmetic logic units (ALUs) are strong combinational circuits in digital computers that carry out arithmetic and logical operations. The Parallel Adder embedded within the Arithmetic Logic Unit (ALU) holds significance, yet the time-consuming nature of carry propagation (CP) during addition demands consideration. To cater to the requirements of low-power and area-efficient applications, the paper suggests an ALU design that integrates a modified Square Root Carry Select Adder (SQRT CSLA). Additionally, for applications necessitating enhanced speed, an alternative ALU design is introduced

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A., Nithya, G. Priyanka A., Ajitha B., Gracia Nirmala Rani D., and Rajaram S. "FPGA Implementation of Low Power and Area Efficient Carry Select Adder." International Journal of Enhanced Research in Science Technology & Engineering 3, no. 7 (2014): 321–27. https://doi.org/10.5281/zenodo.33237.

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In this paper, we have proposed a modified carry select adder which is known as fastest adders that can perform arithmetic operations in Digital signal processors. Modification in the gate level of the Square root Carry Select Adder (SQRT CSLA) structure results in the reduction of area and power of the CSLA structure which offers a simple and efficient function. Depending upon the Regular SQRT CSLA, we have modified the structure of the adders. The proposed design for 128-bit modified CSLA has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the del

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8

S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster spee

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9

PinnikaVenkateswarlu and Kalpana Ragutla. "An Efficient SQRT Architecture of Carry Select Adder Design by HA and Common Boolean Logic." SSRG International Journal of Electronics and Communication Engineering 1, no. 8 (2014): 36–41. https://doi.org/10.5281/zenodo.33082.

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As we are aware that carry select adder is the fastest one amongdata processing element, on the other hand due to having pairs of ripple carry adder structure traditional carry select adder consumes more area. So proposed scheme is to developa low power and low area half adder based (CSLA) using simple using common Boolean logic (CBL), where it employs one half adders to perform the summation operation for the common Boolean logic (CBL) and carry zero respectively. Half adder and CBL have to be designed where half adder requires one XOR gate, one AND gate where CBL requires only one NOT as wel

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10

B.BHUPAL and S.K.SATYANARAYANA. "Design and Simulation of Low Power and Area Efficient SQRT Carry Select Adder with Modified Binary to Excess-1 Converter." International Journal of Scientific Engineering and Technology Research 3, no. 44 (2014): 8927–32. https://doi.org/10.5281/zenodo.33084.

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In the design of Integrated circuits, area occupancy and power consumption plays a vital role because of increasing necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient transistor level modification of EX-OR gate used in BEC-1 converter to significantly reduce the area and power of the CSLA. Based on this modification 4, 8, 16-bit SQRT CSLA a

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Dhandapani, Vaithiyanathan. "An efficient architecture for carry select adder." World Journal of Engineering 14, no. 3 (2017): 249–54. http://dx.doi.org/10.1108/wje-08-2016-0043.

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Purpose Adders play a vital role in almost all digital designs, as all four arithmetic operations can be confined within addition. Hence, area and power optimization of the adders will result in overall circuit optimization. Being the fastest adder, the carry select adder (CSLA) gains higher importance among the different adder styles. However, it suffers from the drawback of increased power and area. The implementation of CSLA in digital circuits requires lots of study for optimization. Hence, to overcome this problem, various improvements were made to the CSLA structure to reduce area and, c

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Yogayata, Shrivastava, Verma Tarun, and Jain Rita. "Design and Implementation of Low Power High Speed 32-Bit HCSA." International Journal of VLSI and Embedded Systems 5 (April 17, 2014): 893–98. https://doi.org/10.5281/zenodo.33236.

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In the design of carry select adder, the requirement of area, speed and power consumption is of prime importance. Power dissipation is one of the most important design objectives in integrated circuits, after speed. Carry select adder (CSLA) is one of the fast adder used to perform fast arithmetic operations as we select the carry beforehand and calculate the sum output for both the carry conditions i.e. for Cin=1 or Cin=0. The most fundamental arithmetic operations in any ALU is addition. It has been ranked the most extensively used operation among a set of real-time digital signal processing

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Tariq Hussein, Fatima, and Fatemah K. AL-Assfor. "Efficient Implementation of Fixed-Point MAC and Multimode MAC Blocks Based on Vedic Mathematic." Iraqi Journal for Electrical and Electronic Engineering 21, no. 2 (2025): 88–98. https://doi.org/10.37917/ijeee.21.2.9.

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Recently, the need for high speed multiply-accumulate (MAC) operations is crucial in numerous systems like 5G, deep learning, in addition to many digital signal processing (DSP) applications. This work offers an improved MAC (I-MAC) block of different bit-size based on Vedic Mathematic and employing a hybrid adder consists of an enhanced Brent-Kung with a carry-select adder (HBK-CSLA) to achieve the sum of products for the MAC. The work is then, developed to design a new multimode fixed-point (FX-Pt) MAC block by exploiting the proposed design of the I-MAC architecture. The proposed multimode

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Kamna, nayak, and Patra K.Pitambar. "Study of High Speed 32-Bit Data Processing Using CSLA." Association for International Journal in Computer Science & Electronics 4, no. 3 (2015): 1–9. https://doi.org/10.5281/zenodo.33244.

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Modern applications demand extremely low power and fast speed in computer architectures for battery-operated devices like Laptop and others. In this work, the main focus is on the low power consumption and provides high speed to the processors. Low-power and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The selection behind the carry select adder is that it is very much efficient in terms of delay. The main focus in this work is to improve the speed of the 32-bit processor and in this case

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15

Priya, Meshram, Mahendra Mithilesh, and Jawarkar Parag. "Designed Implementation of Modified Area Efficient Enhanced Square Root Carry Select Adder." International Journal for Research in Emerging Science and Technology 2, no. 5 (2015): 96–99. https://doi.org/10.5281/zenodo.33092.

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In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In this paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) with BEC is proposed. After logic simplification and sharing partial circuit, only one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation are needed. Based o

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16

Goodman, Joshua T. "A bit of progress in language modeling." Computer Speech & Language 15, no. 4 (2001): 403–34. http://dx.doi.org/10.1006/csla.2001.0174.

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Malti, Aryanan, and Singh Chauhan Jaikaran. "Design Area-Efficient and high speed 32bit CSLA." International Journal of advancement in electronics and computer engineering 4, no. 8 (2015): 555–59. https://doi.org/10.5281/zenodo.45401.

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Modern applications demand extremely less area budgets and enhanced speed in computer architectures for battery-operated devices like Laptop and others. In this thesis, the main focus is on the area and provides high speed to the processors. Less area and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The main focus in this work is to improve the speed of the 32-bit processor and in this case the carry select adder is the better choice. The second concern in the design of this carry select a

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18

Suguna, T., and M. Janaki Rani. "Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications." International Journal of Interactive Mobile Technologies (iJIM) 14, no. 05 (2020): 73. http://dx.doi.org/10.3991/ijim.v14i05.13343.

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In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL

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19

Gopi, M., and GBS R. Naidu. "128 bit Unsigned Multiplier Design and Implementation Using an Efficient SQRT-CSLA." International Journal of Hybrid Information Technology 8, no. 10 (2015): 197–204. http://dx.doi.org/10.14257/ijhit.2015.8.10.18.

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Malti, Aryayan, and Singh Chauhan Jaikaran. "Efficient Method for Area-Efficient 32bit CSLA." International Journal of Emerging Technology and Advanced Engineering 6, no. 2 (2016): 81–85. https://doi.org/10.5281/zenodo.46811.

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Modern applications demand extremely less area budgets and enhanced speed in computer architectures for battery-operated devices like Laptop and others. In this thesis, the main focus is on the area and provides high speed to the processors. Less area and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The main focus in this work is to improve the speed of the 32-bit processor and in this case the carry select adder is the better choice. The second concern in the design of this carry select a

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21

Balasubramanian, Padmanabhan, and Nikos E. Mastorakis. "High-Speed and Energy-Efficient Carry Look-Ahead Adder." Journal of Low Power Electronics and Applications 12, no. 3 (2022): 46. http://dx.doi.org/10.3390/jlpea12030046.

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The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry t

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Raman, Anjali, Chirukoti Anusha, Sucharitha C, Shaik Mohammed Rafi, and Fairooz SK. "Design of A Low Power 16- Bit CSLA Using Binary To Excess-1 Converter." International Journal of VLSI and Signal Processing 7, no. 2 (2020): 11–13. http://dx.doi.org/10.14445/23942584/ijvsp-v7i2p103.

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Mendez, Tanya, Subramanya G. Nayak, Vasanth Kumar P., Vijay S. R., and Vishnumurthy Kedlaya K. "Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending." Electronics 11, no. 15 (2022): 2461. http://dx.doi.org/10.3390/electronics11152461.

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The hardware implementation of error-tolerant adders using the paradigm of approximate computing has considerably influenced the performance metrics, especially in applications that can compromise accuracy. The foundation for approximate processing is the inclusion of errors in the design to enhance the effectiveness and reduce the complexity. This work presents three base adders using the novel concept of error tolerance in digital VLSI design. The research is extended to construct nine variants of power and delay-efficient 16 and 32-bit error-tolerant carry select adders (CSLA). To attain op

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Tariq Hussein, Fatima, and Fatemah K. AL-Assfor. "Design Efficient Vedic-Multiplier for Floating-Point MAC Module." Iraqi Journal for Electrical and Electronic Engineering 20, no. 2 (2024): 182–89. http://dx.doi.org/10.37917/ijeee.20.2.15.

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Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing (DSP) applications, such as image convolution and filters, especially when performed on floating-point numbers to achieve high-level of accuracy. The performance of MAC module highly relies upon the performance of the multiplier utilized. This work offers a distinctive and efficient floating-point Vedic multiplier (VM) called adjusted-VM (AVM) to be utilized in MAC module to meet modern DSP demands. The proposed AVM is based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra) approach and utilizes an enhanced desi

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Balasubramanian, Padmanabhan, Douglas Maskell, and Nikos Mastorakis. "Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic." Electronics 7, no. 10 (2018): 243. http://dx.doi.org/10.3390/electronics7100243.

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Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-pha

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D.Gandhe, Sumeet, and Venkatesh Giripunje. "FPGA Implementation of Area Efficient and Delay Optimized 32-Bit SQRT CSLA with First Addition Logic." International Journal of Computer Applications 95, no. 22 (2014): 43–49. http://dx.doi.org/10.5120/16730-7024.

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Venkata Sudhakar, Chowdam, Suresh Babu Potladurty, and Prasad Reddy Karipireddy. "Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 2 (2025): 398. https://doi.org/10.11591/ijres.v14.i2.pp398-411.

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<p>The multiplier is an essential component in real-time applications. Even though approximation arithmetic affects output accuracy in multipliers, it offers a realistic avenue to constructing power area and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this paper, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HA) and full adders (A-FA), which are strategically placed to add partial products at the most significant b

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Kumar, Shanigarapu, and Kalagadda Bikshalu. "FPGA Implementation of Adaptive Absolute SCORE Algorithm for Cognitive Radio Spectrum Sensing with WTM and LFA." International Journal of Intelligent Engineering and Systems 14, no. 1 (2021): 1–11. http://dx.doi.org/10.22266/ijies2021.0228.01.

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Cognitive Radio (CR) is generally a wireless communication system that has the ability to improve the network’s system-capacity. Since, the white space or temporally unused spectrum are used to enhance the systemcapacity and the important operation involved in the cognition cycle is spectrum sensing. This spectrum sensing supports the Cognitive Radio users to adjust with the environment by identifying the white/vacant spaces without creating any interference to the primary user communication. The traditional filters such as Finite Impulse Response (FIR) filters and median filters used in the s

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Anitha, M., J. Princy Joice, and Rexlin Sheeba.I. "A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (2015): 173. http://dx.doi.org/10.11591/ijres.v4.i3.pp173-177.

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Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to r

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Mohan, Shoba, and Nakkeeran Rangaswamy. "An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic." Electronics ETF 21, no. 1 (2017): 38. http://dx.doi.org/10.7251/els1721038m.

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In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation withi one clock cycle. The existing hierarchical multipliers occupy more area and suffer from accumulation delay of base multiplier output bits. These issues can be addressed by incorporating carry select adder based addition and the multiplier implementation using full swing GDI logic. The basic computation blocks involved in the multiplier are AND gate a

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Akbar, Muhammad Ali, Bo Wang, and Amine Bermak. "A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization." Electronics 10, no. 15 (2021): 1791. http://dx.doi.org/10.3390/electronics10151791.

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Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduce

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S., Sandeep, and Kiran V. "SYNTHESIS AND FPGA VALIDATION OF PARALLEL PREFIX ADDERS." International Journal of Advanced Research 10, no. 10 (2022): 708–17. http://dx.doi.org/10.21474/ijar01/15539.

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In this work, the design implementation, functionality testing, design synthesis and bitstream generation of various n-bit adder architecture of RCA, CLA, CSkA and KSA. And addresses various forms of adders which include Ripple-carry (RCA), Carry-lookahead (CLA), Carry-skip (CSkA), and Kogge-stone (KSA) adders. Certain design restrictions for digital VLSI circuits, such speed and area, can be satisfied using these adders. All the mentioned adder are designed using Verilog HDL, implemented the same on Xilinx Vivado 2018.2, functionality test is carried out by writing testbench, bitstream genera

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Chi, Xu, Maureen A. Sartor, Sanghoon Lee, et al. "Universal concept signature analysis: genome-wide quantification of new biological and pathological functions of genes and pathways." Briefings in Bioinformatics 21, no. 5 (2019): 1717–32. http://dx.doi.org/10.1093/bib/bbz093.

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Abstract Identifying new gene functions and pathways underlying diseases and biological processes are major challenges in genomics research. Particularly, most methods for interpreting the pathways characteristic of an experimental gene list defined by genomic data are limited by their dependence on assessing the overlapping genes or their interactome topology, which cannot account for the variety of functional relations. This is particularly problematic for pathway discovery from single-cell genomics with low gene coverage or interpreting complex pathway changes such as during change of cell

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Kim, Joo-Yeon, Ho-Myoung An, Myung-Shik Lee, Byung-Cheul Kim, and Kwang-Yell Seo. "Investigation for Multi-bit per Cell on the CSL-NOR Type SONOS Flash Memories." Journal of the Korean Institute of Electrical and Electronic Material Engineers 18, no. 3 (2005): 193–98. http://dx.doi.org/10.4313/jkem.2005.18.3.193.

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You, Lingchong, and Eriko Takano. "Synthetic Biology: Reports from CSHA 2016 and More." Biotechnology Journal 13, no. 5 (2018): 1800160. http://dx.doi.org/10.1002/biot.201800160.

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Jayakrishna, P., P. Sravani, R. Sakshitha Reddy, and S. Ashritha. "Design of High-Speed Area-Efficient VLSI Architecture of 32-Bit Three-Operand Binary Adder." International Journal for Research in Applied Science and Engineering Technology 11, no. 6 (2023): 1353–61. http://dx.doi.org/10.22214/ijraset.2023.53550.

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Abstract: Adders are one of the most widely used digital components in digital integrated circuit design. With the advances in technology, the design that offers either high speed, low power consumption, less area, or a combination of them is designed. There are various processes performed by the digital circuits among which arithmetic operations are prominent. Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry save adder (CS3A) is the widely used technique to perform the thre

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徐, 明毅. "Research on Instruction Set Architecture of 40-Bit Processor." Computer Science and Application 09, no. 09 (2019): 1667–82. http://dx.doi.org/10.12677/csa.2019.99186.

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叶, 彬. "Multi Bit Mapping Hiding Algorithm Based on MP3 Huffman Coding." Computer Science and Application 08, no. 05 (2018): 763–73. http://dx.doi.org/10.12677/csa.2018.85085.

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黄, 晶晶. "Bit-Level Color Digital Image Encryption Algorithm Based on Lorenz Chaotic System." Computer Science and Application 06, no. 09 (2016): 565–72. http://dx.doi.org/10.12677/csa.2016.69070.

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黎, 桠娟. "A Novel Bit-Level Image Encryption Algorithm Based on Improved 1D Chaotic Maps." Computer Science and Application 08, no. 02 (2018): 139–53. http://dx.doi.org/10.12677/csa.2018.82018.

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黎, 桠娟. "A Novel Hyper-Chaos-Based Colorimage Encryption Algorithm Using Bit-Level Permutation and Diffusion." Computer Science and Application 08, no. 09 (2018): 1382–95. http://dx.doi.org/10.12677/csa.2018.89150.

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王, 黎明. "Analysis of LoRa Transmission Distance and Data Test in Low Bit Rate Spread Spectrum Communication." Computer Science and Application 10, no. 08 (2020): 1480–89. http://dx.doi.org/10.12677/csa.2020.108155.

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Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." International Daily journal, Discovery Publication 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.32686.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each

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Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." Discovery The International Daily journal 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.33104.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design.High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each s

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汤, 宇晗. "A Color Image Encryption Algorithm Based on Dynamic Joseph Traversal and Crossing Bit-Plane Scrambling-Diffusion." Computer Science and Application 13, no. 04 (2023): 720–36. http://dx.doi.org/10.12677/csa.2023.134071.

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Fernstål, Lotta. "A Bit Arabic: Pseudo-Arabic Inscriptions on Viking Age Weights in Sweden and Expressions of Self-image." Current Swedish Archaeology 16, no. 1 (2021): 61–71. http://dx.doi.org/10.37718/csa.2008.04.

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There are many Viking Age weights in Scandinavia, and not least in Swedcn. A few of the sphrrical weights with flat poles, which were used for weighing silver in trading situations, display so-called pseudo-Arabic inscriptions, i.e. writing which resembles Arabic but which is mostly illegible. Why did some people put Arabic-like writing on their weights, and what did they hope to achieve by this? These questions are discussed together with positive aspects of trade, interaction and encounters with foreigners, visual aspects of weights and weighing, as well as personal choices in the presentati

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NGUYEN, MINH HONG, YOSHIHIRO OJIMA, and MASAHITO TAYA. "Enhanced Colonization of rpoS-Deficient Escherichia coli Cells on Solid Surfaces by Reinforced csgA Gene Expression." Biocontrol Science 19, no. 3 (2014): 147–50. http://dx.doi.org/10.4265/bio.19.147.

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赵, 青杰. "Network Intrusion Detection Model Based on Bat Optimization Algorithm." Computer Science and Application 08, no. 11 (2018): 1650–56. http://dx.doi.org/10.12677/csa.2018.811181.

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Nellore, Kapileswar, Vijayasanthi Palepu, Mohan Radha Devi Palepu, and Kumar Chenchela Vijay. "IMPROVING THE LIFESPAN OF WIRELESS SENSOR NETWORKS VIA EFFICIENT CARRIER SENSING SCHEME-CSMA/SDF." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 4 (2016): 723–32. https://doi.org/10.5281/zenodo.50383.

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Wireless Sensor Networks (WSNs)  refers to a group of spatially dispersed and dedicated sensors for monitoring and recording the physical conditions of the environment like temperature, sound, pollution levels, humidity, etc. WSNs are deployed where manual intervention and wired infrastructure installation is not feasible. Lifetime of WSNs is of major issue. Energy efficient WSNs are to be deployed to improve the network lifespan instead of replacing nodes frequently which is of high cost. In this paper, we propose CSMA/Shortest Data First (SDF) an energy efficient MAC protocol, to increa

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Feng, Xinglong, Yuzhong Zhang, Ang Gao, and Qiao Hu. "Research on AUV Multi-Node Networking Communication Based on Underwater Electric Field CSMA/CA Channel." Biomimetics 9, no. 11 (2024): 653. http://dx.doi.org/10.3390/biomimetics9110653.

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To address the issues of high attenuation, weak reception signal, and channel blockage in the current electric field communication of underwater robots, research on autonomous underwater vehicle (AUV) multi-node networking communication based on underwater electric field Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) channel was conducted. This article, first through simulation, finds that the Optimized Link State Routing (OLSR) protocol has a smaller routing packet delay time and higher reliability compared to the Ad Hoc On-Demand Distance Vector (AODV) protocol on underwate

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