Academic literature on the topic 'Bit Paralell'
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Journal articles on the topic "Bit Paralell"
Yun Sik Lee and P. M. Maurer. "Bit-parallel multidelay simulation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 15, no. 12 (1996): 1547–54. http://dx.doi.org/10.1109/43.552088.
Full textQu, Pei-Yao, Guang-Ming Tang, Jia-Hong Yang, Xiao-Chun Ye, Dong-Rui Fan, Zhi-Min Zhang, and Ning-Hui Sun. "Design of an 8-bit Bit-Parallel RSFQ Microprocessor." IEEE Transactions on Applied Superconductivity 30, no. 7 (October 2020): 1–6. http://dx.doi.org/10.1109/tasc.2020.3017527.
Full textWu, Xiaofu, Chunming Zhao, and Xiaohu You. "Parallel Weighted Bit-Flipping Decoding." IEEE Communications Letters 11, no. 8 (August 2007): 671–73. http://dx.doi.org/10.1109/lcomm.2007.070269.
Full textLi, Pu, Kunying Li, Xiaomin Guo, Yanqiang Guo, Yiming Liu, Bingjie Xu, Adonis Bogris, K. Alan Shore, and Yuncai Wang. "Parallel optical random bit generator." Optics Letters 44, no. 10 (May 9, 2019): 2446. http://dx.doi.org/10.1364/ol.44.002446.
Full textNorth, Richard C., and Walter H. Ku. "β-bit serial/parallel multipliers." Journal of VLSI signal processing systems for signal, image and video technology 2, no. 4 (May 1991): 219–33. http://dx.doi.org/10.1007/bf00925467.
Full textCrook, David, and John Fulcher. "A Comparison of Bit Serial and Bit Parallel DCT Designs." VLSI Design 3, no. 1 (January 1, 1995): 59–65. http://dx.doi.org/10.1155/1995/30583.
Full textKaur, Amandeep, Deepak Mishra, and Mukul Sarkar. "A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 1 (January 2019): 248–52. http://dx.doi.org/10.1109/tvlsi.2018.2871341.
Full textLO‡, HAO-YUNG, and FANG HSU. "A combinational word-parallel and bit-parallel associative processor." International Journal of Electronics 62, no. 4 (April 1987): 589–98. http://dx.doi.org/10.1080/00207218708921010.
Full textScherson, I. D., D. A. Kramer, and B. D. Alleyne. "Bit-parallel arithmetic in a massively-parallel associative processor." IEEE Transactions on Computers 41, no. 10 (1992): 1201–10. http://dx.doi.org/10.1109/12.166599.
Full textMansour, M. M. "A Parallel Pruned Bit-Reversal Interleaver." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 8 (August 2009): 1147–51. http://dx.doi.org/10.1109/tvlsi.2008.2008831.
Full textDissertations / Theses on the topic "Bit Paralell"
Bhardwaj, Divya Anshu. "Inverse Discrete Cosine Transform by Bit Parallel Implementation and Power Comparision." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2447.
Full textThe goal of this project was to implement and compare Invere Discrete Cosine Transform using three methods i.e. by bit parallel, digit serial and bit serial. This application describes a one dimensional Discrete Cosine Transform by bit prallel method and has been implemented by 0.35 ìm technology. When implementing a design, there are several considerations like word length etc. were taken into account. The code was implemented using WHDL and some of the calculations were done in MATLAB. The VHDL code was the synthesized using Design Analyzer of Synopsis; power was calculated and the results were compared.
Wei, Lan. "Implementation of Pipelined Bit-parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1943.
Full textBit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis. The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.
Vasata, Darlon. "Ferramenta de programação e processamento para execução de aplicações com grandes quantidades de dados em ambientes distribuídos." Universidade de São Paulo, 2018. http://www.teses.usp.br/teses/disponiveis/3/3141/tde-14122018-074952/.
Full textThe topic involving the processing of large amounts of data is widely discussed subject currently, about its challenges and applicability. This work proposes a programming tool for development and an execution environment for applications with large amounts of data. The use of the tool aims to achieve better performance of applications in this scenario, exploring the use of physical resources such as multiple lines of execution in multi-core processors and distributed programming, which uses multiple computers interconnected by a communication network, so that they operate jointly in the same application, dividing such processing among such machines. The proposed tool consists of the use of programming blocks, so that these blocks are composed of tasks, and the blocks are executed using the producer consumer model, following an execution flow. The use of the tool allows the division of tasks between the machines to be transparent to the user. With the tool, several functionalities can be used, such as cycles in the execution flow or task advancing using the strategy of speculative processing. The results were compared with two other frameworks, Hadoop and Spark. These results indicate that the use of the tool provides an increase in the performance of the applications, mostly when executed in homogeneous clusters.
Cojocaru, Christian Carleton University Dissertation Engineering Electronics. "Computational RAM: implementation and bit-parallel architecture." Ottawa, 1995.
Find full textÅslund, Anders. "Power Estimation of High Speed Bit-Parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2390.
Full textFast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared.
Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughput does not reach as high as the maximal throughput of the Kogge-Stone parallel prefix adder.
Bolotski, Michael 1965. "Abacus--a reconfigurable bit-parallel architecture for early vision." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/10638.
Full textIncludes bibliographical references (p. 123-126).
by Michael Bolotski.
Ph.D.
Bolotski, Michael. "Distributed bit-parallel architecture and algorithms for early vision." Thesis, University of British Columbia, 1990. http://hdl.handle.net/2429/29462.
Full textApplied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
Le, Chin Aik. "An 8-bit inner product multiplier by parallel pipeline algorithm." Ohio : Ohio University, 1988. http://www.ohiolink.edu/etd/view.cgi?ohiou1182863777.
Full textRising, Barry John Paul. "Hardware architectures for stochastic bit-stream neural networks : design and implementation." Thesis, Royal Holloway, University of London, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.326219.
Full textShah, Milap. "Parallel Aes diffusion inter block diffusion at bit level and compression." Thesis, Högskolan i Halmstad, Akademin för informationsteknologi, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-42449.
Full textBooks on the topic "Bit Paralell"
Rushton, Andrew. Reconfigurable processor-array: A bit-sliced parallel computer. London, [England]: Pitman, 1989.
Find full textReconfigurable processor-array: A bit-sliced parallel computer. London: Pitman, 1988.
Find full textRushton, A. Reconfigurable Processor Array A Bit Sliced Parallel Computer (USA). Irwin, 1991.
Find full textRushton, A. Reconfigurable Processor Array A Bit Sliced Parallel Computer (USA). Irwin, 1990.
Find full textRushton, A. Reconfigurable Processor Array A Bit Sliced Parallel Computer (USA). McGraw-Hill Education, 1986.
Find full textRushton, A. Reconfigurable Processor Array A Bit Sliced Parallel Computer (USA). McGraw-Hill Education, 1990.
Find full textRushton, A. Reconfigurable Processor Array A Bit Sliced Parallel Computer (USA). 4th ed. McGraw-Hill Education, 1990.
Find full textRushton, A. Reconfigurable Processor Array A Bit Sliced Parallel Computer (USA). McGraw-Hill Education, 1991.
Find full textBook chapters on the topic "Bit Paralell"
Mihailov, Mihail, and Hannu Tommola. "Compiling parallel text corpora." In Text Corpora and Multilingual Lexicography, 59–67. Amsterdam: John Benjamins Publishing Company, 2007. http://dx.doi.org/10.1075/bct.8.07mih.
Full textTran, Tuan Tu, Mathieu Giraud, and Jean-Stéphane Varré. "Bit-Parallel Multiple Pattern Matching." In Parallel Processing and Applied Mathematics, 292–301. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31500-8_30.
Full textHoriguchi, Susumu. "Towards Peta-Bit Photonic Networks." In Parallel and Distributed Processing and Applications, 3–16. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11576235_3.
Full textDoerr, Benjamin, Carola Doerr, and Jing Yang. "k-Bit Mutation with Self-Adjusting k Outperforms Standard Bit Mutation." In Parallel Problem Solving from Nature – PPSN XIV, 824–34. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-45823-6_77.
Full textHyyrö, Heikki. "Mining Bit-Parallel LCS-length Algorithms." In String Processing and Information Retrieval, 214–20. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-67428-5_18.
Full textHyyrö, Heikki, and Gonzalo Navarro. "Faster Bit-Parallel Approximate String Matching." In Combinatorial Pattern Matching, 203–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45452-7_18.
Full textStoyanov, Borislav, and Krasimir Kordov. "Pseudorandom Bit Generator with Parallel Implementation." In Large-Scale Scientific Computing, 557–64. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-662-43880-0_64.
Full textHyyrö, Heikki, Yoan Pinzon, and Ayumi Shinohara. "New Bit-Parallel Indel-Distance Algorithm." In Experimental and Efficient Algorithms, 380–90. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11427186_33.
Full textMishra, Bhabani Shankar Prasad, and Santwana Sagnika. "Parallel Environments." In Studies in Big Data, 21–30. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-27520-8_2.
Full textVáradi, Tamás, and Gábor Kiss. "Equivalence and non-equivalence in parallel corpora*." In Text Corpora and Multilingual Lexicography, 147–56. Amsterdam: John Benjamins Publishing Company, 2007. http://dx.doi.org/10.1075/bct.8.13var.
Full textConference papers on the topic "Bit Paralell"
Dietz, Henry G. "Parallel Bit Pattern Computing." In 2019 Tenth International Green and Sustainable Computing Conference (IGSC). IEEE, 2019. http://dx.doi.org/10.1109/igsc48788.2019.8957188.
Full textIngber, Amir, and Meir Feder. "Parallel bit interleaved coded modulation." In 2010 48th Annual Allerton Conference on Communication, Control, and Computing (Allerton). IEEE, 2010. http://dx.doi.org/10.1109/allerton.2010.5706910.
Full textMhedhbi, Imen, Khalil Hachicha, and Patrick Garda. "Multithreading parallel bit plane coding." In 2014 Conference on Design of Circuits and Integrated Systems (DCIS). IEEE, 2014. http://dx.doi.org/10.1109/dcis.2014.7035603.
Full textKrough, Bradley, Paul Corbitt, Lucia Cazares, James Masdea, and David Scadden. "Utilizing High-Frequency In-Bit Sensor Data Improves Drillbit Design and Modelling." In SPE Offshore Europe Conference & Exhibition. SPE, 2021. http://dx.doi.org/10.2118/205429-ms.
Full textMurta, Cristina Duarte, Mariane Raquel Silva Gonçalves, and Paula De Morais Pinhão. "Implementação e Avaliação de Algoritmos de Ordenação Paralela em MapReduce." In Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2013. http://dx.doi.org/10.5753/wscad.2013.16768.
Full textDenyer, P. B., and S. G. Smith. "Bit-Serial Architectures For Parallel Arrays." In O-E/LASE'86 Symp (January 1986, Los Angeles), edited by Keith Bromley. SPIE, 1986. http://dx.doi.org/10.1117/12.960499.
Full textChen, Ren, and Viktor K. Prasanna. "Optimal Circuits for Parallel Bit Reversal." In DAC '17: The 54th Annual Design Automation Conference 2017. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3061639.3062295.
Full textLee, Kyeongho, Jinho Jeong, Sungsoo Cheon, Woong Choi, and Jongsun Park. "Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision." In 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020. http://dx.doi.org/10.1109/dac18072.2020.9218567.
Full textBharathi, S. Jeya, M. Saravana Vadivu, and K. Thiagarajan. "Parallel Communicating Graph Grammar." In 2011 Sixth International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA). IEEE, 2011. http://dx.doi.org/10.1109/bic-ta.2011.2.
Full textQu, Pei-Yao, Guang-Ming Tang, Xiao-Chun Ye, Dong-Rui Fan, Zhi-Min Zhang, and Ning-Hui Sun. "Design of Datapath Circuits for a Bit-Parallel 8-bit RSFQ Microprocessor." In 2019 IEEE International Superconductive Electronics Conference (ISEC). IEEE, 2019. http://dx.doi.org/10.1109/isec46533.2019.8990911.
Full textReports on the topic "Bit Paralell"
Slone, Dale M. Efficient biased random bit generation for parallel processing. Office of Scientific and Technical Information (OSTI), September 1994. http://dx.doi.org/10.2172/105005.
Full textFang, Chin, and R. A. Corttrell. An Overview of High-performance Parallel Big Data transfers over multiple network channels with Transport Layer Security (TLS) and TLS plus Perfect Forward Secrecy (PFS). Office of Scientific and Technical Information (OSTI), May 2015. http://dx.doi.org/10.2172/1179171.
Full textKhomenko, Tetiana. TIME AND SPACE OF HISTORICAL PARALLELS OF EUGEN SVERSTIUK’S JOURNALISM. Ivan Franko National University of Lviv, March 2021. http://dx.doi.org/10.30970/vjo.2021.50.11095.
Full textMelnyk, Iurii. JUSTIFICATION OF OCCUPATION IN GERMAN (1938) AND RUSSIAN (2014) MEDIA: SUBSTITUTION OF AGGRESSOR AND VICTIM. Ivan Franko National University of Lviv, March 2021. http://dx.doi.org/10.30970/vjo.2021.50.11101.
Full textHall, Mark, and Neil Price. Medieval Scotland: A Future for its Past. Society of Antiquaries of Scotland, September 2012. http://dx.doi.org/10.9750/scarf.09.2012.165.
Full textCox, Jeremy. The unheard voice and the unseen shadow. Norges Musikkhøgskole, August 2018. http://dx.doi.org/10.22501/nmh-ar.621671.
Full textHunter, Fraser, and Martin Carruthers. Iron Age Scotland. Society for Antiquaries of Scotland, September 2012. http://dx.doi.org/10.9750/scarf.09.2012.193.
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