Log in

Relevant bibliographies by topics / Bit Paralell / Journal articles

To see the other types of publications on this topic, follow the link: Bit Paralell.

Journal articles on the topic 'Bit Paralell'

Author: Grafiati

Published: 4 June 2021

Last updated: 4 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Bit Paralell.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Yun Sik Lee and P. M. Maurer. "Bit-parallel multidelay simulation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 15, no. 12 (1996): 1547–54. http://dx.doi.org/10.1109/43.552088.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Qu, Pei-Yao, Guang-Ming Tang, Jia-Hong Yang, Xiao-Chun Ye, Dong-Rui Fan, Zhi-Min Zhang, and Ning-Hui Sun. "Design of an 8-bit Bit-Parallel RSFQ Microprocessor." IEEE Transactions on Applied Superconductivity 30, no. 7 (October 2020): 1–6. http://dx.doi.org/10.1109/tasc.2020.3017527.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Wu, Xiaofu, Chunming Zhao, and Xiaohu You. "Parallel Weighted Bit-Flipping Decoding." IEEE Communications Letters 11, no. 8 (August 2007): 671–73. http://dx.doi.org/10.1109/lcomm.2007.070269.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Li, Pu, Kunying Li, Xiaomin Guo, Yanqiang Guo, Yiming Liu, Bingjie Xu, Adonis Bogris, K. Alan Shore, and Yuncai Wang. "Parallel optical random bit generator." Optics Letters 44, no. 10 (May 9, 2019): 2446. http://dx.doi.org/10.1364/ol.44.002446.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

North, Richard C., and Walter H. Ku. "β-bit serial/parallel multipliers." Journal of VLSI signal processing systems for signal, image and video technology 2, no. 4 (May 1991): 219–33. http://dx.doi.org/10.1007/bf00925467.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Crook, David, and John Fulcher. "A Comparison of Bit Serial and Bit Parallel DCT Designs." VLSI Design 3, no. 1 (January 1, 1995): 59–65. http://dx.doi.org/10.1155/1995/30583.

Full text

Abstract:

Bit parallel and bit serial VLSI designs for performing 1-dimensional Discrete Cosine Transforms are compared, in terms of size, complexity and throughput. It is concluded that the bit serial approach is more suited to this application, given the limitations of not only the available VLSI design tools, but also the available silicon real estate allocated for final chip fabrication.

APA, Harvard, Vancouver, ISO, and other styles

7

Kaur, Amandeep, Deepak Mishra, and Mukul Sarkar. "A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 1 (January 2019): 248–52. http://dx.doi.org/10.1109/tvlsi.2018.2871341.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

LO‡, HAO-YUNG, and FANG HSU. "A combinational word-parallel and bit-parallel associative processor." International Journal of Electronics 62, no. 4 (April 1987): 589–98. http://dx.doi.org/10.1080/00207218708921010.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Scherson, I. D., D. A. Kramer, and B. D. Alleyne. "Bit-parallel arithmetic in a massively-parallel associative processor." IEEE Transactions on Computers 41, no. 10 (1992): 1201–10. http://dx.doi.org/10.1109/12.166599.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Mansour, M. M. "A Parallel Pruned Bit-Reversal Interleaver." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 8 (August 2009): 1147–51. http://dx.doi.org/10.1109/tvlsi.2008.2008831.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Li, Weijun, Feng Yu, and Zhenguo Ma. "Efficient Circuit for Parallel Bit Reversal." IEEE Transactions on Circuits and Systems II: Express Briefs 63, no. 4 (April 2016): 381–85. http://dx.doi.org/10.1109/tcsii.2015.2504943.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Rautiainen, Mikko, Veli Mäkinen, and Tobias Marschall. "Bit-parallel sequence-to-graph alignment." Bioinformatics 35, no. 19 (March 9, 2019): 3599–607. http://dx.doi.org/10.1093/bioinformatics/btz162.

Full text

Abstract:

Abstract Motivation Graphs are commonly used to represent sets of sequences. Either edges or nodes can be labeled by sequences, so that each path in the graph spells a concatenated sequence. Examples include graphs to represent genome assemblies, such as string graphs and de Bruijn graphs, and graphs to represent a pan-genome and hence the genetic variation present in a population. Being able to align sequencing reads to such graphs is a key step for many analyses and its applications include genome assembly, read error correction and variant calling with respect to a variation graph. Results We generalize two linear sequence-to-sequence algorithms to graphs: the Shift-And algorithm for exact matching and Myers’ bitvector algorithm for semi-global alignment. These linear algorithms are both based on processing w sequence characters with a constant number of operations, where w is the word size of the machine (commonly 64), and achieve a speedup of up to w over naive algorithms. For a graph with |V| nodes and |E| edges and a sequence of length m, our bitvector-based graph alignment algorithm reaches a worst case runtime of O(|V|+⌈mw⌉|E| log w) for acyclic graphs and O(|V|+m|E| log w) for arbitrary cyclic graphs. We apply it to five different types of graphs and observe a speedup between 3-fold and 20-fold compared with a previous (asymptotically optimal) alignment algorithm. Availability and implementation https://github.com/maickrau/GraphAligner Supplementary information Supplementary data are available at Bioinformatics online.

APA, Harvard, Vancouver, ISO, and other styles

13

Rudolph, Larry. "Bit-parallel, free-space, optical communication." Communications on Pure and Applied Mathematics 48, no. 9 (1995): 1157–71. http://dx.doi.org/10.1002/cpa.3160480909.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Pekmestzi, K. Z., and C. Caraiscos. "Low-latency bit-parallel systolic multiplier." Electronics Letters 29, no. 4 (1993): 367. http://dx.doi.org/10.1049/el:19930247.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Gaikwad, Vrushali, Rajeshree Brahmankar, Amiruna Warambhe, Yugandhara Kute, and Nishant Pandey. "32 Bit Parallel Multiplier Using VHDL." International Journal of Engineering Trends and Technology 9, no. 3 (March 25, 2014): 129–32. http://dx.doi.org/10.14445/22315381/ijett-v9p226.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Wu, Angela Y., and Azriel Rosenfeld. "Parallel processing of encoded bit strings." Pattern Recognition 21, no. 6 (January 1988): 559–65. http://dx.doi.org/10.1016/0031-3203(88)90029-5.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Seo, Hwajeong, Hyunjun Kim, Kyungbae Jang, Hyeokdong Kwon, Minjoo Sim, Gyeongju Song, Siwoo Uhm, and Hyunji Kim. "Secure HIGHT Implementation on ARM Processors." Mathematics 9, no. 9 (May 6, 2021): 1044. http://dx.doi.org/10.3390/math9091044.

Full text

Abstract:

Secure and compact designs of HIGHT block cipher on representative ARM microcontrollers are presented in this paper. We present several optimizations for implementations of the HIGHT block cipher, which exploit different parallel approaches, including task parallelism and data parallelism methods, for high-speed and high-throughput implementations. For the efficient parallel implementation of the HIGHT block cipher, the SIMD instructions of ARM architecture are fully utilized. These instructions support four-way 8-bit operations in the parallel way. The length of primitive operations in the HIGHT block cipher is 8-bit-wise in addition–rotation–exclusive-or operations. In the 32-bit word architecture (i.e., the 32-bit ARM architecture), four 8-bit operations are executed at once with the four-way SIMD instruction. By exploiting the SIMD instruction, three parallel HIGHT implementations are presented, including task-parallel, data-parallel, and task/data-parallel implementations. In terms of the secure implementation, we present a fault injection countermeasure for 32-bit ARM microcontrollers. The implementation ensures the fault detection through the representation of intra-instruction redundancy for the data format. In particular, we proposed two fault detection implementations by using parallel implementations. The two-way task/data-parallel based implementation is secure against fault injection models, including chosen bit pair, random bit, and random byte. The alternative four-way data-parallel-based implementation ensures all security features of the aforementioned secure implementations. Moreover, the instruction skip model is also prevented. The implementation of the HIGHT block cipher is further improved by using the constant value of the counter mode of operation. In particular, the 32-bit nonce value is pre-computed and the intermediate result is directly utilized. Finally, the optimized implementation achieved faster execution timing and security features toward the fault attack than previous works.

APA, Harvard, Vancouver, ISO, and other styles

18

Mai, Luong Chi. "Parallel object classification algorithms in images." Journal of Computer Science and Cybernetics 10, no. 3 (April 15, 2016): 25–34. http://dx.doi.org/10.15625/1813-9663/10/3/8195.

Full text

Abstract:

The contribution concerns a parallelization of object classification algorithms for a SIMD-type parallel machine. It is assumed that gray-level values of image pixels are located in the orthogonal memory block on which a vector of one-bit processor operates in the bit-serial and word – parallel mode. For this computer, the Bayes classification algorithm, the K-mean algorithm and the ensemble average classifier and described.

APA, Harvard, Vancouver, ISO, and other styles

19

Baudais, Jean-Yves, Fahad Syed Muhammad, and Jean-François Hélard. "Robustness Maximization of Parallel Multichannel Systems." Journal of Electrical and Computer Engineering 2012 (2012): 1–16. http://dx.doi.org/10.1155/2012/840513.

Full text

Abstract:

Bit error rate (BER) minimization and SNR-gap maximization, two robustness optimization problems, are solved, under average power and bitrate constraints, according to the waterfilling policy. Under peak power constraint the solutions differ and this paper gives bit-loading solutions of both robustness optimization problems over independent parallel channels. The study is based on analytical approach, using generalized Lagrangian relaxation tool, and on greedy-type algorithm approach. Tight BER expressions are used for square and rectangular quadrature amplitude modulations. Integer bit solution of analytical continuous bitrates is performed with a new generalized secant method. The asymptotic convergence of both robustness optimizations is proved for both analytical and algorithmic approaches. We also prove that, in the conventional margin maximization problem, the equivalence between SNR-gap maximization and power minimization does not hold with peak-power limitation. Based on a defined dissimilarity measure, bit-loading solutions are compared over Rayleigh fading channel for multicarrier systems. Simulation results confirm the asymptotic convergence of both resource allocation policies. In nonasymptotic regime the resource allocation policies can be interchanged depending on the robustness measure and on the operating point of the communication system. The low computational effort leads to a good trade-off between performance and complexity.

APA, Harvard, Vancouver, ISO, and other styles

20

Gupta, Sumit, and Akhtar Rasool. "Bit Parallel String Matching Algorithms: A Survey." International Journal of Computer Applications 95, no. 10 (June 18, 2014): 27–32. http://dx.doi.org/10.5120/16632-6501.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Velrajkumar, Pitchandi, C. Senthilpari, G. Ramanamurthy, and EK Wong. "Bit parallel - iterative circuit for robotic application." IEICE Electronics Express 9, no. 6 (2012): 443–49. http://dx.doi.org/10.1587/elex.9.443.

Full text

APA, Harvard, Vancouver, ISO, and other styles

22

Heule, Marijn, and Hans van Maaren. "Parallel SAT Solving using Bit-level Operations1." Journal on Satisfiability, Boolean Modeling and Computation 4, no. 2-4 (May 1, 2008): 99–116. http://dx.doi.org/10.3233/sat190040.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Kirichenko, Alex F., Igor V. Vernik, Michael Y. Kamkar, Jason Walter, Maximilian Miller, Lucian Remus Albu, and Oleg A. Mukhanov. "ERSFQ 8-Bit Parallel Arithmetic Logic Unit." IEEE Transactions on Applied Superconductivity 29, no. 5 (August 2019): 1–7. http://dx.doi.org/10.1109/tasc.2019.2904484.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Larsson-Edefors, P., and W. P. Marnane. "Most-significant-bit-first serial/parallel multipliers." IEE Proceedings - Circuits, Devices and Systems 145, no. 4 (1998): 278. http://dx.doi.org/10.1049/ip-cds:19982122.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Hung, Che-Lun, Chun-Yuan Lin, Chia-Shin Ou, Yuan-Hong Tseng, Po-Yen Hung, Ship-Peng Li, and Chun-Ting Fu. "Efficient bit-parallel subcircuit extraction using CUDA." Concurrency and Computation: Practice and Experience 28, no. 16 (December 23, 2015): 4326–38. http://dx.doi.org/10.1002/cpe.3732.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

P.Chaitanya kumari, P. Chaitanya kumari. "Design of 32 bit Parallel Prefix Adders." IOSR Journal of Electronics and Communication Engineering 6, no. 1 (2013): 1–6. http://dx.doi.org/10.9790/2834-610106.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Akl, Selim G., and Henk Meijer. "On the bit complexity of parallel computations." Integration 6, no. 2 (July 1988): 201–12. http://dx.doi.org/10.1016/0167-9260(88)90039-9.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Hariri, Arash, and Arash Reyhani-Masoleh. "Bit-Serial and Bit-Parallel Montgomery Multiplication and Squaring over GF(2^m)." IEEE Transactions on Computers 58, no. 10 (October 2009): 1332–45. http://dx.doi.org/10.1109/tc.2009.70.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Dobos, Andrew, Taraka Sai Pavan Grandhi, Sudhakar Godeshala, Deirdre R. Meldrum, and Kaushal Rege. "Parallel fabrication of macroporous scaffolds." Biotechnology and Bioengineering 115, no. 7 (March 31, 2018): 1729–42. http://dx.doi.org/10.1002/bit.26593.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

K, Nehru K., Nagarjuna T, and Somanaidu U. "Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 2 (July 1, 2018): 115. http://dx.doi.org/10.11591/ijres.v7.i2.pp115-123.

Full text

Abstract:

<span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes<strong> </strong>with the lowest transistor<strong> </strong>count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.</span>

APA, Harvard, Vancouver, ISO, and other styles

31

Berisha, Artan, and Hektor Kastrati. "Parallel impelementation of RC6 algorithm." Journal of Computer Science and Technology Studies 3, no. 2 (June 26, 2021): 01–09. http://dx.doi.org/10.32996/jcsts.2021.3.2.1.

Full text

Abstract:

Data security is very important in the field of Computer Science. In this paper the encryption algorithm called RC6 will be analyzed and its standard and parallel implementation will be done. First the field of Cryptology is discussed in general terms, then the classification of encryption algorithms according to operation and techniques is explained. RC6 is a symmetric block algorithm derived from the RC5 algorithm. RC6 operates on 128-bit blocks and accepts 128, 192, 256-bit keys until 2040 bytes. In the Advanced Encryption Standard (AES) competition, RC6 managed to rank among the five finalists. The structure of the RC6 algorithm will be analyzed also the encryption and decryption methods. The comparison between standard and parallel implementation will be made.

APA, Harvard, Vancouver, ISO, and other styles

32

Lakshmi Prasanna, J., V. Sahiti, E. Raghuveera, and M. Ravi Kumar. "CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 647. http://dx.doi.org/10.14419/ijet.v7i2.7.10915.

Full text

Abstract:

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs.

APA, Harvard, Vancouver, ISO, and other styles

33

Pinto, Rohan, and Kumara Shama. "Low-Power Modified Shift-Add Multiplier Design Using Parallel Prefix Adder." Journal of Circuits, Systems and Computers 28, no. 02 (November 12, 2018): 1950019. http://dx.doi.org/10.1142/s0218126619500191.

Full text

Abstract:

Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier “bypass zero feed multiplicand directly,” based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed parallel prefix adders designed based on revised Ling equations. The proposed 8-bit, 16-bit and 32-bit multipliers are implemented using 180-nm and 90-nm CMOS technologies. Simulation results reveal that the proposed multiplier is fast and lowers the power by 35% predominantly for a 32-bit multiplier.

APA, Harvard, Vancouver, ISO, and other styles

34

., Ajitha S. S. "EFFICIENT IMPLEMENTATION OF BIT PARALLEL FINITE FIELD MULTIPLIERS." International Journal of Research in Engineering and Technology 03, no. 03 (March 25, 2014): 661–67. http://dx.doi.org/10.15623/ijret.2014.0303122.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Imana, J. L., J. M. Sanchez, and F. Tirado. "Bit-parallel finite field multipliers for irreducible trinomials." IEEE Transactions on Computers 55, no. 5 (May 2006): 520–33. http://dx.doi.org/10.1109/tc.2006.69.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Li, Yao, Ting Wang, Hideo Kosaka, Shigeru Kawai, and Kenichi Kasahara. "Fiber-image-guide-based bit-parallel optical interconnects." Applied Optics 35, no. 35 (December 10, 1996): 6920. http://dx.doi.org/10.1364/ao.35.006920.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Enuchenko, M. S., D. V. Morozov, and M. M. Pilipko. "An 8-bit parallel DAC with segmented architecture." Journal of Communications Technology and Electronics 62, no. 1 (January 2017): 89–100. http://dx.doi.org/10.1134/s1064226917010053.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Chen, K. H., G. S. Huang, and R. C. T. Lee. "Bit-Parallel Algorithms for Exact Circular String Matching." Computer Journal 57, no. 5 (March 3, 2013): 731–43. http://dx.doi.org/10.1093/comjnl/bxt023.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Crochemore, Maxime, Costas S. Iliopoulos, Gonzalo Navarro, Yoan J. Pinzon, and Alejandro Salinger. "Bit-parallel (δ,γ)-matching and suffix automata." Journal of Discrete Algorithms 3, no. 2-4 (June 2005): 198–214. http://dx.doi.org/10.1016/j.jda.2004.08.005.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Hyyrö, Heikki. "Bit-parallel approximate string matching algorithms with transposition." Journal of Discrete Algorithms 3, no. 2-4 (June 2005): 215–29. http://dx.doi.org/10.1016/j.jda.2004.08.006.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

San Segundo, Pablo, Fernando Matia, Diego Rodriguez-Losada, and Miguel Hernando. "An improved bit parallel exact maximum clique algorithm." Optimization Letters 7, no. 3 (December 31, 2011): 467–79. http://dx.doi.org/10.1007/s11590-011-0431-y.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Hatamian, M., and G. L. Cash. "A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS." IEEE Journal of Solid-State Circuits 21, no. 4 (August 1986): 505–13. http://dx.doi.org/10.1109/jssc.1986.1052564.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Singhal, Subodh Kumar, B. K. Mohanty, Sujit Kumar Patel, and Gaurav Saxena. "Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder." Journal of Circuits, Systems and Computers 29, no. 12 (February 4, 2020): 2050186. http://dx.doi.org/10.1142/s0218126620501868.

Full text

Abstract:

Parallel prefix adder (PPA) is the core component of diminished-1 modulo ([Formula: see text]) adder structure. In this paper, group-carry selection logic based PPA design is proposed and it is free from redundant logic operations which otherwise present in the existing PPA design based on group sum selection logic. Further, the logic expression of pre-processing unit of PPA is also presented in a simplified form to save some logic resources. The proposed PPA design for bit-width 32-bit involves 26.1% less area, consumes 28.4% less power and marginally higher critical-path delay than the existing PPA design. An efficient diminished-1 modulo ([Formula: see text]) adder structure is presented using proposed PPA design and modified carry computation algorithm of existing design. The proposed diminished-1 modulo ([Formula: see text]) adder structure for bit-width 32-bit offers a saving of 25.5% in area-delay-product (ADP) and 24.1% in energy-delay-product (EDP) than the best of the existing modulo adder structure.

APA, Harvard, Vancouver, ISO, and other styles

44

WEN, HE, LASZLO B. KISH, and ANDREAS KLAPPENECKER. "COMPLEX NOISE-BITS AND LARGE-SCALE INSTANTANEOUS PARALLEL OPERATIONS WITH LOW COMPLEXITY." Fluctuation and Noise Letters 12, no. 01 (March 2013): 1350002. http://dx.doi.org/10.1142/s0219477513500028.

Full text

Abstract:

We introduce the complex noise-bit as information carrier, which requires noise signals in two parallel wires instead of the single-wire representations of noise-based logic discussed so far. The immediate advantage of this new scheme is that, when we use random telegraph waves as noise carrier, the superposition of the first 2N integer numbers (obtained by the Achilles heel operation) yields nonzero values. We introduce basic instantaneous operations, with O(20) time and hardware complexity, including bit-value measurements in product states, single-bit and two-bit noise-gates (universality exists) that can instantaneously operate over large superpositions with full parallelism. We envision the possibility of implementing instantaneously running quantum algorithms on classical computers while using similar number of classical bits as the number of quantum bits emulated without the necessity of error corrections. Mathematical analysis and proofs are given.

APA, Harvard, Vancouver, ISO, and other styles

45

Gharajeh, Mohammad, and Majid Haghparast. "Novel reversible CLA, optimized RCA and parallel adder/subtractor circuits." Serbian Journal of Electrical Engineering 17, no. 3 (2020): 259–83. http://dx.doi.org/10.2298/sjee2003259g.

Full text

Abstract:

This paper proposes reversible circuit designs of the three most commonly used adders: carry look-ahead adder (CLA adder), ripple carry adder (RCA adder), and parallel adder/subtractor. The n-bit reversible CLA adder, called CLA-GH, is designed using the Peres and Fredkin gates. The n-bit optimized reversible RCA adder, called ORCA-GH, is designed using the reversible circuit of a parity-preserving reversible full adder. Both circuits reduce the quantum cost. However, the ORCA-GH circuit also improves the number of constant inputs. Furthermore, the n-bit reversible parallel adder/subtractor, called PAS-GH, is designed using the Feynman, Peres, and Fredkin gates. It decreases the number of garbage outputs and quantum cost. The transistor realizations of the CLA-GH and PAS-GH circuits are provided accordingly. The evaluation results indicate that the proposed circuits surpass the existing works in all figures of merit.

APA, Harvard, Vancouver, ISO, and other styles

46

Zhang, Jing Xian, Zheng Song, and Qing Sheng Hu. "A Systolic Bit-Parallel Multiplier with Flexible Latency and Complexity over GF(2m) Using Polynomial Basis." Advanced Materials Research 457-458 (January 2012): 848–55. http://dx.doi.org/10.4028/www.scientific.net/amr.457-458.848.

Full text

Abstract:

This paper presents a systolic bit-parallel multiplier with flexible latency and complexity over GF(2m) using polynomial basis. Via the employment of shift register array and pipeline strategy, the multiplier designed in this paper is able to work pipelining parallel with smaller critical path. A cell which could reach the function of reducing the input operand’s degree by one and add the results of different degrees together is created in this paper. The systolic bit-parallel multiplier can be made of several such cells. Several multipliers which have different latencies and complexities with pipeline strategy are created with further discuss, the comprehensive performances of these designs are estimated with the parameter of area-time. At the end of the page, we compare the systolic bit-parallel multiplier of this paper with a certain number of typical designs these years, the result shows that the design in this paper obtains a comprehensive performance improvement by 70%, 27% and 31%.

APA, Harvard, Vancouver, ISO, and other styles

47

Vieira Segatto, M. E., F. N. Timofeev, R. Wyatt, R. Kashyap, and J. R. Taylor. "Use of fibre gratings for bit skew compensation in all optical bit parallel WDM systems." Optics Communications 190, no. 1-6 (April 2001): 165–71. http://dx.doi.org/10.1016/s0030-4018(01)01092-6.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

JENG, SHIANN-SHIUN, HSING-CHEN LIN, CHUN-CHYUAN CHEN, and SHU-MING CHANG. "HARDWARE IMPLEMENTATION AND VERIFICATION OF FIR FILTER UTILIZING M-BIT PDA." Journal of Circuits, Systems and Computers 19, no. 02 (April 2010): 503–17. http://dx.doi.org/10.1142/s0218126610006207.

Full text

Abstract:

An efficient architecture for a FPGA symmetry FIR filter is proposed that employs the M-bit parallel-distributed arithmetic (M-bit PDA). The partial product is pre-calculated and saved into the distributed ROM to eliminate a large amount of multiplications. Altera Stratix II EP2S60 is used as a target device to implement the M-bit PDA. The hardware implementation requires 936 adaptive look-up tables (ALUTs), 888 registers, 1 PLL, 40960 memory bits for the FIR filter implementation with the M-bit PDA (in this case M = 2). Additionally, the maximum clock rate for this implementation can be achieved up to 155.36 MHz. In comparison with the parallel multiplier/adder cell (MAC) and serial distributed arithmetic (SDA), the proposed architecture consumes a smaller area and operates with a higher speed due to omitting the multipliers.

APA, Harvard, Vancouver, ISO, and other styles

49

Lee, Chiou-Yng. "Low-complexity bit-parallel systolic multipliers over GF(2 )." Integration 41, no. 1 (January 2008): 106–12. http://dx.doi.org/10.1016/j.vlsi.2007.05.001.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Xu, Kefu, Wenke Cui, Yue Hu, and Li Guo. "Bit-Parallel Multiple Approximate String Matching based on GPU." Procedia Computer Science 17 (2013): 523–29. http://dx.doi.org/10.1016/j.procs.2013.05.067.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!