Relevant bibliographies by topics / Bitstream access

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  1. Journal articles

Academic literature on the topic 'Bitstream access'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Bitstream access"

1

Yan, Tao, Xiao Xiong Zhou, Wen Ting Luo, Ze Liang Liu, and Pan Dong Zhang. "Multi-View Video Coding Based on Video Correction." Advanced Materials Research 989-994 (July 2014): 3714–17. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.3714.

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In order to enables the video to be displayed on a multitude of different terminals, Multi-view video coding (MVC) demands high compression rates as well as view scalability. A new the inter-view prediction structure with flexibility, MVC compatibility and view scalability is proposed. The proposed scheme first correct views. It then uses the position of the cameras and the relation of inter-views to divide all views into base view and enhancement views. Finally, the views quire by the viewers use scalable Multi-view Video Coding (SMVC). The main bitstream is the same as a H.264/AVC mono-sequence bitstream for H.264/AVC compatibility. The auxiliary bitstream come from enhancement views coding. We proposed SMVC scheme is tested with two Multi-view sequences to determine its flexibly view scalability, high coding efficiency and random access performance.
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2

Moiron, Sandro, Rouzbeh Razavi, Martin Fleury, and Mohammed Ghanbari. "Intelligent Bandwidth Allocation of IPTV Streams with Bitstream Complexity Measures." International Journal of Handheld Computing Research 4, no. 3 (2013): 41–62. http://dx.doi.org/10.4018/jhcr.2013070103.

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IPTV video services are increasingly being considered for delivery to mobile devices over broadband wireless access networks. The IPTV streams or channels are multiplexed together for transport across an IP core network prior to distribution across the access network. According to the type of access network, prior bandwidth constraints exist that restrict the multiplex data-rate. This paper presents a bandwidth allocation scheme based on content complexity to equalize the overall video quality of the IPTV sub-streams, in effect a form of statistical multiplexing. Bandwidth adaptation is achieved through a bank of bit-rate transcoders. Complexity metrics serve to estimate the appropriate bandwidth share for each stream, prior to distribution over a wireless or ADSL access network. These metrics are derived after entropy decoding of the input compressed bit-streams, without the delay resulting from a full decode. Fuzzy-logic control serves to adjust the balance between spatial and temporal coding complexity. The paper examines constant and varying bandwidth scenarios. Experimental results show a significant overall gain in video quality in comparison to a fixed bandwidth allocation.
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3

Zhang, Tao, Jian Wang, Shize Guo, and Zhe Chen. "A Comprehensive FPGA Reverse Engineering Tool-Chain: From Bitstream to RTL Code." IEEE Access 7 (2019): 38379–89. http://dx.doi.org/10.1109/access.2019.2901949.

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4

Lin, Yongbing, and Philipp Zhang. "A new bitstream random access scheme using multipicture motion-compensated prediction." IEEE Transactions on Consumer Electronics 55, no. 2 (2009): 670–76. http://dx.doi.org/10.1109/tce.2009.5174438.

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5

Shang, Yueyun, Dengpan Ye, Zhuo Wei, and Yajuan Xie. "GPU-Based MPEG-2 to Secure Scalable Video Transcoding." International Journal of Digital Crime and Forensics 6, no. 2 (2014): 52–69. http://dx.doi.org/10.4018/ijdcf.2014040104.

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Most of the high definition video content are still produced in a single-layer MPEG-2 format. Multiple-layers Scalable Video Coding (SVC) offers a minor penalty in rate-distortion efficiency when compared to single-layer coding MPEG-2. A scaled version of the original SVC bitstream can easily be extracted by dropping layers from the bitstream. This paper proposes a parallel transcoder from MPEG-2 to SVC video with Graphics Processing Unit (GPU), named PTSVC. The objective of the transcoder is to migrate MPEG-2 format video to SVC format video such that clients with different network bandwidth and terminal devices can seamlessly access video content. Meanwhile, the transcoded SVC videos are encrypted such that only authorized users can access corresponding SVC layers. Using various scalabilities SVC test sequences, experimental results on TM5 and JSVM indicate that PTSVC is a higher efficient transcoding system compared with previous systems and only causes little quality loss.
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6

Cardona, Luis Andres, and Carles Ferrer. "AC_ICAP: A Flexible High Speed ICAP Controller." International Journal of Reconfigurable Computing 2015 (2015): 1–15. http://dx.doi.org/10.1155/2015/314358.

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The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller.
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7

Chen, Minzhen, and Peng Liu. "A Deep Learning-Based FPGA Function Block Detection Method With Bitstream to Image Transformation." IEEE Access 9 (2021): 99794–804. http://dx.doi.org/10.1109/access.2021.3096664.

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8

Owen Jr., Don, Derek Heeger, Calvin Chan, et al. "An Autonomous, Self-Authenticating, and Self-Contained Secure Boot Process for Field-Programmable Gate Arrays." Cryptography 2, no. 3 (2018): 15. http://dx.doi.org/10.3390/cryptography2030015.

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Secure booting within a field-programmable gate array (FPGA) environment is traditionally implemented using hardwired embedded cryptographic primitives and non-volatile memory (NVM)-based keys, whereby an encrypted bitstream is decrypted as it is loaded from an external storage medium, e.g., Flash memory. A novel technique is proposed in this paper that self-authenticates an unencrypted FPGA configuration bitstream loaded into the FPGA during the start-up. The internal configuration access port (ICAP) interface is accessed to read out configuration information of the unencrypted bitstream, which is then used as input to a secure hash function SHA-3 to generate a digest. In contrast to conventional authentication, where the digest is computed and compared with a second pre-computed value, we use the digest as a challenge to a hardware-embedded delay physical unclonable function (PUF) called HELP. The delays of the paths sensitized by the challenges are used to generate a decryption key using the HELP algorithm. The decryption key is used in the second stage of the boot process to decrypt the operating system (OS) and applications. It follows that any type of malicious tampering with the unencrypted bitstream changes the challenges and the corresponding decryption key, resulting in key regeneration failure. A ring oscillator is used as a clock to make the process autonomous (and unstoppable), and a novel on-chip time-to-digital-converter is used to measure path delays, making the proposed boot process completely self-contained, i.e., implemented entirely within the re-configurable fabric and without utilizing any vendor-specific FPGA features.
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9

Raake, Alexander, Silvio Borer, Shahid M. Satti, et al. "Multi-Model Standard for Bitstream-, Pixel-Based and Hybrid Video Quality Assessment of UHD/4K: ITU-T P.1204." IEEE Access 8 (2020): 193020–49. http://dx.doi.org/10.1109/access.2020.3032080.

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10

Sultana, Bushra, Anees Ullah, Arsalan Ali Malik, et al. "VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC." Electronics 10, no. 8 (2021): 899. http://dx.doi.org/10.3390/electronics10080899.

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Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.
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