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Relevant bibliographies by topics / Boostable repeater

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Journal articles
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Academic literature on the topic 'Boostable repeater'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 February 2022

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Journal articles on the topic "Boostable repeater"

1

Shim, Kyu-Nam, and Jiang Hu. "Boostable Repeater Design for Variation Resilience in VLSI Interconnects." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 9 (2013): 1619–31. http://dx.doi.org/10.1109/tvlsi.2012.2212733.

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2

Sharma, Pawan, Anil Kumar, Balwan Singh, et al. "Characterization of Protective Epitopes in a Highly Conserved Plasmodium falciparum Antigenic Protein Containing Repeats of Acidic and Basic Residues." Infection and Immunity 66, no. 6 (1998): 2895–904. http://dx.doi.org/10.1128/iai.66.6.2895-2904.1998.

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ABSTRACT The delineation of putatively protective and immunogenic epitopes in vaccine candidate proteins constitutes a major research effort towards the development of an effective malaria vaccine. By virtue of its role in the formation of the immune clusters of merozoites, its location on the surface of merozoites, and its highly conserved nature both at the nucleotide sequence level and the amino acid sequence level, the antigen which contains repeats of acidic and basic residues (ABRA) of the human malaria parasitePlasmodium falciparum represents such an antigen. Based upon the predicted am

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3

VENKATAIAH, C., V. N. V. SATYA PRAKASH, and V. NEERAJA. "Design of Boostable Repeater for VLSI Interconnects." IJARCCE, November 27, 2014, 8396–402. http://dx.doi.org/10.17148/ijarcce.2014.31110.

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4

"BOOSTABLE REPEATER DESIGN WITH DUAL ADAPTIVE SUPPLY VOLTAGE FOR VLSI INTERCONNECTS." International Journal of Advance Engineering and Research Development 2, no. 11 (2015). http://dx.doi.org/10.21090/ijaerd.021171.

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Dissertations / Theses on the topic "Boostable repeater"

1

Shim, Kyu-Nam 1978. "Voltage and Timing Adaptation for Variation and Aging Tolerance in Nanometer VLSI Circuits." Thesis, 2012. http://hdl.handle.net/1969.1/148350.

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Process variations and circuit aging continue to be main challenges to the power-efficiency of VLSI circuits, as considerable power budget must be allocated at design time to mitigate timing variations. Modern designs incorporate adaptive techniques for variation compensation to reduce the extra power consumption. The efficiency of existing adaptive approaches, however, is often significantly attenuated by the fine-grained nature of variations in nanometer technology such as random dopant fluctuation, litho-variation, and different rates of transistor degradation due to non-uniform activity fa

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