Relevant bibliographies by topics / Booth radix-16

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  3. Conference papers

Academic literature on the topic 'Booth radix-16'

Author: Grafiati
Published: 7 June 2025
Last updated: 2 August 2025

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Journal articles on the topic "Booth radix-16"

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Kim, Hyunpil, Sangook Moon, and Yongsurk Lee. "Radix-16 Booth multiplier using novel weighted 2-stage Booth algorithm." IEICE Electronics Express 11, no. 13 (2014): 20140407. http://dx.doi.org/10.1587/elex.11.20140407.

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Choubey, Abhishek, SPV Subbarao, and Shruti B. Choubey. "Design of delay efficient Booth multiplier using pipelining." International Journal of Engineering & Technology 7, no. 2.16 (2018): 94. http://dx.doi.org/10.14419/ijet.v7i2.16.11423.

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Multiplication is one of the most an essential arithmetic operation used in numerous applications in digital signal processing and communications. These applications need transformations, convolutions and dot products that involve an enormous amount of multiplications of an operand with a constant. Typical examples include wavelet, digital filters, such as FIR or IIR. However, multiplier structures have relatively large area-delay product, long latency and significantly high power consumption compared to other the arithmetic structure. Therefore, low power multiplier design has been always a s
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A, Jenitha, Ashwini S, Bharath Reddy S, Dinesh Kumar R, and Sahana R. "PARTIAL PRODUCT ARRAY HEIGHT REDUCTION USING RADIX-16 FOR 64-BIT BOOTH MULTIPLIER." International Journal of Current Engineering and Scientific Research 6, no. 6 (2019): 90–95. http://dx.doi.org/10.21276/ijcesr.2019.6.6.17.

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Cekli, Serap, and Ali Akman. "A high speed pipelined radix-16 Booth multiplier architecture for FPGA implementation." AEU - International Journal of Electronics and Communications 185 (October 2024): 155435. http://dx.doi.org/10.1016/j.aeue.2024.155435.

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SHIN, Ji-Hye, and Young-Beom JANG. "A New DA Implementation Technique for Digital Filters Using Radix-16 Modified Booth Algorithm." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E94-A, no. 4 (2011): 1136–39. http://dx.doi.org/10.1587/transfun.e94.a.1136.

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Antelo, Elisardo, Paolo Montuschi, and Alberto Nannarelli. "Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 2 (2017): 409–18. http://dx.doi.org/10.1109/tcsi.2016.2561518.

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Kuo, Chao-Tsung, and Yao-Cheng Wu. "FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme." Applied Sciences 13, no. 18 (2023): 10407. http://dx.doi.org/10.3390/app131810407.

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The residue number system is widely used in applications such as communication systems, cryptography, digital filters, digital signal processors, fault-tolerant detection, and so on. This paper proposes a multifunction modulo (2n ± 1) multiplier based on the radix-4 Booth encoding scheme that can operate both modulo (2n − 1) and modulo (2n + 1) multipliers using the same hardware structure with only one control signal. A novel modulo (2n ± 1) multiplier based on radix-4 Booth encoding is proposed that can achieve superior performance, with low power, fast operation, high area efficiency, and l
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Kumaresan, K., Arunkumar, P., and Arivazhagan, P. "Enhanced Design of High Performance Radix-16 Booth Multiplier Using Partial CSD and DA Algorithm." Irish Interdisciplinary Journal of Science & Research 07, no. 03 (2023): 81–89. http://dx.doi.org/10.46759/iijsr.2023.7309.

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Sureshbabu, J., and G. Saravanakumar. "A Radix-16 Booth Multiplier Based on Recoding Adder with Ultra High Power Efficiency and Reduced Complexity for Neuroimaging." Journal of Medical Imaging and Health Informatics 10, no. 4 (2020): 814–21. http://dx.doi.org/10.1166/jmihi.2020.2936.

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In the current medical developments the neuro imaging plays a vital role in the study of a human brain related disorders. The accuracy of the brain study is mainly dependent on the images created from the scanners at a rapid speed. In achieving this we need a high speed and low power consuming scanners. The current scenario in VLSI design, the scanners highly rely on a high speed Digital Signal Processor (DSP), which generally depends on the speed of a multiplier. Multipliers are considered as a more complex component when compared with adders. The current techniques provide greater access to
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Tang, Xiqin, Yang Li, Chenxiao Lin, and Delong Shang. "A Low-Power Area-Efficient Precision ScalableMultiplier with an Input Vector Systolic Structure." Electronics 11, no. 17 (2022): 2685. http://dx.doi.org/10.3390/electronics11172685.

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In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data input scheme is proposed to reduce the number of signal transitions. This structure is similar to a systolic array in matrix multiply units of a Convolutional Neural Network (CNN), but it reduces the number of processing elements by 3/4 concerning the same vector systolic accelerator in reference. Th
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Book chapters on the topic "Booth radix-16"

1

Dalal, Anshul, Manoj Choudhary, and S. Balamurugan. "Design Framework of 4-Bit Radix-4 Booth Multiplier Using Perpendicular Nanomagnetic Logic in MagCAD." In Communications in Computer and Information Science. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5048-2_31.

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Conference papers on the topic "Booth radix-16"

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Temel, Mertcan. "Formal Verification of Booth Radix-8 and Radix-16 Multipliers." In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2024. http://dx.doi.org/10.23919/date58400.2024.10546685.

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Adinarayana, T. V. S., G. Rajesh, Yashasvi Linga Reddy, Vishwass R. Yadav, and Srinivas Abhinay Gandla. "Design of a 16-Bit Power-Efficient Posit Multiplier with Selective Activation and Modified Radix-4 Booth Multiplier." In 2025 6th International Conference on Mobile Computing and Sustainable Informatics (ICMCSI). IEEE, 2025. https://doi.org/10.1109/icmcsi64620.2025.10883248.

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Ping-hua, Chen, and Zhao Juan. "High-speed Parallel 32×32-b Multiplier Using a Radix-16 Booth Encoder." In 2009 3rd International Symposium on Intelligent Information Technology Application Workshops (IITAW). IEEE, 2009. http://dx.doi.org/10.1109/iitaw.2009.44.

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Ramakrishna, A., N. Balaji, and P. Srihari. "An efficient and enhanced memory based FFT processor using radix 16 booth with carry skip adder." In 2016 International conference on Signal Processing, Communication, Power and Embedded System (SCOPES). IEEE, 2016. http://dx.doi.org/10.1109/scopes.2016.7955712.

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Vamsi, Hari Sai Ram, K. Srinivasa Reddy, C. Babu, and N. S. Murty. "Design of reversible logic based 32-bit MAC unit using radix-16 booth encoded wallace tree multiplier." In 2018 International Conference on Computer Communication and Informatics (ICCCI). IEEE, 2018. http://dx.doi.org/10.1109/iccci.2018.8441263.

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