Relevant bibliographies by topics / Branch prediction

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Branch prediction'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 January 2023

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Journal articles on the topic "Branch prediction"

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Fan, Hehe, Linchao Zhu, and Yi Yang. "Cubic LSTMs for Video Prediction." Proceedings of the AAAI Conference on Artificial Intelligence 33 (July 17, 2019): 8263–70. http://dx.doi.org/10.1609/aaai.v33i01.33018263.

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Predicting future frames in videos has become a promising direction of research for both computer vision and robot learning communities. The core of this problem involves moving object capture and future motion prediction. While object capture specifies which objects are moving in videos, motion prediction describes their future dynamics. Motivated by this analysis, we propose a Cubic Long Short-Term Memory (CubicLSTM) unit for video prediction. CubicLSTM consists of three branches, i.e., a spatial branch for capturing moving objects, a temporal branch for processing motions, and an output branch for combining the first two branches to generate predicted frames. Stacking multiple CubicLSTM units along the spatial branch and output branch, and then evolving along the temporal branch can form a cubic recurrent neural network (CubicRNN). Experiment shows that CubicRNN produces more accurate video predictions than prior methods on both synthetic and real-world datasets.
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Sendag, R., J. J. Yi, and Peng-fei Chuang. "Branch Misprediction Prediction: Complementary Branch Predictors." IEEE Computer Architecture Letters 6, no. 2 (February 2007): 49–52. http://dx.doi.org/10.1109/l-ca.2007.13.

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Ball, Thomas, and James R. Larus. "Branch prediction for free." ACM SIGPLAN Notices 28, no. 6 (June 1993): 300–313. http://dx.doi.org/10.1145/173262.155119.

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Jiménez, Daniel A. "Generalizing neural branch prediction." ACM Transactions on Architecture and Code Optimization 5, no. 4 (March 2009): 1–27. http://dx.doi.org/10.1145/1498690.1498692.

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Jimenez, Daniel A. "Piecewise Linear Branch Prediction." ACM SIGARCH Computer Architecture News 33, no. 2 (May 2005): 382–93. http://dx.doi.org/10.1145/1080695.1070002.

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Driesen, Karel, and Urs Hölzle. "Accurate indirect branch prediction." ACM SIGARCH Computer Architecture News 26, no. 3 (June 1998): 167–78. http://dx.doi.org/10.1145/279361.279380.

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Young, Cliff, and Michael D. Smith. "Static correlated branch prediction." ACM Transactions on Programming Languages and Systems 21, no. 5 (September 1999): 1028–75. http://dx.doi.org/10.1145/330249.330255.

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Seznec, Andre, Joshua San Miguel, and Jorge Albericio. "Practical Multidimensional Branch Prediction." IEEE Micro 36, no. 3 (May 2016): 10–19. http://dx.doi.org/10.1109/mm.2016.33.

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Hyesoon Kim, J. A. Joao, O. Mutlu, Chang Joo Lee, Y. N. Patt, and R. Cohn. "Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware." IEEE Transactions on Computers 58, no. 9 (September 2009): 1153–70. http://dx.doi.org/10.1109/tc.2008.227.

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Stark, Jared, Marius Evers, and Yale N. Patt. "Variable length path branch prediction." ACM SIGPLAN Notices 33, no. 11 (November 1998): 170–79. http://dx.doi.org/10.1145/291006.291042.

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Dissertations / Theses on the topic "Branch prediction"

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Hicks, Michael Andrew. "Energy efficient branch prediction." Thesis, University of Hertfordshire, 2010. http://hdl.handle.net/2299/4613.

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Energy efficiency is of the utmost importance in modern high-performance embedded processor design. As the number of transistors on a chip continues to increase each year, and processor logic becomes ever more complex, the dynamic switching power cost of running such processors increases. The continual progression in fabrication processes brings a reduction in the feature size of the transistor structures on chips with each new technology generation. This reduction in size increases the significance of leakage power (a constant drain that is proportional to the number of transistors). Particularly in embedded devices, the proportion of an electronic product’s power budget accounted for by the CPU is significant (often as much as 50%). Dynamic branch prediction is a hardware mechanism used to forecast the direction, and target address, of branch instructions. This is essential to high performance pipelined and superscalar processors, where the direction and target of branches is not computed until several stages into the pipeline. Accurate branch prediction also acts to increase energy efficiency by reducing the amount of time spent executing mis-speculated instructions. ‘Stalling’ is no longer a sensible option when the significance of static power dissipation is considered. Dynamic branch prediction logic typically accounts for over 10% of a processor’s global power dissipation, making it an obvious target for energy optimisation. Previous approaches at increasing the energy efficiency of dynamic branch prediction logic has focused on either fully dynamic or fully static techniques. Dynamic techniques include the introduction of a new cache-like structure that can decide whether branch prediction logic should be accessed for a given branch, and static techniques tend to focus on scheduling around branch instructions so that a prediction is not needed (or the branch is removed completely). This dissertation explores a method of combining static techniques and profiling information with simple hardware support in order to reduce the number of accesses made to a branch predictor. The local delay region is used on unconditional absolute branches to avoid prediction, and, for most other branches, Adaptive Branch Bias Measurement (through profiling) is used to assign a static prediction that is as accurate as a dynamic prediction for that branch. This information is represented as two hint-bits in branch instructions, and then interpreted by simple hardware logic that bypasses both the lookup and update phases for appropriate branches. The global processor power saving that can be achieved by this Combined Algorithm is around 6% on the experimental architectures shown. These architectures are based upon real contemporary embedded architecture specifications. The introduction of the Combined Algorithm also significantly reduces the execution time of programs on Multiple Instruction Issue processors. This is attributed to the increase achieved in global prediction accuracy.
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Alovisi, Pietro. "Static Branch Prediction through Representation Learning." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-277923.

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In the context of compilers, branch probability prediction deals with estimating the probability of a branch to be taken in a program. In the absence of profiling information, compilers rely on statically estimated branch probabilities, and state of the art branch probability predictors are based on heuristics. Recent machine learning approaches learn directly from source code using natural language processing algorithms. A representation learning word embedding algorithm is built and evaluated to predict branch probabilities on LLVM’s intermediate representation (IR) language. The predictor is trained and tested on SPEC’s CPU 2006 benchmark and compared to state-of-the art branch probability heuristics. The predictor obtains a better miss rate and accuracy in branch prediction than all the evaluated heuristics, but produces and average null performance speedup over LLVM’s branch predictor on the benchmark. This investigation shows that it is possible to predict branch probabilities using representation learning, but more effort must be put in obtaining a predictor with practical advantages over the heuristics.
Med avseende på kompilatorer, handlar branch probability prediction om att uppskatta sannolikheten att en viss förgrening kommer tas i ett program. Med avsaknad av profileringsinformation förlitar sig kompilatorer på statiskt upp- skattade branch probabilities och de främsta branch probability predictors är baserade på heuristiker. Den senaste maskininlärningsalgoritmerna lär sig direkt från källkod genom algoritmer för natural language processing. En algoritm baserad på representation learning word embedding byggs och utvärderas för branch probabilities prediction på LLVM’s intermediate language (IR). Förutsägaren är tränad och testad på SPEC’s CPU 2006 riktmärke och jämförd med de främsta branch probability heuristikerna. Förutsägaren erhåller en bättre frekvens av missar och träffsäkerhet i sin branch prediction har jämförts med alla utvärderade heuristiker, men producerar i genomsnitt ingen prestandaförbättring jämfört med LLVM’s branch predictor på riktmärket. Den här undersökningen visar att det är möjligt att förutsäga branch prediction probabilities med användande av representation learning, men att det behöver satsas mer på att få tag på en förutsägare som har praktiska övertag gentemot heuristiken.
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Bielby, Matthew Iain. "Ultra low power cooperative branch prediction." Thesis, University of Edinburgh, 2015. http://hdl.handle.net/1842/14187.

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Branch Prediction is a key task in the operation of a high performance processor. An inaccurate branch predictor results in increased program run-time and a rise in energy consumption. The drive towards processors with limited die-space and tighter energy requirements will continue to intensify over the coming years, as will the shift towards increasingly multicore processors. Both trends make it increasingly important and increasingly difficult to find effective and efficient branch predictor designs. This thesis presents savings in energy and die-space through the use of more efficient cooperative branch predictors achieved through novel branch prediction designs. The first contribution is a new take on the problem of a hybrid dynamic-static branch predictor allocating branches to be predicted by one of its sub-predictors. A new bias parameter is introduced as a mechanism for trading off a small amount of performance for savings in die-space and energy. This is achieved by predicting more branches with the static predictor, ensuring that only the branches that will most benefit from the dynamic predictor’s resources are predicted dynamically. This reduces pressure on the dynamic predictor’s resources allowing for a smaller predictor to achieve very high accuracy. An improvement in run-time of 7-8% over the baseline BTFN predictor is observed at a cost of a branch predictor bits budget of much less than 1KB. Next, a novel approach to branch prediction for multicore data-parallel applications is presented. The Peloton branch prediction scheme uses a pack of cyclists as an illustration of how a group of processors running similar tasks can share branch predictions to improve accuracy and reduce runtime. The results show that sharing updates for conditional branches across the existing interconnect for I-cache and D-cache updates results in a reduction of mispredictions of up to 25% and a reduction in run-time of up to 6%. McPAT is used to present an energy model that suggests the savings are achieved at little to no increase in energy required. The technique is then extended to architectures where the size of the branch predictors may differ between cores. The results show that such heterogeneity can dramatically reduce the die-space required for an accurate branch predictor while having little impact on performance and up to 9% energy savings. The approach can be combined with the Peloton branch prediction scheme for reduction in branch mispredictions of up to 5%.
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GAO, HONGLIANG. "IMPROVING BRANCH PREDICTION ACCURACY VIA EFFECTIVE SOURCE INFORMATION AND PREDICTION ALGORITHMS." Doctoral diss., University of Central Florida, 2008. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3286.

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Modern superscalar processors rely on branch predictors to sustain a high instruction fetch throughput. Given the trend of deep pipelines and large instruction windows, a branch misprediction will incur a large performance penalty and result in a significant amount of energy wasted by the instructions along wrong paths. With their critical role in high performance processors, there has been extensive research on branch predictors to improve the prediction accuracy. Conceptually a dynamic branch prediction scheme includes three major components: a source, an information processor, and a predictor. Traditional works mainly focus on the algorithm for the predictor. In this dissertation, besides novel prediction algorithms, we investigate other components and develop untraditional ways to improve the prediction accuracy. First, we propose an adaptive information processing method to dynamically extract the most effective inputs to maximize the correlation to be exploited by the predictor. Second, we propose a new prediction algorithm, which improves the Prediction by Partial Matching (PPM) algorithm by selectively combining multiple partial matches. The PPM algorithm was previously considered optimal and has been used to derive the upper limit of branch prediction accuracy. Our proposed algorithm achieves higher prediction accuracy than PPM and can be implemented in realistic hardware budget. Third, we discover a new locality existing between the address of producer loads and the outcomes of their consumer branches. We study this address-branch correlation in detail and propose a branch predictor to explore this correlation for long-latency and hard-to-predict branches, which existing branch predictors fail to predict accurately.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Computer Science PhD
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Egan, Colin. "Dynamic branch prediction in high performance superscalar processors." Thesis, University of Hertfordshire, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.340035.

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Thankappan, Achary Retnamma Renjith. "Broadcast Mechanism for improving Conditional Branch Prediction in Speculative Multithreaded Processors." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/368.

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ABSTRACT Many aspects of speculative multithreading have been under constant and crucial research in the recent times with the increased importance in exploiting parallelism in single thread applications. One of the important architectural optimizations that is very pertinent in this scenario is branch prediction. Branch Prediction assumes increased importance for multi-threading systems that execute threads speculatively, since wrong predictions can be much costlier here, in terms of threads, than a few instructions that occupy the pipeline in a uni-processor. Conventional branch prediction techniques have provided increasingly better prediction accuracies for uni-core processing. But the branch prediction itself takes on a whole new dimension when applied to multi-core architectures based on Speculative Multithreading. Dependence on global branch history has helped branch predictors to achieve high prediction accuracy in single thread applications. The discontinuity of global history created at the thread boundaries cripple the performance of branch predictors in a multi-threaded environment. Many studies in the past have tried to address the branch history problem to improve the prediction accuracy. Most of these have been found either to be architecture specific or complex in terms of the hardware needed to recreate or approximate the right history to be given to the threads when they start executing out of order. This hardware overhead increases as the number and size of threads increase thereby limiting the scalability of the algorithms proposed so far. The current thesis takes a different direction and proposes a simple and scalable solution to effectively reduce the misprediction rates in Speculative Multithreaded systems. This is accomplished by making use of a synergistic interaction between threads to boost the inherent biased nature of branches and using less complex hardware to reduce aliasing between branches in the threads. The study proposes a new scheme called the Global Broadcast Buffer scheme to effectively reduce branch mispredictions in Speculative Multithreaded architectures.
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Simon, Elizabeth A. "Turning predicate information to advantage to improve compiler scheduling and branch prediction /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2002. http://wwwlib.umi.com/cr/ucsd/fullcit?p3036988.

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Tarlescu, Maria-Dana. "The Elastic History Buffer, a multi-hybrid branch prediction scheme using static classification." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape7/PQDD_0025/MQ50893.pdf.

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Belyaeva, Elena. "On a new logistic regression model for bankruptcy prediction in the IT branch." Thesis, Uppsala universitet, Analys och sannolikhetsteori, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-242789.

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Lind, Tobias. "Evaluation of Instruction Prefetch Methods for Coresonic DSP Processor." Thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129128.

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With increasing demands on mobile communication transfer rates the circuits in mobile phones must be designed for higher performance while maintaining low power consumption for increased battery life. One possible way to improve an existing architecture is to implement instruction prefetching. By predicting which instructions will be executed ahead of time the instructions can be prefetched from memory to increase performance and some instructions which will be executed again shortly can be stored temporarily to avoid fetching them from the memory multiple times. By creating a trace driven simulator the existing hardware can be simulated while running a realistic scenario. Different methods of instruction prefetch can be implemented into this simulator to measure how they perform. It is shown that the execution time can be reduced by up to five percent and the amount of memory accesses can be reduced by up to 25 percent with a simple loop buffer and return stack. The execution time can be reduced even further with the more complex methods such as branch target prediction and branch condition prediction.
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Books on the topic "Branch prediction"

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York, Richard. Branch prediction strategies for low power microprocessor design. Manchester: Universityof Manchester, 1994.

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Man zhi gou zao cheng kuang ji shen bu zhao kuang yu ce: Manzhi gouzao chengkuang ji shenbu zhaokuang yuce = Mantle branch structures mineralization and depth prospecting prediction. Beijing: Di zhi chu ban she, 2010.

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Stephens, Debra Lynn. Predicting post-advertisement attitudes. Cambridge, Mass: Marketing Science Institute, 1992.

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Stephens, Debra Lynn. Predicting post-advertisement attitudes. Cambridge, Mass: Marketing Science Institute, 1992.

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Stephens, Debra Lynn. Predicting post-advertisement attitudes. Cambridge, Mass: Marketing Science Institute, 1992.

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Pachurin, German. Technology for studying the destruction of structural materials under different loading conditions. ru: INFRA-M Academic Publishing LLC., 2021. http://dx.doi.org/10.12737/981296.

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The textbook is devoted to solving topical issues related to the prediction of the effect of plastic deformation on the behavior in various operating conditions of a wide class of metals and alloys. The technology developed by the author for studying the mechanical properties and the process of destruction of plastically treated metal materials under various loading conditions (static at different temperatures, cyclic in air at low, room and elevated temperatures, as well as at room temperature in the presence of a corrosive environment) is described. Meets the requirements of the federal state educational standards of higher education of the latest generation. Addressed to bachelors and undergraduates of higher educational institutions of full-time and part-time education in the areas of training 20.03.01 Technosphere safety" (training profile "Safety of technological processes and production"), 22.03.01 and 22.04.01 "Materials Science and Materials Technology", 22.03.02 and 22.04.02 "Metallurgy", 15.03.01 and 15.04.01 "Mechanical Engineering", 15.05.01 "Design of technological machines and complexes", 15.03.02 "Technological machines and equipment", 15.03.04 and 15.04.04 "Automation of technological processes and production", 17.05.02 "Strelkovo-pushechnoe, artillery and rocket weapons", 15.03.05 "Design and technological support of machine-building industries". It can be useful for scientific and engineering workers of enterprises of automotive, aviation, shipbuilding and other metalworking branches of mechanical engineering, laboratory workers, as well as for training specialists in materials science, metal science and metal forming."
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Russell, John M. Final report submitted to the National Aeronautics and Space Administration, Shuttle Contract Office, Processing and Consumables Branch, entitled Development and verification of methods for predicting flow rates through leaks in valves and couplings. Melbourne, Fla: Florida Institute of Technology, Office of Sponsored Programs, 1993.

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Wessinger, Catherine. Collective Martyrdom and Religious Suicide. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780190656485.003.0004.

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The Branch Davidians and Heaven’s Gate, two religious groups marked by apocalyptic worldviews, are compared to elucidate two types of trajectories of apocalyptic groups involved in violence. The Branch Davidians expected to be martyred based on David Koresh’s interpretations of the Bible’s prophecies about the events of the Last Days. Therefore, in 1993 they regarded assaults against their community by federal agents as verifying Koresh’s predictions. In 1997, the Heaven’s Gate “class” carried out what they regarded as an “exit” to The Level Above Human (TELAH) by implementing a collective religious suicide. In both cases, the interactions of outsiders with the group contributed to the resulting loss of life, although internal factors were more predominant in the case of Heaven’s Gate. The members of both groups lived and died in accordance with their respective worldviews and understandings of salvation.
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Lucander, David. “An Economic D-Day for Negro Americans”. University of Illinois Press, 2017. http://dx.doi.org/10.5406/illinois/9780252038624.003.0006.

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This chapter examines the role of St. Louis March on Washington Movement (MOWM) in petitioning the Fair Employment Practice Committee (FEPC) to open a branch in the city. Making the FEPC a permanent agency within the federal government was thought to be key to keeping the precarious inroads made by black workers during the war and avoiding another round of hardship that mirrored the Great Depression. By 1949, it was clear that predictions of massive postwar job losses were tragically accurate. It seemed as if securing a federal fair employment law was the most effective way to safeguard the dwindling opportunities for gainful work, so the push for a Permanent FEPC became the centerpiece of A. Philip Randolph's program. The impact of a greater FEPC presence on the employment prospects of African American workers and job seekers is difficult to quantify, but once this office opened, MOWM redirected its energies toward helping that agency remediate racist employment patterns.
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Flock and Flow: Predicting and Managing Change in a Dynamic Marketplace. Indiana University Press, 2006.

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Book chapters on the topic "Branch prediction"

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Rebeiro, Chester, Debdeep Mukhopadhyay, and Sarani Bhattacharya. "Branch Prediction Attacks." In Timing Channels in Cryptography, 125–37. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-12370-7_9.

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Acıiçmez, Onur, Çetin Kaya Koç, and Jean-Pierre Seifert. "Predicting Secret Keys Via Branch Prediction." In Lecture Notes in Computer Science, 225–42. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11967668_15.

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Ramirez, Alex, Josep L. Larriba-Pey, and Mateo Valero. "Branch Prediction Using Profile Data." In Euro-Par 2001 Parallel Processing, 386–94. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44681-8_57.

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He, Liqiang, and Guangyong Zhang. "Parallel Branch Prediction on GPU Platform." In Lecture Notes in Computer Science, 153–60. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11842-5_20.

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Aragón, Juan L., José González, José M. García, and Antonio González. "Confidence Estimation for Branch Prediction Reversal." In High Performance Computing — HiPC 2001, 214–23. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-45307-5_19.

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Veidenbaum, Alexander V. "Instruction cache prefetching using multilevel branch prediction." In Lecture Notes in Computer Science, 51–70. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/bfb0024203.

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Santana, Oliverio J., Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, and Mateo Valero. "A Comprehensive Analysis of Indirect Branch Prediction." In Lecture Notes in Computer Science, 133–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-47847-7_13.

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Iwama, Chitaka, Niko Demus Barli, Shuichi Sakai, and Hidehiko Tanaka. "Improving Conditional Branch Prediction on Speculative Multithreading Architectures." In Euro-Par 2001 Parallel Processing, 413–17. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44681-8_60.

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Thomas, Renju, and Manoj Franklin. "Using Dataflow Based Context for Accurate Branch Prediction." In High Performance Computing — HiPC 2002, 587–96. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-36265-7_55.

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Farooq, Muhammad Umar, Lei Chen, and Lizy Kurian John. "Compiler Support for Value-Based Indirect Branch Prediction." In Lecture Notes in Computer Science, 185–99. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-28652-0_10.

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Conference papers on the topic "Branch prediction"

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Farooq, M. U., K. Khubaib, and L. K. John. "Store-Load-Branch (SLB) predictor: A compiler assisted branch prediction for data dependent branches." In 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2013. http://dx.doi.org/10.1109/hpca.2013.6522307.

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Pruett, Stephen, and Yale Patt. "Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches." In MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3466752.3480053.

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Ball, Thomas, and James R. Larus. "Branch prediction for free." In the ACM SIGPLAN 1993 conference. New York, New York, USA: ACM Press, 1993. http://dx.doi.org/10.1145/155090.155119.

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Chaver, Daniel, Luis Piñuel, Manuel Prieto, Francisco Tirado, and Michael C. Huang. "Branch prediction on demand." In the 2003 international symposium. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/871506.871603.

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Sendag, Resit, Joshua J. Yi, Peng-fei Chuang, and David J. Lilja. "Low power/area branch prediction using complementary branch predictors." In Distributed Processing Symposium (IPDPS). IEEE, 2008. http://dx.doi.org/10.1109/ipdps.2008.4536323.

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Zhou, Zihao, Mayank Kejriwal, and Risto Miikkulainen. "Extended scaled neural predictor for improved branch prediction." In 2013 International Joint Conference on Neural Networks (IJCNN 2013 - Dallas). IEEE, 2013. http://dx.doi.org/10.1109/ijcnn.2013.6707059.

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Monchiero, M., G. Palermo, M. Sami, C. Silvano, V. Zaccaria, and R. Zafalon. "Power-aware branch prediction techniques." In Proceedins of the 14th ACM Great Lakes symposium. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/988952.989058.

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Sadooghi-Alvandi, M., K. Aasaraai, and A. Moshovos. "Toward virtualizing branch direction prediction." In 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012). IEEE, 2012. http://dx.doi.org/10.1109/date.2012.6176514.

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Calder, Brad, Dirk Grunwald, Donald Lindsay, James Martin, Michael Mozer, and Benjamin Zorn. "Corpus-based static branch prediction." In the ACM SIGPLAN 1995 conference. New York, New York, USA: ACM Press, 1995. http://dx.doi.org/10.1145/207110.207118.

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Bermingham, David, Zhen Liu, Xiaojun Wang, and Bin Liu. "Branch prediction for network processors." In 2008 International Conference on Microelectronics - ICM. IEEE, 2008. http://dx.doi.org/10.1109/icm.2008.5393519.

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Reports on the topic "Branch prediction"

1

Hemmert, K. Scott, and D. Eric Johnson. Toward improved branch prediction through data mining. Office of Scientific and Technical Information (OSTI), September 2009. http://dx.doi.org/10.2172/993886.

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Ponder, C. G., and M. C. Shebanow. An information-theoretic look at branch-prediction. Office of Scientific and Technical Information (OSTI), September 1990. http://dx.doi.org/10.2172/6569918.

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Thankappan Achary Retnamma, Renjith. Broadcast Mechanism for improving Conditional Branch Prediction in Speculative Multithreaded Processors. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.368.

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Cerviño, Julio, and Jaime Rivera-Camino. A model for predicting attitudes towards spanish product, brands and country image: An exploratory international study. CENTRUM Catolica Graduate Business School, December 2015. http://dx.doi.org/10.7835/ccwp-2015-12-0026.

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Sadachar, Amrut, and Swagata Chakraborty. Investigating the Role of Western Acculturation, Ethnocentrism, and Consumer Cosmopolitanism in Predicting Preferences for Apparel Brands Among Indian Consumers. Ames (Iowa): Iowa State University. Library, January 2019. http://dx.doi.org/10.31274/itaa.8442.

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