Log in

Relevant bibliographies by topics / Brent-Kung adder / Journal articles

To see the other types of publications on this topic, follow the link: Brent-Kung adder.

Journal articles on the topic 'Brent-Kung adder'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Brent-Kung adder.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

reddy*, M. Ramana. "Design of Static CMOS 16 Bit High Speeds and Low Power Consumption Hybrid Adder Circuit using Brent Kung Adder." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 6 (2020): 300–310. http://dx.doi.org/10.35940/ijrte.e6559.038620.

Full text

Abstract:

This paper presents a static sixteen Bit CMOS Brent kung adder shape was designed, which famous a higher pace and decrease strength intake in comparison with those of the ripple deliver adders. The pace enhancement changed into done through modifying the shape through thru adding a Brent Kung adder, complete adders the usage of (28 transistor, Boolean exact judgment) that is masses speeder whilst in comparison to ripple supply adder and These pace adders will bring about growth in DSP processors. The time delays and power consumptions are lots much less with unique adders with the aid of imple

APA, Harvard, Vancouver, ISO, and other styles

2

RH, Naik, Ganesh D, Lakshmi Tirupathamma M, Siva Sai K, and Venkateswarlu D. "Optimized FFA-Based 3-Parallel Polyphase FIR Filter Using Modified Brent-Kung Adder and Booth Multiplier for VLSI Applications." International Journal for Modern Trends in Science and Technology 11, no. 03 (2025): 128–35. https://doi.org/10.5281/zenodo.15084889.

Full text

Abstract:

Digital Signal Processing (DSP) plays a crucial role in biomedical applications, as well as in voice and image processing. Digital filters serve as fundamental building blocks for DSP applications, signal analysis, and estimation. With advancements in VLSI technology, the complexity of designing digital filters has been significantly reduced, enabling efficient on-chip architectures for DSP applications.Finite Impulse Response (FIR) filters, which have a finite-duration impulse response, are widely used in DSP systems due to their stability and linear-phase characteristics, in contrast to Infi

APA, Harvard, Vancouver, ISO, and other styles

3

Shaik, Maznu. "Design and Performance Evaluation of Brent Kung Adder based 8-Bit Vedic Multiplier." International Journal for Research in Applied Science and Engineering Technology 12, no. 12 (2024): 825–30. https://doi.org/10.22214/ijraset.2024.65922.

Full text

Abstract:

Multiplier is an essential functional block of a microprocessor because multiplication is needed to be performed repeatedly in almost all scientific calculations. Therefore, design of fast and low power binary multiplier is very important particularly for Digital Signal Processors. Vedic mathematics has improved the performance of multiplier. Vedic mathematics, a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably comp

APA, Harvard, Vancouver, ISO, and other styles

4

Mahammad, Masood Ahmad, Appala Raju Uppala, Suggala Ram Prasad, and Anusha Marouthu. "Performance analysis of parallel prefix adders developed with field programmable gate array technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 109. https://doi.org/10.11591/ijres.v14.i1.pp109-116.

Full text

Abstract:

In many digital systems like high-performance computing and digital signal processing, parallel prefix adders are vital. Field programmable gate array (FPGA) technology is a well-known platform for developing parallel prefix adders. FPGA performance depends on bit size of the adder, the adder structure chosen, and the implementation specifications. An examination of the performance and area of parallel prefix adders developed using FPGA technology is presented in this research work. We look into how different design factors, such as the adder structure and the number of input bits, affect the

APA, Harvard, Vancouver, ISO, and other styles

5

Mahammad, Masood Ahmad, Appala Raju Uppala, Ram Prasad Suggala, and Anusha Marouthu. "Performance analysis of parallel prefix adders developed with field programmable gate array technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 109–16. https://doi.org/10.11591/ijres.v14.i1.pp109-116.

Full text

Abstract:

In many digital systems like high-performance computing and digital signal processing, parallel prefix adders are vital. Field programmable gate array (FPGA) technology is a well-known platform for developing parallel prefix adders. FPGA performance depends on bit size of the adder, the adder structure chosen, and the implementation specifications. An examination of the performance and area of parallel prefix adders developed using FPGA technology is presented in this research work. We look into how different design factors, such as the adder structure and the number of input bits, affect the

APA, Harvard, Vancouver, ISO, and other styles

6

R, Anjali, Sorna Marium R, Sujithra M, and Mariammal K. "Fault-Resilient Brent-Kung Adder Design Using Advanced Built-in Self-Test (BIST) Architecture." Journal of Electronics and Informatics 7, no. 1 (2025): 1–18. https://doi.org/10.36548/jei.2025.1.001.

Full text

Abstract:

In modern digital systems, ensuring both high performance and reliability is essential, especially in fault-sensitive environments. This research introduces the design and implementation of a fault-tolerant Brent-Kung adder, integrated with an advanced Built-In Self-Test (BIST) framework. The Brent-Kung adder, known for its efficient carry propagation and speed optimization, is augmented with BIST techniques to enhance its reliability and testability in digital systems. A Linear Feedback Shift Register (LFSR) is used to produce pseudo-random test patterns, while a Multiple Input Signature Regi

APA, Harvard, Vancouver, ISO, and other styles

7

Pushpalatha, B., T. Pavani, and A. Ushasree. "Efficient stable-width adder-sapling strategy using Brent Kung adder." Materials Today: Proceedings 42 (2021): 1492–97. http://dx.doi.org/10.1016/j.matpr.2021.01.443.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Prihozhy, A. A. "Synthesis of parallel adders from if-decision diagrams." «System analysis and applied information science», no. 2 (August 18, 2020): 61–70. http://dx.doi.org/10.21122/2309-4923-2020-2-61-70.

Full text

Abstract:

Addition is one of the timing critical operations in most of modern processing units. For decades, extensive research has been done devoted to designing higher speed and less complex adder architectures, and to developing advanced adder implementation technologies. Decision diagrams are a promising approach to the efficient many-bit adder design. Since traditional binary decision diagrams does not match perfectly with the task of modelling adder architectures, other types of diagram were proposed. If-decision diagrams provide a parallel many-bit adder model with the time complexity of Ο(log2n)

APA, Harvard, Vancouver, ISO, and other styles

9

Harish, Basavoju, Rukmini M.S.S., and Sivani K. "HIGH PERFORMANCE FIR FILTER BASED ON PIPELINED PARALLEL PREFIX ADDER FOR SIGNAL PROCESSING APPLICATIONS." ICTACT Journal on Microelectronics 8, no. 2 (2022): 1334–37. https://doi.org/10.21917/ijme.2022.0230.

Full text

Abstract:

Multiple adders and multipliers make up a complex digital signal processing system (DSP). The efficient design of adders and multipliers improves the DSP system performance. In this paper, modified 4-Tap digital Finite Impulse Response (FIR) filter is built using the Pipelined Brent-Kung adder (PBKA) and a Vedic multiplier. The top-level module (FIR filter) is created by writing PBKA and PBKA-based Vedic multiplier Verilog code. The results of Pipelined Brent Kung adderbased FIR filter are compared with BKA and KSA-based 4-Tap digital FIR filter. According to the synthesis results, the PBKA-ba

APA, Harvard, Vancouver, ISO, and other styles

10

Sivadurgarao, Parasa, Naga Venkata Tejaswini Paruchuri, Huzaifa Mohammad, Vardhini Vagu, Geethika Pakalapati, and Taraka Rama Shanmukh Sai Segu. "Design and validation of low power, high performance parallel prefix adders." i-manager’s Journal on Electronics Engineering 15, no. 3 (2025): 48. https://doi.org/10.26634/jele.15.3.21813.

Full text

Abstract:

In the realm of designing digital systems through Very Large Scale Integration (VLSI), the digital adder takes center stage. However, low-power VLSI adder designs grapple with the Propagation Delay issue, leading to increased latency. This paper explores the viability of Parallel Prefix Adders (PPA) in addressing these challenges for low-power VLSI designs, emphasizing minimal propagation latency. The paper delves into the design and analysis of select PPA models, comparing their performance in terms of area, delay, and power. Utilizing Xilinx Vivado 2019.1, this study evaluates four prominent

APA, Harvard, Vancouver, ISO, and other styles

11

Neeraja, P. K., and Narayanadass Ramadass. "A Modified Fused Floating Point Three Term Adder." International Journal of Engineering and Advanced Technology (IJEAT) 10, no. 1 (2020): 415–19. https://doi.org/10.35940/ijeat.A1908.1010120.

Full text

Abstract:

This paper is about a modified architecture for a fused floating point three term adder. The important feature of a fused floating-point three-term adder is its ability to do multiple additions in same block to get better performance as well as accuracy compared to a conventional discrete floating point adder. The parallel prefix adder is one amongst the fastest adders and out of which the han-carlson adder represents a blend of the kogge-stone adders and brent-kung adder. In this work, han carlson adder is used to enhance the performance of the three term adder along with various optimization

APA, Harvard, Vancouver, ISO, and other styles

12

R, Arul. "Rounding Multiplier to Improve the efficiency using Brent Kung Adder." International Journal for Research in Applied Science and Engineering Technology 7, no. 4 (2019): 307–11. http://dx.doi.org/10.22214/ijraset.2019.4055.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Kowsalya, P., M. Malathi, and Palaniappan Ramanathan. "Low Power Parallel Prefix Adder." Applied Mechanics and Materials 573 (June 2014): 194–200. http://dx.doi.org/10.4028/www.scientific.net/amm.573.194.

Full text

Abstract:

Addition is a fundamental operation of all Arithmetic and Logic Units (ALU).The speed of addition operation decides the computational frequency of ALU. In order to improve the performance of the binary adder, the parallel prefix adder are preferred. There are various parallel prefix adders available. This work focuses on designing 8-bit prefix adders such as Brent Kung ,Kogge Stone and Sklansky adders using GDI technique. The performance of these GDI based prefix adders are compared with that of CMOS based prefix adder. GDI based prefix adders out performs CMOS based prefix adders in terms of

APA, Harvard, Vancouver, ISO, and other styles

14

Researcher. "LOW POWER HIGH SPEED HANS CARLSON ADDER USING SPST." International Journal of Applied Electronics (IJAE) 5, no. 2 (2024): 1–10. https://doi.org/10.5281/zenodo.13381981.

Full text

Abstract:

The concept of SPST is to segregate the arithmetic units into Most significant Part (MSP) & Least significant Part (LSP), where MSP doesn’t affect most of computation results. Efficient adders are beneficial in the arithmetic circuit design. Ripple carry adder was found to have lowest gate count but maximum delay. To address the area and delay, a high speed low power Han Carlson adder adopting SPST is proposed in this part of process. Hans Carlson adder’s is coalescence of two designs comprising Kogge-stone and the Brent-Kung construction. The Xilinx- Vivado tool was used to si

APA, Harvard, Vancouver, ISO, and other styles

15

Dr., Vasudeva G. "Floating Point Unit with High Precision Efficiency." International Journal of Soft Computing and Engineering (IJSCE) 15, no. 2 (2025): 24–30. https://doi.org/10.35940/ijsce.B3669.15020525.

Full text

Abstract:

<strong>Abstract:</strong> In this paper, we dive into the design of a Single Precision Floating Point Unit (FPU), a key player in the world of modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in areas like scientific research, graphics rendering, and machine learning. Our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The Brent-Kung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel- prefix structure, it keeps del

APA, Harvard, Vancouver, ISO, and other styles

16

S, Dhasarathan. "LOW POWER CIRCUIT FOR BRENT-KUNG ADDER BASED ON ADIABATIC LOGIC." International Journal of Advances in Signal and Image Sciences 4, no. 1 (2018): 8. http://dx.doi.org/10.29284/ijasis.4.1.2018.8-15.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Naga Babu, Ch, P. Naga Siva Sai, Ch Priyanka, K. Hari Kishore, M. Bindu Bhargavi, and K. Karthik. "Comparative Analysis of High Speed Carry Skip Adders." International Journal of Engineering & Technology 7, no. 2.24 (2018): 121. http://dx.doi.org/10.14419/ijet.v7i2.24.12015.

Full text

Abstract:

In this paper we compared a high speed carry skip adders by considering parameters such as area, LUT’S, delay, power. When compared to conventional CSKA and other adders. Here in this project in first stage CSKA designed by using multiplexer as skip logic so by using this speed gets increased by skipping of carry. so here area gets increased so to reduce area another hybrid variable latency carry skip adder(Brent-kung adder) is designed .here power utilization also gets decreased, speed gets increased, but some delay is produced here to overcome that we followed a another method called Kogge-S

APA, Harvard, Vancouver, ISO, and other styles

18

Mohith, M. S. N. V., Dr S. Ravi, K. Yaswanth Simha, L. Alekhya, and M. Maruthi Sriram. "A Novel High Performance Architecture for Mac Unit Using Vedic Multiplier and Brent-Kung Adder." International Journal of Research and Scientific Innovation XII, no. IV (2025): 202–10. https://doi.org/10.51244/ijrsi.2025.12040021.

Full text

Abstract:

The DSP industries make use of Multiply and Accumulate (MAC) units in their systems unanimously. As the name implies, MAC unit performs both Multiplication and addition operations. The proposed MAC unit make use of parallel prefix adder, instead of ripple carry adder, and hence there is an improvement in the performance of the DSP processors. Further, this paper also examines the performance by using Brent-Kung adder, one of the high-speed adders which is used to reduce the delay of MAC units. To enhance the performance of multiplication process, the proposed design uses a Vedic multiplier, ba

APA, Harvard, Vancouver, ISO, and other styles

19

G, Vasudeva, and Bharathi Gururaj. "Design of an Efficient Single Precision Floating Point Unit." International Journal of Electrical Engineering and Computer Science 7 (March 26, 2025): 44–54. https://doi.org/10.37394/232027.2025.7.5.

Full text

Abstract:

In this , we design of a Single Precision Floating Point Unit (FPU), a key player in the world of modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in areas like scientific research, graphics rendering, and machine learning. Our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The Brent-Kung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel- prefix structure, it keeps delays minimal even as the numbers get bigger. Fo

APA, Harvard, Vancouver, ISO, and other styles

20

Abbas, Abdulkareem Dawah. "Review of high-speed phase accumulator for direct digital frequency synthesizer." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (2020): 4008. http://dx.doi.org/10.11591/ijece.v10i4.pp4008-4014.

Full text

Abstract:

A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW

APA, Harvard, Vancouver, ISO, and other styles

21

Abdulkareem, Dawah Abbas. "Review of high-speed phase accumulator for direct digital frequency synthesizer." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (2020): 4008–14. https://doi.org/10.11591/ijece.v10i4.pp4008-4014.

Full text

Abstract:

A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent-Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW

APA, Harvard, Vancouver, ISO, and other styles

22

Govindaraj, Prabakaran, Shanmugasundaram Nallasamy, Mohankumar Mylsamy, and Sathiyapriya Krishnamoorthy. "DESIGN AND ANALYSIS OF NOVEL PARALLEL PREFIX ADDERS FOR VLSI CIRCUITS." Suranaree Journal of Science and Technology 31, no. 1 (2024): 010276(1–8). http://dx.doi.org/10.55766/sujst-2024-01-e0379.

Full text

Abstract:

Arithmetic Logic Unit is the brain of all processors, is composed of an Adder circuit. The main component of multiplier circuits is the adder, which performs subtraction (by 2’s complement arithmetic). Since the most fundamental operation in mathematics is addition, and the adder is the most essential part of the processor, the study of VLSI arithmetic has required many digital VLSI researchers. When designing digital systems employing the VLSI approach, the digital adder plays a major role. Low power VLSI based adder designs perform poorly because of the propagation delay issue. With the aid

APA, Harvard, Vancouver, ISO, and other styles

23

S, Gomathi. "Design of Adaptive Filter for Biosignal Noise Cancellation Using Brent Kung Adder." International Journal of Emerging Trends in Engineering Research 8, no. 7 (2020): 3111–15. http://dx.doi.org/10.30534/ijeter/2020/38872020.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

B Gowda, Ranjith, and R. M Banakar. "Design of high speed low power optimized square root BK adder." International Journal of Engineering & Technology 7, no. 2.12 (2018): 240. http://dx.doi.org/10.14419/ijet.v7i2.12.11289.

Full text

Abstract:

Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these t

APA, Harvard, Vancouver, ISO, and other styles

25

Anagani, Vamsidhar, Kasi Geethanjali, Anusha Gorantla, and Annamreddy Devi. "An improved approximate parallel prefix adder for high performance computing applications: a comparative analysis." International Journal of Informatics and Communication Technology (IJ-ICT) 14, no. 2 (2025): 382. https://doi.org/10.11591/ijict.v14i2.pp382-392.

Full text

Abstract:

Binary adders are fundamental in digital circuit designs, including digital signal processors and microprocessor data path units. Consequently, significant research has focused on improving adders’ power-delay efficiency. The carry tree adder (CTA) is alternatively referred to as the parallel prefix adder (PPA), is among the fastest adders, achieving superior performance in very large scale integrated (VLSI) implementations through efficient concurrent carry generation and propagation. This study introduces approximate PPAs (AxPPAs) by applying approximations in prefix operators (POs). Four ty

APA, Harvard, Vancouver, ISO, and other styles

26

Yagain, Deepa, Vijaya Krishna A, and Akansha Baliga. "Design of High-Speed Adders for Efficient Digital Design Blocks." ISRN Electronics 2012 (September 26, 2012): 1–9. http://dx.doi.org/10.5402/2012/253742.

Full text

Abstract:

The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and

APA, Harvard, Vancouver, ISO, and other styles

27

Deepak, Kumar Athur, Narayanan Bhuvanesh, Gopalakrishnan Amshuman, Palanisamy Sasipriya, and Angeline Augustine Anita. "Design of novel high speed parallel prefix adder." Design of novel high speed parallel prefix adder 29, no. 3 (2023): 1345–54. https://doi.org/10.11591/ijeecs.v29.i3.pp1345-1354.

Full text

Abstract:

Adders are crucial logical building blocks found almost in all the modern electronic system designs. In the adder architecture design, the fundamental issue is the propagation latency in the carry chain. As the length of the input operands increases, the length of the carry chain along with it. Parallel prefix adders, which address the problem of carry propagation in adders, are the most efficient adder topologies for hardware implementation. However, delay reduction still could be achieved for very high speed applications. Hence, in this paper design of 16bit novel parallel prefix adder is pr

APA, Harvard, Vancouver, ISO, and other styles

28

Suguna, T., and M. Janaki Rani. "Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications." International Journal of Interactive Mobile Technologies (iJIM) 14, no. 05 (2020): 73. http://dx.doi.org/10.3991/ijim.v14i05.13343.

Full text

Abstract:

In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL

APA, Harvard, Vancouver, ISO, and other styles

29

Jaya, Koshta Kavita Khare and M.K Gupta. "EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON FPGA." International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.2, April 2019 10, no. 2 (2019): 01–12. https://doi.org/10.5281/zenodo.3442142.

Full text

Abstract:

Video Compression is very essential to meet the technological demands such as low power, less memory and fast transfer rate for different range of devices and for various multimedia applications. Video compression is primarily achieved by Motion Estimation (ME) process in any video encoder which contributes to significant compression gain.Sum of Absolute Difference (SAD) is used as distortion metric in ME process.In this paper, efficient Absolute Difference(AD)circuit is proposed which uses Brent Kung Adder(BKA) and a comparator based on modified 1’s complement principle and conditional

APA, Harvard, Vancouver, ISO, and other styles

30

Bache, Florian, and Tim Güneysu. "Boolean Masking for Arithmetic Additions at Arbitrary Order in Hardware." Applied Sciences 12, no. 5 (2022): 2274. http://dx.doi.org/10.3390/app12052274.

Full text

Abstract:

Modular addition is an important component of many cryptographic algorithms such as ARX-ciphers and lattice-based post-quantum secure schemes. In order to protect devices that execute these algorithms against side-channel attacks, countermeasures such as masking must be applied. However, if an implementation needs to be secured against multivariate attacks, univariately secure masking schemes do not suffice. In this work, we focus on hardware architectures for higher-order masked addition circuits. We present and discuss three adder designs that are protected with a provably secure masking sch

APA, Harvard, Vancouver, ISO, and other styles

31

L S a, Ravi. "Analysis of Low Power High Speed Parallel Prefix Adder Using Cadence Encounter Platform." INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 04 (2025): 1–9. https://doi.org/10.55041/ijsrem46598.

Full text

Abstract:

I. ABSTRACT High performance in the age of lightning-fast computing and energy-efficient electrical devices depends on the creation of optimised arithmetic units. The efficiency of adders, which are crucial components of the majority of digital systems, has a direct effect on the system's overall speed and power usage. In this study, a low-power, high-speed parallel prefix adder (PPA) architecture leveraging Cadence nclaunch is designed and implemented. In terms of gates, power, and area, prefixes topologies such as Brent-Kung and Kogge-Stone are examined and contrasted. The suggested architec

APA, Harvard, Vancouver, ISO, and other styles

32

Et. al., Barma Venkata RamaLakshmi. "Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 5673–83. http://dx.doi.org/10.17762/turcomat.v12i3.2242.

Full text

Abstract:

This paper presents the implementation and design of Radix-8 booth Multiplier using 32-bit parallel prefix adders. High performance processors have a high demand in the industrial market. For achieving high performance and to enhance the computational speed multiplier plays a key role in performance of digital system. But the major drawback is it consumes more power , area and delay. To enhance the performance and decrease the area consumption and delay there are many algorithms and techniques. In this paper we designed a radix-8 Booth Multiplier using two parallel prefix adders and compared t

APA, Harvard, Vancouver, ISO, and other styles

33

Kaza, Srilakshmi, Syamala Yarlagadda, S. D. Raghavendra Chintapalli, and E. Vijaya Babu. "PERFORMANCE COMPARISON OF FINFET-BASED ENERGY RECOVERY ADDER CIRCUITS." Telecommunications and Radio Engineering 83, no. 5 (2024): 83–94. http://dx.doi.org/10.1615/telecomradeng.v83.i5.80.

Full text

Abstract:

The growing demand for secure devices (such as radio frequency identification tags, wireless sensor networks, and smart cards) and the widespread use of the Internet of Things (IoT) have necessitated the secure and energy-efficient design of IoT devices. To date, most of the previous investigations carried out regarding secure devices have focused on the implementation of adiabatic logic circuits for ultra-low power applications. However, to investigate various applications of adiabatic logic circuits, it is essential to analyze their performance characteristics. In this work, the performance

APA, Harvard, Vancouver, ISO, and other styles

34

Kogut, Ihor, Volodymyr Hryha, Bohdan Dzundza, Liudmyla Hryha, and Iryna Hatala. "Research and Design of Multibit Binary Adders on Fpga." Advances in Cyber-Physical Systems 9, no. 2 (2024): 108–14. https://doi.org/10.23939/acps2024.02.108.

Full text

Abstract:

This paper provides an analysis of the system characteristics and functional capabilities of various types of adders for the high-speed component construction of arithmetic and logical devices in modern superscalar processors. The main features of parallel prefix adders (Sklansky, Brent Kung, Kogge Stone, Ladner Fisher, Han Carlson) and tree-like structures based on incomplete binary adders have been determined in this study. The structures of typical and improved incomplete binary adders have been shown and their complexity characteristics have been calculated as well. Various architectures (

APA, Harvard, Vancouver, ISO, and other styles

35

Reddy Hemantha, G., S. Varadarajan, and M. N. Giriprasad. "DA Based Systematic Approach Using Speculative Addition for High Speed DSP Applications." International Journal of Engineering & Technology 7, no. 2.24 (2018): 197. http://dx.doi.org/10.14419/ijet.v7i2.24.12030.

Full text

Abstract:

In recent years Parallel-prefix topologies has been emerged to offer a high-speed solution for many DSP applications. Here in this paper carrier approximation is introduced to incorporate speculation in Han Carlson prefix method. And overall latency is considerably reduced using single Brent-Kung addition as a pre and post processing unit. In order to improve the reliability error detection network is combined with the approximated adder and it is assert the error correction unit whenever speculation fails during carries propagation from LSB segment to MSB unit. The proposed speculative adder

APA, Harvard, Vancouver, ISO, and other styles

36

Choudhary, Anjulata, Nishi Pandey, and Meha Shrivastava. "Area and Delay Efficient 2-D DWT using Canonic Signed Digit and Brent Kung Adder Technique." International Journal of Computer Sciences and Engineering 7, no. 10 (2019): 235–39. http://dx.doi.org/10.26438/ijcse/v7i10.235239.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Sharma, Ayushi, and Ajit Singh. "Design and Implementation of a delay and area efficient 32x32bit Vedic Multiplier using Brent Kung Adder." International Journal of Engineering Trends and Technology 41, no. 8 (2016): 393–98. http://dx.doi.org/10.14445/22315381/ijett-v41p271.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Nehru, K., T. Nagarjuna, and U. Somanaidu. "Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders." International Journal of Reconfigurable and Embedded Systems 7, no. 2 (2018): 115–23. https://doi.org/10.11591/ijres.v7.i2.pp115-123.

Full text

Abstract:

Parallel prefix adder network is a type of carry look ahead adder structure.  It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article,  an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes with the lowest transistor count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel

APA, Harvard, Vancouver, ISO, and other styles

39

Ibrahim, Salah Hasan, Sawal Hamid Md Ali, and Md Shabiul Islam. "Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer." Scientific World Journal 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/131568.

Full text

Abstract:

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes

APA, Harvard, Vancouver, ISO, and other styles

40

Dr., Vasudeva G. "Floating Point Unit with High Precision Efficiency." International Journal of Soft Computing and Engineering (IJSCE) 15, no. 2 (2025): 24–30. https://doi.org/10.35940/ijsce.B3669.15020525/.

Full text

Abstract:

<strong>Abstract:</strong> In this paper, we dive into designing a Single Precision Floating Point Unit (FPU), a key player in modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in scientific research, graphics rendering, and machine learning—our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The BrentKung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel-prefix structure, it minimises delays even as the numbe

APA, Harvard, Vancouver, ISO, and other styles

41

Gudipati, Parashuramulu. "An ASIC level Implementation of Modified CSA to Optimize Low Power and High Speed Using Brent Kung Adder." International Journal for Research in Applied Science and Engineering Technology 6, no. 3 (2018): 1400–1404. http://dx.doi.org/10.22214/ijraset.2018.3215.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Dr. Vasudeva G and Dr Bharathi Gururaj. "Floating Point Unit with High Precision Efficiency." International Journal of Soft Computing and Engineering 15, no. 2 (2025): 24–30. https://doi.org/10.35940/ijsce.b3669.15020525.

Full text

Abstract:

In this paper, we dive into designing a Single Precision Floating Point Unit (FPU), a key player in modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in scientific research, graphics rendering, and machine learning—our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The BrentKung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel-prefix structure, it minimises delays even as the numbers get bigger. For multiplication

APA, Harvard, Vancouver, ISO, and other styles

43

Erna, G., G. Srihari, M. Purna Kishore, Ashok Nayak B., and M. Bharathi. "FPGA Implementation of High-Performance Truncated Rounding based Approximate Multiplier with High-Level Synchronous XOR-MUX Full Adder." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 22 (December 4, 2023): 111–25. http://dx.doi.org/10.37394/23201.2023.22.13.

Full text

Abstract:

In research and development, the most emerging field in digital signal processing and image processing is rounded-based approximated signed and unsigned multipliers. In the present research, we propose some cutting-edge, Preformation, and logic simplification technology connected to processing the Discrete cosine transform (DCT) and Discrete wavelet transform (DWT) images for sharpening. This technology will yield a truncated shifter incorporated with logical XOR-MUX Full adder techniques. A reliable and cost-effective approximate signed and unsigned multiplier was created for the rounding met

APA, Harvard, Vancouver, ISO, and other styles

44

Tariq Hussein, Fatima, and Fatemah K. AL-Assfor. "Efficient Implementation of Fixed-Point MAC and Multimode MAC Blocks Based on Vedic Mathematic." Iraqi Journal for Electrical and Electronic Engineering 21, no. 2 (2025): 88–98. https://doi.org/10.37917/ijeee.21.2.9.

Full text

Abstract:

Recently, the need for high speed multiply-accumulate (MAC) operations is crucial in numerous systems like 5G, deep learning, in addition to many digital signal processing (DSP) applications. This work offers an improved MAC (I-MAC) block of different bit-size based on Vedic Mathematic and employing a hybrid adder consists of an enhanced Brent-Kung with a carry-select adder (HBK-CSLA) to achieve the sum of products for the MAC. The work is then, developed to design a new multimode fixed-point (FX-Pt) MAC block by exploiting the proposed design of the I-MAC architecture. The proposed multimode

APA, Harvard, Vancouver, ISO, and other styles

45

Tariq Hussein, Fatima, and Fatemah K. AL-Assfor. "Design Efficient Vedic-Multiplier for Floating-Point MAC Module." Iraqi Journal for Electrical and Electronic Engineering 20, no. 2 (2024): 182–89. http://dx.doi.org/10.37917/ijeee.20.2.15.

Full text

Abstract:

Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing (DSP) applications, such as image convolution and filters, especially when performed on floating-point numbers to achieve high-level of accuracy. The performance of MAC module highly relies upon the performance of the multiplier utilized. This work offers a distinctive and efficient floating-point Vedic multiplier (VM) called adjusted-VM (AVM) to be utilized in MAC module to meet modern DSP demands. The proposed AVM is based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra) approach and utilizes an enhanced desi

APA, Harvard, Vancouver, ISO, and other styles

46

Pudi, Vikramkumar, and K. Sridharan. "Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA." IEEE Transactions on Nanotechnology 11, no. 1 (2012): 105–19. http://dx.doi.org/10.1109/tnano.2011.2158006.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

Vinutha, C. Ruth, M. Bharathi, and D. Divya. "A Survey on Brent-Kung, Han-Carlson and Kogge-Stone Parallel Prefix Adders for Their Area, Speed and Power Consumption." i-manager's Journal on Circuits and Systems 3, no. 4 (2015): 37–41. http://dx.doi.org/10.26634/jcir.3.4.5929.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

"Architecture of 2X2 FIR Filter using Vedic Multiplier and Brent-Kung Adder." International Journal of Innovative Technology and Exploring Engineering 9, no. 5 (2020): 1638–42. http://dx.doi.org/10.35940/ijitee.e3070.039520.

Full text

Abstract:

This paper proposed, a 2X2 FIR filter which is based on the Brent-Kung adder and Vedic multiplier. A 2X2 FIR filter has been designed using Brent-Kung-Adder (BKA) and filter coefficient. Verilog platform and Xilinx 14.5 software. The BrentKung adder is much faster than the look ahead carry adder (LACD), carry select adder and ripple carry adder (RCA) and it is a parallel prefix adder. Lowarea and the power consumption in Brent-kung adder is also less as compared to various adders. Multiplication of a number using the Vedic multiplier is arithmetic key operation to be performed with low power c

APA, Harvard, Vancouver, ISO, and other styles

49

Machavolu, Divya Sathvika Dr. P.Sreenivasulu Mr S.Surendra Babu. "Decoder Reduction Approximation Scheme For Booth Multipliers Using Brent-Kung Adder." May 3, 2025. https://doi.org/10.5281/zenodo.15332462.

Full text

Abstract:

<strong>Abstract: </strong>This work reveals a new approximation method that uses Booth multipliers to reduce the amount of error produced while reducing the number of decoders in the design to increase computational efficiency. To make it more efficient, the design forms part of the Brent-Kung Adder which captures the benefits of its parallel prefix structure in achieving low propagation delay and improvement in scalability. The 16-bit BD16.4 multiplier together with the Brent-Kung Adder thrives in performance and accuracy compared to conventional logarithmic and higher-radix multipliers. Fur

APA, Harvard, Vancouver, ISO, and other styles

50

V, Gayathri, Kathirvelu M, and Yogeswari P. "Efficient MAC Unit Design for DSP Processors Using Multiplication and Accumulation Operations." International Journal of Innovative Science and Research Technology (IJISRT), October 17, 2024, 3135–42. http://dx.doi.org/10.38124/ijisrt/ijisrt24sep1652.

Full text

Abstract:

Digital signal processors are essential for intricate processes like filtering and convolution. CPU core integration into a single Integrated Circuit (IC) is widespread to satisfy growing processing needs. Multiply and Accumulate (MAC) units are essential for repeated addition and multiplication in DSP. Performance of the MAC unit has a big impact on the total speed of the DSP algorithm. It is suggested to create a high-speed MAC unit with a pipelined Brent Kung (BK) Adder design and the Vedic multiplier technique. A comparative study with a standard Brent Kung adder and a 32-bit MAC unit reve

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!