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Tochel, Claire. "Evaluation of contrast threshold measurements and simultaneous brightness ratios in the diagnosis of glaucoma." Thesis, University of Glasgow, 2001. http://theses.gla.ac.uk/4879/.
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There is considerable dissatisfaction with the reliability and sensitivity of the methods used to assess the glaucomatous visual field. Two types of visual field test, which have been proposed as having potential in diagnosing glaucomatous visual field defects, have been modified and tested on a group of patients from a glaucoma clinic, a group of age-matched control subjects and a younger control group. 1. A grating pattern was generated using a laser interferometer which projected a large diameter image onto the retina independent of the subject's refractive error. The experimental set up which produced the most reliable and consistently low contrast threshold values in normal subjects was sought. The display characteristics which were examined included different orientations for the field quadrants as projected to the subject; stationary and flickering patterns using a variety of flicker generation methods; red and green light sources; and concentric or vertical sinusoidal grating patterns. Ultimately the optimal display was found to be a stationary image consisting of a green, vertical sinusoidal grating pattern. Arcuate regions of the visual field (at 10 to 20° from fixation) were stimulated in 4 distinct, obliquely oriented quadrants and a low spatial frequency (one cycle per degree) was chosen. 2. Normal limits were obtained from age-matched control subjects for comparison with the results for the patients from the glaucoma clinic. In the patient group, of the 13 who completed the test, 9 individuals were identified as abnormal with one or more of their contrast threshold scores exceeding that limit. The patients' Friedmann visual field plots were analysed and the amount of loss in each quadrant was quantified. There was a positive correlation between the quantified visual field loss and contrast threshold scores in 6 patients, a statistically borderline correlation in 2 patients and the absence of a correlation was found in 5 patient's results. The results for a subgroup of 6 visually abnormal eyes (not affected by glaucoma) excluded from the age-matched control group are also described. Their visual defects included mild cataract, amblyopia and retinal detachment. There were no clear abnormal results in 5 of the eyes in this group; however, in one subject with retinal scarring due to an infection, there was a distinct elevation of contrast threshold in the affected eye. Humphrey visual field plots were obtained for all but one of the age-matched control subjects. 3. Simultaneous brightness ratios (SBR) have previously been shown to provide an indication of'glaucomatous damage. The same subject groups as described above were tested. SBRs were obtained for central vision in both eyes of subjects (inter-ocular ratio). This technique was now extended for the first time to paired regions within each eye (intra-ocular ratios) producing 'nasal I temporal' and 'upper I lower' ratios. In each test the subject controlled the brightness ratio which was changed in a smoothly graduated and continuou8 way. The most effective procedure for recording repeatable SBRs was first explored, and it was determined that these could be best obtained by alternating the start point of the graduated filter position. For each subject, 5 ratios were obtained: inter-ocular SBR; upper I lower intra-ocular SBR for right eye and left eye; and nasal I temporal intra-ocular SBR for right eye and left eye. 4. Normal limits were obtained from age-matched control subjects for comparison with the results for the patients from the glaucoma clinic. In each of the 5 SBR tests carried out, these limits were wide, reflecting considerable variation in the normal results. Of the 14 patients who completed the tests, 5 were identified as abnormal by one or more of their SBRs being outside normal limits. Three of these were identified as abnormal by their inter-ocular SBRs alone, one was abnormal according to his upper I lower intra-ocular SBR alone and one patient had an abnormal inter-ocular SBR and an abnormal intra-ocular SBR. The corresponding regions of the patients' Friedmann visual fields were quantified, and these values were used to calculate visual field loss ratios. There was a positive correlation between the visual field loss ratios and SBRs in 3 patients, but no correlation in 11 patients. In the sub-group of 6 visually abnormal eyes without glaucoma, mild cataract appeared not to adversely affect SBR. Mean SBRs were normal in the subject with retinal detachment but there was evidence of an enhanced amount of variation in the readings. Two subjects with a damaged retina and one with an amblyopic eye did produce abnormal inter-ocular SBRs, with the normal eye being significantly more sensitive in both cases.
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Caicedo, Jhon Alexander Gomez. "CMOS low-power threshold voltage monitors circuits and applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.
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Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap.A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.
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Wang, Yanbin. "Threshold voltage control by backgating in fully depleted SOI CMOS." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0007/MQ43350.pdf.
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Wang, Yanbin Carleton University Dissertation Engineering Electronics. "Threshold voltage control by backgating in fully depleted SOI CMOS." Ottawa, 1999.
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Narendra, Siva G. (Siva Gurusami) 1971. "Effect of MOSFET threshold voltage variation on high-performance circuits." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8341.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 95-101).
The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in threshold voltage variation due to worsening short channel effect. This thesis will address three specific circuit design challenges arising from increased threshold voltage variation and present prospective solutions. First, with supply voltage scaling, control of die-to-die threshold voltage variation becomes critical for maintaining high yield. An analytical model will be developed for existing circuit technique that adaptively biases the body terminal of MOSFET devices to control this threshold voltage variation. Based on this model, recommendations on how to effectively use the technique in future technologies will be presented. Second, with threshold voltage scaling, sub-threshold leakage power is expected to be a significant portion of total power in future CMOS systems. Therefore, it becomes imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and a circuit technique to reduce system leakage without reducing system performance will be discussed.
(cont.) Finally, due to different processing steps and short channel effects, threshold voltage of devices of same or different polarities in the same neighborhood may not be matched. This will introduce mismatch in the device drive currents that will not be acceptable in some high performance circuits. In the last part of the thesis, voltage and current biasing schemes that minimize the impact of neighborhood threshold voltage mismatch will be introduced.
by Siva G. Narendra.
Ph.D.
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Wang, Annie I. (Annie I.-Jen) 1981. "Threshold voltage in pentacene field effect transistors with parylene dielectric." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/17998.
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Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 59-63).
Organic field effect transistors (OFETs) offer a suitable building block for many flexible, large-area applications such as display backplanes, electronic textiles, and robotic skin. Besides the organic semiconductor itself, an important area in the development of OFETs is the gate dielectric material. In this thesis the organic polymer parylene is studied as a gate dielectric for pentacene OFETs. The three main areas of study were: (1) parylene's performance as a dielectric, (2) possible improvement of OFETs by surface treatments, and (3) the effects of interface traps on threshold voltage and parasitic bulk conductivity. Parylene was found to provide a favorable, hydrophobic interface for pentacene growth, yielding transistors with mobilities > 0.5cm²/Vs at -100V. While the two surface treatments explored did increase contact angle by 10-20⁰, neither the ammonium sulfide nor the polystyrene treatment significantly improved pentacene packing or mobility. Modification of the parylene surface using an oxygen plasma introduced traps at the semiconductor-dielectric interface, observable through a variety of characterization techniques. A model is developed to explain how the fixed and mobile charges these traps introduce influence the threshold voltage and parasitic conductivity in the device.
by Annie I. Wang.
M.Eng.and S.B.
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Nirmala, Ithihasa Reddy. "Threshold Voltage Defined Switches and Gates to Prevent Reverse Engineering." Scholar Commons, 2016. http://scholarcommons.usf.edu/etd/6555.
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1Semiconductor supply chain is increasingly getting exposed to variety of security attacks such as Trojan insertion, cloning, counterfeiting, reverse engineering (RE), piracy of Intellectual Property (IP) or Integrated Circuit (IC) and side-channel analysis due to involvement of untrusted parties. In this thesis, we use threshold voltage-defined switches to design a logic gate that will camouflage the conventional logic gates both logically and physically to resist RE and IP piracy. The proposed gate can function as NAND, AND, NOR, OR, XOR, and XNOR robustly using threshold defined switches. We also propose a flavor of camouflaged gate that represents reduced functionality (NAND, NOR and NOT) at much lower overhead. The camouflaged design operates at nominal voltage and obeys conventional reliability limits. A small fraction of gates can be camouflaged to increase the RE effort extremely high. Simulation results indicate 46-53% area, 59-68% delay and 52-76% power overhead when 5-15% gates are identified and camouflaged using the proposed gate. A significant higher RE effort is achieved when the proposed gate is employed in the netlist using controllability, observability and hamming distance sensitivity based gate selection metrics.
1 Information included in this chapter is reprinted from [19] with permission. Copyright permission included in Appendix B.
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Akhavan, Fomani Arash. "Threshold Voltage Instability and Relaxation in Hydrogenated Amorphous Silicon Thin Film Transistors." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/769.
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This thesis presents a study of the bias-induced threshold voltage metastability phenomenon of the hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs). An application of gate bias stress shifts the threshold voltage of a TFT. After the bias stress is removed, the threshold voltage eventually returns to its original value. The underlying physical mechanisms for the shift in threshold voltage during the application of the bias and after the removal of the bias stress are investigated. The creation of extra defect states in the band gap of a-Si:H close to the gate dielectric interface, and the charge trapping in the silicon nitride (SiN) gate dielectric are the most commonly considered instability mechanisms of threshold voltage. In the first part of this work, the defect state creation mechanism is reviewed and the kinetics of the charge trapping in the SiN is modelled assuming a simplified mono-energetic and a more realistic Gaussian distribution of the SiN traps. The charge trapping in the mono-energetic SiN traps was approximated by a logarithmic function of time. However, the charge trapping with a Gaussian distribution of SiN traps results in a more complex behavior.
The change in the threshold voltage of a TFT after the gate bias has been removed is referred to threshold voltage relaxation, and it is investigated in the second part of this work. A study of the threshold voltage relaxation sheds more light on the metastability mechanisms of a-Si:H TFTs. Possible mechanisms considered for the relaxation of threshold voltage are the annealing of the extra defect states and the charge de-trapping from the SiN gate dielectric. The kinetics of the charge de-trapping from a mono-energetic and a Gaussian distribution of the SiN traps are analytically modelled. It is shown that the defect state annealing mechanisms cannot explain the observed threshold voltage relaxation, but a study of the kinetics of charge de-trapping helps to bring about a very good agreement with the experimentally obtained results. Using the experimentally measured threshold voltage relaxation results, a Gaussian distribution of gap states is extracted for the SiN. This explains the threshold voltage relaxation of TFT after the bias stress with voltages as high as 50V is removed.
Finally, the results obtained from the threshold voltage relaxation make it possible to calculate the total charge trapped in the SiN and to quantitatively distinguish between the charge trapping mechanism and the defect state creation mechanisms. In conclusion, for the TFTs used in this thesis, the charge trapping in the SiN gate dielectric is shown to be the dominant threshold voltage metastability mechanism caused in short bias stress times.
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Seshadri, Sriram Mannargudi. "INVESTIGATION OF HIGH-k GATE DIELECTRICS AND METALS FOR MOSFET DEVICES." Master's thesis, University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3331.
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Progress in advanced microlithography and deposition techniques have made feasible high- k dielectric materials for MOS transistors. The continued scaling of CMOS devices is pushing the Si-SiO2 to its limit to consider high-k gate dielectrics. The demand for faster, low power, smaller, less expensive devices with good functionality and higher performance increases the demand for high-k dielectric based MOS devices. This thesis gives an in-depth study of threshold voltages of PMOS and NMOS transistors using various high-k dielectric materials like Tantalum pent oxide (Ta2O5), Hafnium oxide (HfO2), Zirconium oxide (ZrO2) and Aluminum oxide (Al2O3) gate oxides. Higher dielectric constant may lead to high oxide capacitance (Cox), which affects the threshold voltage (VT) of the device. The working potential of MOS devices can be increased by high dielectric gate oxide and work function of gate metal which may also influence the threshold voltage (VT). High dielectric materials have low gate leakage current, high breakdown voltage and are thermally stable on Silicon Substrate (Si). Different kinds of deposition techniques for different gate oxides, gate metals and stability over silicon substrates are analyzed theoretically. The impact of the properties of gate oxides such as oxide thickness, interface trap charges, doping concentration on threshold voltage were simulated, plotted and studied. This study involved comparisons of oxides-oxides, metals-metals, and metals-oxides. Gate metals and alloys with work function of less than 5eV would be suitable candidates for aluminum oxide, hafnium oxide etc. based MOSFETs.M.S.E.E.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
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Ravi, Ajaay. "Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE)." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1302550444.
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Chin, Shang-Chei, and 金尚志. "Study of Dynamic Threshold Voltage MOSFET." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/35114525041736943045.
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Lin, Hui-Chi, and 林慧琪. "Predicting LED Brightness and Voltage using LED Process Data." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/783c34.
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碩士國立中正大學
資訊管理學系暨研究所
101
In order to maintain the advantages of domestic LED industry, it is necessary to upgrade the manufacturing process not only to develop new product but also reduce production costs and improve yield. There are dozen variables which influence process parameters. If they are not been effectively test in engineering run first, often the whole process will have to start from scratch again. It's time-consuming and costly. The source of LED chip processing data are complex and hard to collect. Causing the low order fill rate because the product stuck on production line waiting for data processing. Thereby one of the key to improve competitiveness in the market is to manage process data at all time. This study using MES system to collect processing information. Staring from integrate information from different sources, and then use the data pre-processing method to do data initial processing and filtering. After, using techniques such as Neural Networks、Support Vector Machine、Regression Analysis and Model Tree of data mining to find the best predictive model. The Model Tree proved to be the best predictive model. Analysis and determine the process factor that affect brightness and voltage of LED chips. Provide engineering staff the data in time for process improvement.
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Lee, Po-Ming, and 李博明. "Dual Threshold Voltage SRAM & BIST Comparators." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/54537803463637070668.
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博士國立中山大學
電機工程學系研究所
92
Since the invention of SRAM (Static Random Access Memory), many improvements have been proposed. The major targets are speed, area, and power consumption. The evolution of the CMOS process technology makes it possible to implement SRAM by using dual threshold voltage transistors. Hence, we will use TSMC (Taiwan Semiconductor Manufacturing Company) 0.25 $mu$m 1P5M CMOS process to realize the dual threshold voltage SRAM in this thesis. In order to reduce SRAM internal power consumption, we also propose quenchers to suppress unwanted oscillation between bit lines. In addition, several types of BIST (Build In Self Test) comparators are also proposed to test the mentioned SRAM. After detailed simulations, the proposed comparators possess impressive results in high fan-in, low transistor count, and high speed. The proposed SRAM and BIST comparators are fabricated by the CMOS process provided by National Science Council Chip Implementation Center (CIC). The measurements of the chips are fully corrected to meet the design goals.
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Wang, Jhong-Sheng, and 王仲盛. "Drift-Current Threshold Voltage Models of MOSFETs." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/74494561749171279789.
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Ho, Yen-Te, and 何彥德. "Low Power Design Using Dual Threshold Voltage." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/44905926043321454956.
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碩士國立清華大學
資訊工程學系
91
With the growing of design complexity and the wide use of portable and wireless electronic systems, reduction in power consumption has become more and more important in today's VLSI circuits. In CMOS digital circuits, power dissipation consists of dynamic and static power consumption. When the manufacturing technology scales to 0.05 micron in the future, the dynamic power will contribute to nearly 50% of the total power consumption. Therefore, in this thesis, we put our emphasises on the reduction of static power consumption by reducing the subthreshold current in order to solve this future problem. We will address the gate-level power optimization by selection of threshold voltage for a given timing constraint. We also develop a design flow to incorporate our algorithm into current commercial tools.
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Wen, Cheng-neng, and 溫政能. "An OLED Pixel Driver Using Voltage Feedback for Threshold Voltage Shift Compensation." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/bkc72z.
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碩士國立中山大學
電機工程學系研究所
96
In this thesis we proposed two new pixel circuits for organic light emission display. The first one is 5T1C circuit with two control signals. It can compensate threshold voltage variation and the drop of the power supply voltage that result in OLED current non-uniformity. We have demonstrates that the pixel circuit has high immunity to the threshold voltage variation. In addition, the circuit uses low supply voltage compared with the conventional 5T1C pixel circuit, so it is a low power driver circuit. The second one employs the voltage feedback method and uses the gain value of design circuit for compensating the threshold voltage shift of the driving TFT.To the aim is to reach that to the flow through current of the driving TFT have no relationship with the threshold voltage of TFT. Thus, the OLED can emission light with retaining uniformity light in each time. Because the proposed circuit configuration has low supply voltage and low select pulse voltage, the spike wave phenomenon can be improved and eliminated while the circuit switchs on and off. Due to the circuit supply voltage is decreased, it power consumption reduce significantly and the capacitor charging time is less than 70 μs. Thus, in this thesis, the two proposed pixel circuits are both of low voltage and low power. The two pixel circuits designed have been fabricated by TSMC 0.35μm 2P4M CMOS technology with 3.3v power supply. The 5TIC chip area is 1031.8 × 1083.7μm2 and the measured result shows that when the select pulse is 0~10V, the input voltage is 10V, the select pulse2 is 0~8V and the Vdata voltage range is 0~5V, the OLED current is correspond to 0~20.6μA and the maximum power consumption is 17μw. The chip area of the voltage feedback circuit is 1083.38 × 1149.8μm2 and the measured result shows that when the select pulse is 0~10V, the input voltage is 10V and the feedback resistor is 50Ω, the power consumption is 72μw and the charging time is 51.7μs.
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Lindsey, Imiola. "Device modeling of transconductance threshold voltage reference devices." Thesis, 2006. http://hdl.handle.net/10125/20941.
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Lee, Wei-ning, and 李威寧. "A Study of Threshold Voltage Controlfor Liquid Crystal." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/96853347587651411830.
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碩士逢甲大學
工業工程與系統管理學研究所
94
In recent years, LCDs have been becoming to one of the most popular industries following the semi-conductors. However, the rapid expansion of market conducts to more intense competition. To overcome the impact of bitter rivalry from large-sized panel manufacturer, it is essential for medium and small-sized panel maker to revise the product designing. LCD composes mainly of substrate, polarizer, color filter, liquid crystal and driver. Considering the improper matching up of the liquid crystal and the driver can increase production cost significantly, this research aims to prevent inappropriate design by controlling the threshold voltage of liquid crystal with a statistics and analysis software. Consequently to achieve more efficient competition.
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Liu, Shou-En, and 劉守恩. "Threshold Voltage Model of Asymmetry Double Gate MOSFET." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/23002033707927316207.
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WANG, YEN-TING, and 王彥婷. "A HIGH PERFORMANCE THRESHOLD VOLTAGE BASED TEMPERATURE SENSOR." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/03935992866969689706.
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碩士大同大學
電機工程學系(所)
98
A smart temperature sensing system with digital output consists of a temperature sensor and a voltage reference in the front end and an analog-to-digital converter (ADC) in the back end. In this thesis, a threshold-voltage based temperature sensor has been presented, and a low temperature coefficient voltage reference is achieved by using a pn-junction proportional to absolute temperature (PTAT) current generator to compensate the threshold-voltage based temperature sensor. In addition, a 7-bit flash ADC has been designed to convert the output of the temperature sensor to a digital code. The simulation results obtained from HSPICE using a standard TSMC 0.18um CMOS models and 1.8V power supply are presented in this thesis. This sensor is almost insensitive to the supply and is very linear dependent to temperature. The simulation result shows that the voltage output of the sensor has the temperature error of ±0.07°C from -20°C～100°C, and temperature coefficient of it is -1.239 mV/°C. The low temperature coefficient voltage reference has the result of 1.51V, and the temperature coefficient is 1.058ppm/°C. The 7-bit flash bit has the INL of 0.32LSB, and DNL of 0.38LSB, which can meet the requirement of the temperature sensing system with 1°C resolution.
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Chang, Szu-Wei. "A Low Power Scheduling Method with Dual Supply Voltage and Dual Threshold Voltage." 2004. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2906200415455400.
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Liu, Sheng-Che, and 劉聖哲. "Low-Voltage Circuit Design Using PD SOI Dynamic-Threshold Voltage MOS (DTMOS) Techniques." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/54800027175988214419.
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碩士國立臺灣大學
電機工程學研究所
88
This thesis reports two low-voltage low-power circuits which are designed by using PD SOI DTMOS techniques. In chapter 2, this thesis introduced a novel 0.7V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold techniques. With an innovative approach by connecting the body terminal for an NMOS device in the latch and the write access pass transistor to write word line, this 6T memory cell can be used to provides SBLSRWA capability for 0.7V two-port SOI CMOS cache memory. In chapter 3, this thesis introduced a novel low-voltage content addressable memory (CAM) cell structure using partially-depleted SOI CMOS dynamic-threshold techniques. With a unique structure by dynamically controlling the bodies of transistors that compose XOR portion of CAM cell via two auxiliary transistors, this CAM cell can be used to provide faster compare capability for low voltage range SOI CMOS CAM applications.
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Liu, Yi-Ting, and 劉怡婷. "Voltage Scalable Switched Capacitor DC-DC Converter for Near-Threshold Voltage Integrated Circuit." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/cn5c3d.
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碩士國立交通大學
電機工程學系
102
This thesis proposes a DC-DC converter operation at 0.5 V. The circuit consists of four parts: a comparator, a digital control circuit, a switched capacitor and a digital circuit under test (DUT). The digital control circuit take the comparator output to control the switched capacitor operation to achieve the target voltage according to the reference voltage. It’s 2-phase interleaved converter can be configured into three topologies, which supports the output voltages of 0.25-0.45 V from the 0.5 V input supply, it has an efficiency between 59-79% for the load current of 100 µA. This converter is designed with all digital control without any static power consumption. At the load of 0.45 V and 100 µA, the switched capacitor consumes 57 µW. Among them, 45 µW is for the DUT with an efficiency of 79 %. The comparator and the digital control consume only 2 µW under lowest load power. It can be applied to implantable biomedical chip with low power consumption circuits. This chip is fabricated in TSMC GUTM 90 nm CMOS process, with high efficiency. The chip area is 1mm × 1mm.
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Chang, Dern-kan, and 張登堪. "Design of Low-Voltage CMOS Voltage Reference Circuits Based on Sub-threshold Characteristics." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/99526991345794192669.
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碩士國立中興大學
電機工程學系所
95
The conventional band-gap reference voltage circuits usually require high supply voltage. To comply with the trend of low voltage operations, many people have tried to use the sub-threshold characteristics to generate the reference voltage. However, they may suffer from larger corner variations or larger chip area due to the resistors in the circuits. This thesis introduces two voltage reference circuits to alleviate these problems. The first voltage reference circuit is presented for generating a constant reference voltage of 278mV using sub-threshold characteristics of 0.18um CMOS technology at supply voltages from 0.8V to 2.6V with a total current of 3.6 uA. The threshold voltage variation due to process corner variation is minimized by a threshold voltage tracking technique between the normal and high threshold NMOS transistors. In the mean time, channel-length modulation effect is also compensated. The proposed circuit on the chip area of 0.04mm 2 achieves the total reference voltage variation of 2.5mV for various process corners and temperature variation from -20 degree C to 120 degree C. The second voltage reference without the resistor providing a constant voltage reference of 101mV was realized in 0.18um CMOS technology at supply voltage from 0.9V to 2.6V with a total current of 7.4uA. There are two NMOS transistors used as resistors. The resistance ratio can be compensated to cancel temperature variation effects to achieve a nearly constant voltage reference. For temperatures from -10 degree C to 110 degree C, it has a variation about 2mV with different process corners, in chip area of 0.0122mm 2.
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Chang, Szu-Wei, and 張四維. "A Low Power Scheduling Method with Dual Supply Voltage and Dual Threshold Voltage." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/71448988551644085022.
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碩士國立臺灣大學
資訊工程學研究所
92
Dynamic power consumption goes down quadratically with the supply voltage scaling down. It is naturally for the researchers to scale down the supply voltage to reduce power consumption. It is also possible to reduce the power consumption in a design without degrading the performance by reducing the supply voltage of those cells o® the critical path. This method is so-called dual/multiple supply voltage methodology. However, it is also possible to provide dual/multiple threshold voltage to reduce the power consumption. As in [1] [2] [3] [4] [5] [6] [8] [7], many researches focus on assigning dual supply/threshold voltage to gate-level design. In this paper, we proposed a partitioning methodology with multiple supply voltage and multiple threshold voltage in behavioral synthesis stage. By considering multiple voltages and multiple thresholds in higher level of the design flow, we can explore larger design space of power, area, and performance. Hence we can optimize the power consumption without losing circuit e±ciency and area. And because the scheduling problem has been proven to be a NP problem, so we can not find optimal solution in polynomial time. To solve this, we adopt a GA (Genetic Algorithm) based SA (Simulated Annealing) approach to find an approximation result.
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Huang, You-Cheng, and 黃宥脀. "An Ultra-Linear Voltage-To-Current Converter with Mobility Degradation and Threshold-Voltage Compensations." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/25982678247034032470.
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碩士雲林科技大學
電子與資訊工程研究所
96
This work presents a design of ultra-linear voltage-to-current converter with mobility degradation and threshold-voltage compensations. For mobility degradation in deep submicron processes, the proposed compensation method can effectively decrease the high order nonlinear items within relationship between voltage and current. In addition, through modifying the configuration of current source, the proposed design is insensitive to variation of threshold voltage and also leads to higher power rejection ratio. According to experiment results, we enable a wide operational range and almost constant transconductance that reach to 0.9V and 0.946~1.025 normalized value in 3.3V COMS process respectively. Moreover, the experiment result also shows the proposed design can decrease the variation error less than 3% caused by variation of threshold-voltage which under 3%. The theoretical development and design flow of proposed method are derived completely and this work is implemented by TSMC 0.35um 2P4M 3.3V CMOS process.
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Power, Kevin Edward. "An investigation of voltage threshold hyperpolarization : mechanism to function." 2009. http://hdl.handle.net/1993/21562.
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Lin, Chia-Hung, and 林佳宏. "Dynamic Voltage Scaling for the Digital Sub-Threshold Operation." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/23895485172533415413.
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碩士國立交通大學
電機學院電機與控制學程
99
In this thesis we propose a dynamic voltage scaling system, we have by dynamically adjust the digital circuit operating voltage to overcome frequency impact when the digital circuit is operating in the sub-threshold region with process violation and temperature change. And maintain the operating frequency will not have a dramatic change due to operate in the sub-threshold region. This system use the concept of frequency loop lock, using the frequency detector to compare the critical path of the digital circuits and the reference frequency. Then appropriate adjustments to the operating voltage of the digital circuit to change the critical path delay, so that digital circuits can work at the reference frequency in minimum operating voltage and not restricted by the process and temperature variations. In dynamic voltage scaling system we use a switch capacitor voltage converter to adjust the operating voltage, the use of switched capacitor voltage converter as a benefit is not required to use the inductor. The capacitance can produced directly in the IC, SoC integration is easier to achieve the purpose. The proposed circuit architecture in TSMC 0.18μm 1P6M CMOS process simulated, the simulation results show that the operation of the digital circuit voltage ripple can less than 1mV, frequency error is less than 3%.
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Duh, Wern-Yih, and 杜文毅. "Bridging Fault Analysis and Logic Gate Threshold Voltage Determination." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/24839279878536979046.
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碩士國立成功大學
電機工程學系
86
BIFEST(A Built-in Intermediate Fault Effect Sensing and Test GenerationSystem for CMOS Bridging Faults)是一個處理橋式錯誤之自 動測試向量產生（Auto Test Pattern Generation or ATPG）系統，其主 要功能在於利用邏輯測試方法及內建式中間電壓值測試法（Built-in IntermediateVoltage Testing or BIVT）去偵測橋式錯誤；BIFEST之邏 輯測試法是一傳統之ATPG系統，即使用相似於PODEM與PPSFP之方式完成的 ，而BIVT方法是針對剩餘未被邏輯測試法偵測到之橋式錯誤，其會產生中 間電壓者，使用一內建式中間電壓感測器（Built-in Intermediate Voltage Sensors or BIVS）去偵測。此篇論文在已有的BIFEST系統下， 分析各種剩餘無法使用BIFEST之邏輯測試法偵測之橋式錯誤，探討造成其 未能被測到的原因，以及討論具有哪些特性之橋式錯誤無法使用BIFEST之 BIVT方法偵測到；最後我們發現大部分是因電路之特性，而致使許多錯誤 無法使用BIFEST之邏輯測試法偵測到，唯有橋式錯誤型式是發生在一邏輯 閘之兩輸入情況，因系統採用悲觀的邏輯閘臨界電壓模型，而造成錯誤效 應易成為中間電壓值（介於邏輯1與邏輯0之間），及此種橋式錯誤之錯誤 涵蓋率過低；在分析完BIVT程序後，我們發現無法使用BIVT方法偵測到之 橋式錯誤，其無法產生中間值電壓。另外在BIFEST系統中，其邏輯閘臨界 電壓判定模型並不完善，故我們發展了一套改良版之邏輯閘臨界電壓判定 模型，其有較高的正確性且可涵蓋更多情況，最後我們將BIFEST之邏輯閘 臨界電壓判定模型代換成新的模型，如預期的，其結果較正確且邏輯測試 程序之錯誤涵蓋率會提升。 BIFEST (A Built-in Intermediate Fault Effect sensing and Test Generation System for CMOS Bridging Faults) is an ATPG (Automatic Test Pattern Generation) system for bridging faults. The BIFEST system combines logic testing method and Built-in Intermediate Voltage Testing (BIVT) method to detect bridging faults. The logic testing method of BIFEST is a conventional ATPG process that employs PODEM-like and PPSFP-based methods. The BIVT method is developed for remaining faults after logic testing. If the emaining bridging faults result in intermediate voltage then they are dealt with by special circuits called built-in intermediate voltage sensors (BIVSs).In this thesis, we analyze remaining bridging faults that cannot be detected by logic testing of BIFEST and discuss the reasons. We also discuss the properties of faults that cannot be detected by the BIVT method. After analyzing, we find that causation that makes bridging undetectable by logic testing of BIFEST is mostly due to circuit characteristics. For the case that when the bridging fault ype is between two inputs of a logic gate(In2BF), the fault effects become intermediate voltage easily and the fault coverage of In2BF is lower because BIFEST system uses a pessimistic model of gate threshold. After analyzed the BIVT method, we find that the bridging faults that are undetectable by BIVT cannot produce intermediate voltage at bridging sites.In BIFEST system, the logic gate threshold determination method is not good, so we improve the original model to get a new one. The new logic gate threshold determination model is more accurate and it covers more conditions. Then we replace the original gate threshold determination model with the new one. As expected, we obtain the higher accuracy and fault coverage after logic testing in BIFEST system.
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Wen, Cheng Chieh, and 鄭傑文. "An Analytical Threshold Voltage Model for Deep-Submicrometer MOSFET's." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/36573029223464534481.
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Tseng, Chi-Ping, and 曾祈賓. "Fabrication of SiGe/Si Hetrojunction Dynamic Threshold Voltage MOSFETs." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/72177903971648740407.
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碩士國立中央大學
電機工程研究所
92
Abstract In this thesis, we have demonstrated a high performance Si1-xGex（x = 0、0.3）DTMOS for low voltage、low power and high speed device applications. Measured the DC performance and compared the temperature effect between DTMOS and standard MOS at 77K、150K、300K、320K and 350K, respectively。 In our measurement, we had found that the SiGe DTMOS has higher drive current、greater transconductance、lower leakage current and ideal subthreshold slope than standard MOS. Beside, the threshold voltage and subthreshold slope of SiGe DTMOS have less sensitive for temperature than that of standard MOS. At high temperature, the degradation of SiGe DTMOS performance had lower than Si standard MOS. Therefore, SiGe DTMOS had better stability for temperature. According to the above advantage, SiGe DTMOS have the potential in low voltage、low power dissipation and high speed application.
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Lin, Po Jen, and 林柏仁. "High Energy Efficiency Near-Threshold Voltage Arithmetic Circuit Design." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/djfgc2.
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Huang, Chin Yi, and 黃金義. "Near-Threshold-Voltage Adder Design with Dual Body Bias." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/mmvq6y.
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Zhang, Shi-Han, and 張仕函. "Minimum Implant Area-Aware Placement and Threshold Voltage Refinement." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/m5kepm.
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碩士國立清華大學
資訊工程學系所
105
Threshold voltage assignment is a very effective technique to reduce leakage power consumption in modern integrated circuit (IC) design. As feature size continues to decrease, the layout constraints (called MinIA constraints) on the implant area, which determines the threshold voltage of a device, are becoming increasingly difficult to satisfy. It is necessary to take these constraints into consideration during the placement stage. [1] proposes to resolve the MinIA constraint violations of a given placement by performing simultaneous detailed placement and threshold voltage refinement. They first present an optimal and efficient mixed integer-linear programming (MILP)-based algorithm to handle intra-row MinIA constraints. We then extend the MILP-based algorithm to handle both inter-row and intrarow MinIA constraints. Our algorithm guarantees to fix all MinIA constraint violations. Experimental results demonstrate that our algorithm only perturb the original placement and threshold voltage assignment solutions minimally to eliminate all violations and are fast in practice.
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Chiou, Jian-Fa, and 邱建發. "A Study of Voltage Scaling into Sub-threshold Region." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/62048567004342709706.
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碩士國立清華大學
電機工程學系
98
In recent years, power has become one of the most important issues for chip designs. A lot of low-power design techniques have been developed. In digital circuits, adaptive voltage scaling is an effective approach to achieve low power design due to its lower supply voltage. This thesis focuses on the digital circuit operation while the power supply voltage is scaled down even to the sub-threshold region of the MOS transistor. The issues we encountered may happen not only in low power design but also become common issues while the supply voltage scaling down to close the threshold voltage in advanced technologies. With different (lower) supply voltage, the characteristic of circuit would be changed significantly. The design guidelines in nominal supply voltage cannot guarantee optimumality in low supply voltage. We are going to fix the performance degradation due to threshold voltage mismatch of PMOS and NMOS when voltage is scaled down. Develop a feasible solution to design a voltage insensitive digital circuit. It can be used in DVFS (Dynamic Voltage Frequency Scaling) system. Then we check the functionality of common used cell in digital circuits such as sequential cells, transmission gates, and other logic cells. Moreover, we’ll take a look at the circuit architecture to ensure the circuit not to deviate the optimal point too far.
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Sang, Chung-Sheng, and 桑崇陞. "Study of threshold-voltage Adjustable EG-FET as biosensor." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/16900442416517539021.
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碩士國立交通大學
材料科學與工程學系奈米科技碩博士班
101
Recently, real-time measurement in FET biosensor has been studied widely to detect and distinguish analyte in concentration instantly. To avoid unexpected chemical reaction and to provide a reference potential, the reference electrode in solution is kept grounded during experiment. However, under the real-time measurement, the characteristic of commercial FET devices are not suitable due to grounded reference electrode. Besides, the circumstance of device is disrupted by drift effect and hysteresis effect. Drift effect often occurs with construction and reconstruction of electric double layer and hysteresis effect happens with diffusion velocity of different ions in solution and competition of pKa of functional groups (-OH or -NH2 group) on the sensing chip. In this study, we investigated two method, VDS control method and inverter control method to stabilize the circumstance of solution under measurement. We regulated voltage of drain and source and kept gate electrode grounded to adjust the threshold voltage and setpoint. Moreover, inverter control method is designed to source grounded to stabilize FET device. In pH buffer measurement, drift effect and hysteresis effect were improved using VDS control method compared with conventional method. And the results showed that SAM can also stabilize the surface of sensing chip. In streptavidin measurement, concentration of streptavidin can be distinguished by surface potential change, and the limit of detection (LOD) is ~42 pM by using inverter control method. According to the results of our experiment, we believe that this technique can be applied to the future bio-sensing.
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Leo, Hon-Yuan, and 梁漢源. "Synchronous/Asynchronous 4-T SRAM Using Dual Threshold Voltage." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/10081186264260574324.
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碩士國立中山大學
電機工程學系研究所
91
英文提要： Two different topics associated with their respective applications are proposed in this thesis. The first topic is focused on the implementation of a 4-Kb 500MHz 4-T CMOS SRAM using low-Vthn bitline drivers and high-Vthp latches. The storage of data is realized by a pair of cross-coupled PMOS transistors, while the wordline is controlled by a pair of NMOS transistors. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. The second topic is the implementation of cascade address transition detector (ATD) design with high noise immunity. We employ a feedback loop to prevent interference of noise and false alarm signal to stabilize the generated CS (Chip Select) signal. Besides, we use one delay buffer to dynamically adjust the CS strobe.
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Chen, Tian-Hau, and 陳天豪. "A CMOS SRAM Using Dynamic Threshold Voltage Wordline Transistors." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/27384358009189966379.
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碩士國立中山大學
電機工程學系研究所
91
This thesis includes two topics. The first topic is a CMOS SRAM using dynamic threshold voltage wordline-transistors, which is focused on high speed applications. The second one is a high voltage generator for FLASH memories. The generated high voltages are applied to the wordline controlled transistors during access and verification operations. By taking advantage of the large current provided by low Vth and low leakage current provided by high Vth, a CMOS SRAM using dynamic threshold voltage wordline transistors is presented. The design of a 4-Kb SRAM is measured to possess a 2.2 ns access time, and consume 43.6 mW in the standby mode. The highest operating clock rate is estimated to be 667 MHz. A high voltage generator using 4 clocks with two phases is presented to provide a high voltage supply required by FLASH memories during programming mode and erase mode operations. The circuit is implemented by TSMC 0.25um 1P5M CMOS process. It can provide as high as +11.7 V and -11.6 V by given VDD=2.5 V.
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kang, ting kuo, and 康定國. "A Study of Threshold Voltage Extraction in MOSFET Devices." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/11929060087807077362.
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碩士大葉工學院
電機工程研究所
84
We clearly know that the accuracy of a device model in predictingdevice characteristics is dependent on the correct parameters of themodel. In the thesis, we completely investigate how to determine thethreshold voltage of MOSFET devices. In order to succeed in getting threshold voltage, we present a new physically based method for measuringthe threshold voltage of MOSFET devices. This novel method, called the bulk charge varying (BCV) method, is based on the drain current to include the bulk charge variation from the source end to the drain end. The BCV method will be a new accurately technique for experimentallyextracting the threshold voltage of MOSFET devices. Actually, the threshold voltage is functions of channel width and channel length. Based upon the BCV method, we will develope a new model,called the BCVW model, for the MOSFET threshold voltage profiling behaviorstrongly depends on the channel width of the devices. Meanwhile, the BCVWmodel is not sensitive to the measurement noise and error which is due toby using a nonlinear optimization method (L-M method). Nevertheless, an anomalous reverse short-channel effect has been detected in the DDD n-MOSFET devices. In order to solve the complex reverse short-channelproblem, the fuzzy theory and neural network techniques will be used in thefuture directed guide.
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Lin, Ji-Yong, and 林基永. "Power Consumption Optimization Methodology Using Mixed Threshold Voltage Cells for Low-Voltage Low-Power Designs." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/50233140909430674636.
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碩士國立臺灣大學
電子工程學研究所
101
This thesis reports a power consumption optimization methodology using mixed-threshold-voltage cells for low-voltage low-power designs. In Chapter 2, a power consumption optimization methodology (PCOM) using mixed-VTH (MVT) cells with for low-power designs has been presented. Via selecting MVT cell variant selection according to the “unbalanced timing arc” criteria and adopting a sensitivity-based cell assignment algorithm to integrate MVT cells out of HVT/LVT/MVT pools for the circuit optimization flow, the PCOM could provide a design as indicated in a 16-bit multiplier with 3811 cells, using a 90nm CMOS technology at 1V -under the tightest delay constraint a 45.36% reduction in power consumption as compared to the one using all-LVT cells. Then in Chapter 3, a critical-path aware power consumption optimization methodology (CPAPCOM) using mixed-VTH cells for low-power SOC designs has been presented. Using the critical-path weighted sensitivity as an index for assigning each cell to LVT, HVT or MVT cell, the CPAPCOM provides an effective power saving for a low-voltage/low-power SOC design, as indicated in the same 16-bit multiplier with a 44.90% reduction in power consumption as compared to the circuit using all-LVT cells.
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Huang, Ho-Hua, and 黃河樺. "Failure Analysis of Threshold Voltage Shift of High-Voltage Metal-Oxide-Semiconductor Field –Effect Transistors." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/51120602286693409015.
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碩士國立交通大學
工學院半導體材料與製程設備學程
101
The rapid increase in the demand of 3C consumer products requires a fast supply of a large quantity of flat panel displays of different dimensions. Nowadays, the liquid crystal display (LCD) is the standard display panel for various kinds of television sets, mobile phones and tablet computers. These LCD displays are controlled by integrated circuit (IC) drivers that are fabricated using the high-voltage (HV) metal-oxide-semiconductor (MOS) field-effect transistor (FET) process. The stability of the threshold voltage (VT) of HV-MOSFET drivers greatly affect the performance of the LCD panel displays. From the wafer acceptance test (WAT), two types of VT instability (or drift) are found to occur to the HV-MOSFET drivers. One type is a high VT in the P-type MOS (PMOS) but a low VT in the N-type MOS (NMOS); the other is a high VT in NMOS but a low VT in PMOS. In the thesis, we study the failure cause of the VT drift of the HV-MOSFET drivers. We used WAT analysis, in conjunction with various material analysis techniques, to study the dependence of the VT drift on the parameters of the fabrication processes of the HV-MOSFET drivers. From the study, we found that a thin initial oxide layer before the ion implantation (IMP) will result in a serious VT drift. The formation of the thin oxide layer may occur due to following improper process conditions: the time of IMP drive-in, the time for the pre-IMP wet clean, and the waiting time between the pre-IMP wet-clean and the IMP process.This study found that the main factor causing the VT drift of the HV-MOSFET driver was the wafer location in the furnace for the deposition of the sacrificial oxide and the pad oxide for the shallow trench isolation process. The placement of wafers on the top section of the furnace may result in an opposite VT drift to that on the bottom section. This is due to the non-uniform distribution of the oxygen flow in the furnace. The problem of the VT drift of the HV-MOSFET drivers was eliminated by the modification of the furnace deposition conditions of the pad oxide in the shallow trench isolation process.
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Chiang, Tai Yi, and 江泰逸. "Low Voltage Dynamic Logic Circuit Design Using PD SOI Dynamic-Threshold Voltage MOS (DTMOS) Techniques." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/63618067044843627667.
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碩士國立臺灣大學
電機工程學研究所
89
This thesis reports several low-voltage dynamic logic circuits using partially-depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques. In chapter 2, two novel true single-phase-clocking (TSPC) latches using PD SOI COMS DTMOS technique for low-voltage CMOS VLSI circuits are proposed. Via controlling the body voltage dynamically, the 0.8V split-output PD-SOI TSPC latch using DTMOS techniques shows an 80% reduction in the switching time and the non-split-output latch has less slow clock problems as verified by MEDICI result. In chapter 3, a 0.7V Manchester carry look-ahead circuit using PD SOI DTMOS techniques suitable for low-voltage CMOS VLSI systems is reported. Using asymmetrical dynamic threshold pass-transistor (ADTPT) technique with the PD-SOI DTMOS dynamic logic circuit, this 0.7V PD-SOI DTMOS Manchester carry look-ahead has an improvement of 30% in the propagation delay time as compared to the conventional circuit based on two-dimensional device simulation MEDICI results.
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"Novel dual-threshold voltage FinFETs for circuit design and optimization." Thesis, 2011. http://hdl.handle.net/1911/70416.
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A great research effort has been invested on finding alternatives to CMOS that have better process variation and subthreshold leakage. From possible candidates, FinFET is the most compatible with respect to CMOS and it has shown promising leakage and speed performance. This thesis introduces basic characteristics of FinFETs and the effects of FinFET physical parameters on their performance are explained quantitatively. I show how dual- V th independent-gate FinFETs can be fabricated by optimizing their physical parameters. Optimum values for these physical parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-14, FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than CMOS gates. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz and 75°C, the library that contains the novel gates reduces total power and the number of fins by 36% and 37% respectively, over a conventional library that does not have novel gates in the 32nm technology.
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TASI, YU-WEN, and 蔡侑文. "Analytical Solutions to the Threshold Voltage of Micro Curled Beams." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/69439106064591898627.
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碩士國立臺灣科技大學
機械工程系
93
The analytical modeling of the electrostatic devices is quite complicated and difficult in virtue of the electric-mechanical coupling effect, the nonlinearity of the electrostatic force, the fringe field, and the pre-deformation of the micro-structure caused by the residual stress and stress gradient. This thesis is to investigate the pull-in phenomenon of the pre-deformed microstructures subjected to electrostatic loads. High precision analytical modeling of the threshold voltage is established in this thesis. First of all, we use energy method to drive out the bending strain energy and electrical potential energy of the micro curled beam subjected to electrostatic loads. Based on the assumption of small deflection and adopting the Taylor series expansion, the expression of the total potential energy can be simplified as third-order and fourth-order models by omitting the terms with higher order than the third-order and the fourth-order respectively. Continuously, by the use of Rayleigh-Ritz method and assumed mode method, the approximate analytical solutions of the threshold voltage of curled beams are obtained based on the full-order, the third-order, and the fourth-order models respectively. The results obtained by this work agree more well to the experimental results compared to the published works. Five common used assumed deflection shape functions, including the natural mode, the uniform load deflection function, the concentrated load deflection function, the combined loads deflection function, and the square function are also compared with each other. The natural mode is verified to be the best choice. The numerical results show that the greatest error of the full-order model is below 8%, the one of the fourth-order model is below 9%, the one of the third-order model is below 18%, and the one of the literature is below 37%.
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Lin, Geng-Cing, and 林耕慶. "Device Threshold Voltage Measurement Circuit of Nano-scale CMOS SRAM." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60550065200696051283.
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碩士國立交通大學
電子研究所
100
Variation issue is one of the key design factors for robust current VLSI systems, and this kind of issue will affect the device threshold voltage (VTH) value. However, the VTH value is still associated with the device performance, stability and reliability, then when we talk about the variation issue that the VTH is the important indicator to reflect this phenomenon. So we want to create a measurement structure that can measure the device threshold voltage, then we can collect the voltage data to realize how the variation issue will affect this testing chip. We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (VTH) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the VTH measurement scheme is about 2-7mV at TT corner across temperature range from 85oC to -45oC, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit.
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Chung, Chun-Hua, and 鐘俊驊. "ILP-Based Multi-Threshold Voltage Assignment for Leakage Power Reduction." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/85654015920881135264.
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碩士中原大學
資訊工程研究所
97
Along with the shrink of Integrated Circuit (IC) process technology, the consumption of dynamic power reduces due to reduction of the supply voltage. However, the consumption of static power occupies a greater proportion of entire power consumption. The consumption of leakage power occupies about half of entire power consumption in 90nm process technology. Therefore, how to reduce the consumption of leakage power has become an important issue for the deep-submicron chip design in the future. This research paper proposes a method to reduce leakage power with the application of integer linear programming (ILP) on the swapping of multi-threshold voltage. The objective of this paper is to retain the performance of original circuit design while effectively minimizing the consumption of leakage power in various timing constraionts. First, we perform static timing analyze, as well as formulate the corresponding consumption of circuit power and timing model of integer linear programming. We then resolve the integer linear programming problem and acquire the optimal solution for the model of integer linear programming by using the commercial linear programming software (LINGO v11). This paper utilizes ISCAS’85 benchmark for the testing circuit; the benchmark circuit power consumption and timing model are realized with TSMC 90nm standard library. Comparing to the original design, the experimental results indicate that the dual-threshold and multi-threshold voltage approach can provide up to an average of 66.11% and 69.52% of leakage power reduction, respectively. In addition, the average runtime of our integer linear programming model in LINGO v11 for all circuits is less than three minutes.
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Yuan, Kuo-Hua, and 袁國華. "Modeling of PD-SOI Dynamic Threshold Voltage MOS (DTMOS) Devices." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/17904169823882612738.
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碩士國立臺灣大學
電機工程學研究所
87
In this thesis, analytical models for partially-depleted SOI dynamic-threshold MOS (DTMOS) devices are described. In Chapter 2, using the proposed quasi-2D approach, a closed-form threshold-voltage model for short-channel PD SOI DTMOS devices is obtained. Then, a drain current model in subthreshold region is introduced. As verified by experimental data and 2D simulation results, this analytical model provides an accurate prediction of the threshold-voltage and drain current behaviors of the short-channel PD SOI DTMOS devices. Based on the analytical model, as verified by the 2D simulation results, PD SOI DTMOS devices have less short-channel effects as compared to the devices without the DTMOS configuration. In Chapter 3, drain current models for PD SOI DTMOS devices in strong inversion region are derived. First, an electron mobility model considering electron temperature is derived using energy balance equation. Then, the drain current characteristics of DTMOS devices is divided into the triode region ($V_D < V_{DSAT}$) and the saturation region ( $V_D > V_{DSAT}$) . It is shown that the drain current of DTMOS devices is larger than standard MOS. At the end of Chapter 3, the DC and transient behaviors of the DTMOS inverter are simulated and analyzed.
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Lin, Jyun-Yi, and 林俊誼. "90nm Mixed-Threshold Voltage Standard Cell Library Design and Characterization." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/3b27xz.
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碩士國立交通大學
電子工程系所
96
With the advance of process technology and the increasing requirement of portable electric products, the power consumption of these products becomes very important. In this thesis, we first make the overview about the advanced characterization flow of timing and power in deep submicron CMOS standard cell library. Then, we propose a methodology using mixed-threshold voltage transistors in a circuit instead of single normal-threshold voltage transistors to reduce power consumption with the same timing performance. We find out the critical path and the critical transistors on the critical path that result in the longest delay time in the pull-up and pull-down networks, respectively. Then we replace the critical transistors with lower threshold voltage transistors and do resizing to meet the time performance of original circuits. Using this technique, we do not have to use additional transistors and do not change the structure of circuits to obtain the requirement of low power. Moreover, the leakage current is also blocked in most of the transistor paths. We apply this mixed-threshold voltage methodology to establish our 90nm low power standard cell library. Then we use many design examples to compare the performance with the high-Vt standard cell library and make the conclusion that we can have around 5% to 30% dynamic power saving, 20% to 55% delay-power product saving and the area is 0% to 40% larger than the standard cells with single high-Vt transistors.
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Huamg, Chia Feng, and 黃家楓. "Energy Efficiency Analysis for Near Threshold Voltage CMOS Logic Families." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/j73xu7.
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Hsu, Chih Wei, and 徐志維. "Hardware Sharing Near Threshold Voltage Carry Select Adder Circuit Design." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/q78uyy.
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