Relevant bibliographies by topics / Buffer layer architecture

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Buffer layer architecture'

Author: Grafiati
Published: 4 June 2021
Last updated: 20 February 2023

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Journal articles on the topic "Buffer layer architecture"

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Oh, Yong Jun, Jung Seok Ra, and Ui Gil Lee. "Effects of Deposition Parameters on the Crystallinities of CeO2 and Y2O3 Buffer Layers on Textured Ni Deposited by Magnetron Sputtering." Solid State Phenomena 124-126 (June 2007): 779–82. http://dx.doi.org/10.4028/www.scientific.net/ssp.124-126.779.

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The epitaxial growth conditions of CeO2 and Y2O3 single buffer layers on textured Ni tapes were examined using rf magnetron sputtering, and the process conditions for the sequential and mixture buffer layers of these two materials were investigated respectively in order to develop a more simplified buffer architecture. The CeO2 single layer exhibited a well developed (200) epitaxial growth at Ar/10%O2 gas below 450°C, although the epitaxial property was decreased with increasing layer thickness. With regard to the deposition of Y2O3 on Ni, the epitaxial growth was not successful. The epitaxy of Y2O3 on Ni was very sensitive to the O2 gas pressure during sputtering. The repeated sequential architecture of the CeO2 and Y2O3 layers exhibited a good epitaxial property at 400°C/(Ar/10%O2) for the initial CeO2 layer and 700°C/Ar and 700°C/(Ar/10%O2) for the subsequent Y2O3 and CeO2 layers, respectively. The Y-doped CeO2 buffers with (200) epitaxy were successfully obtained by the co-sputtering of Ce and Y metals in a reactive gas condition, and the maximum target Y/Ce ratio for the epitaxy was about 1/10.
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Gianni, L., A. Baldini, M. Bindi, A. Gauzzi, S. Rampino, and S. Zannella. "High Jc coated conductors with a simple buffer layer architecture." Physica C: Superconductivity and its Applications 426-431 (October 2005): 872–77. http://dx.doi.org/10.1016/j.physc.2005.03.037.

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Cheng, Wei-Kai, Xiang-Yi Liu, Hsin-Tzu Wu, Hsin-Yi Pai, and Po-Yao Chung. "Reconfigurable Architecture and Dataflow for Memory Traffic Minimization of CNNs Computation." Micromachines 12, no. 11 (November 5, 2021): 1365. http://dx.doi.org/10.3390/mi12111365.

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Computation of convolutional neural network (CNN) requires a significant amount of memory access, which leads to lots of energy consumption. As the increase of neural network scale, this phenomenon is further obvious, the energy consumption of memory access and data migration between on-chip buffer and off-chip DRAM is even much more than the computation energy on processing element array (PE array). In order to reduce the energy consumption of memory access, a better dataflow to maximize data reuse and minimize data migration between on-chip buffer and external DRAM is important. Especially, the dimension of input feature map (ifmap) and filter weight are much different for each layer of the neural network. Hardware resources may not be effectively utilized if the array architecture and dataflow cannot be reconfigured layer by layer according to their ifmap dimension and filter dimension, and result in a large quantity of data migration on certain layers. However, a thorough exploration of all possible configurations is time consuming and meaningless. In this paper, we propose a quick and efficient methodology to adapt the configuration of PE array architecture, buffer assignment, dataflow and reuse methodology layer by layer with the given CNN architecture and hardware resource. In addition, we make an exploration on the different combinations of configuration issues to investigate their effectiveness and can be used as a guide to speed up the thorough exploration process.
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Stan, L., P. N. Arendt, I. O. Usov, H. Wang, S. R. Foltyn, B. Maiorov, J. R. Groves, R. F. DePaula, and Y. Li. "Engineered reactive cosputtered SmxZr1–xOythin films as buffer layers for YBa2Cu3O7−δcoated conductors." Journal of Materials Research 22, no. 4 (April 2007): 1082–86. http://dx.doi.org/10.1557/jmr.2007.0138.

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This study shows that biaxially textured SmxZr1−xOy(SZO) with a wide range of compositions (0.06 <x< 0.75) can be grown directly on ion-beam-assisted deposition (IBAD) MgO template using reactive cosputtering. The SZO crystal structure can be changed, and the lattice parameter can be tailored (from 5.23 to 5.49 Å) by changing the composition. We have developed a simplified high-temperature superconducting coated conductor using SZO as the buffer layer. YBa2Cu3O7−δ(YBCO) films grown by pulsed laser deposition on the SZO buffered IBAD MgO have self-field critical current densities (Jc) in the 2–4 MA/cm2range. The in-field measurements demonstrate that high-quality YBCO films can be grown on SZO buffered IBAD MgO. The present results are especially important because they were obtained on coated conductors with the simpler architecture by eliminating the additional homoepitaxial layer of MgO. This translates in faster production and lower manufacturing cost.
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ARBER, LEON, and SCOTT PAKIN. "THE IMPACT OF MESSAGE-BUFFER ALIGNMENT ON COMMUNICATION PERFORMANCE." Parallel Processing Letters 15, no. 01n02 (March 2005): 49–65. http://dx.doi.org/10.1142/s0129626405002052.

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Of the many factors that contribute to communication performance, perhaps one of the least investigated is that of message-buffer alignment. Although the generally accepted practice is to page-align buffer memory for best performance, our studies show that the actual relationship of buffer alignment to communication performance cannot be expressed with such a simple formula. This paper presents a case study in which porting a simple network performance test from one language to another resulted in a large performance discrepancy even though both versions of the code consist primarily of calls to messaging-layer functions. Careful analysis of the two code versions revealed that the discrepancy relates to the alignment in memory of the message buffers. Further investigation revealed some surprising results about the impact of message-buffer alignment on communication performance: (1) different networks and node architectures prefer different buffer alignments; (2) page-aligned memory does not always give the best possible performance, and, in some cases, actually yields the worst possible performance; and, (3) on some systems, the most significant factor affecting network performance is the relative alignment of send and receive buffers with respect to each other.
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MUKHERJEE, SANKHA S., and SYED S. ISLAM. "EFFECTS OF BUFFER LAYER THICKNESS AND DOPING CONCENTRATION ON SiC MESFET CHARACTERISTICS." International Journal of High Speed Electronics and Systems 14, no. 03 (September 2004): 890–96. http://dx.doi.org/10.1142/s0129156404003009.

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Two-dimensional simulations have been carried out using the Atlas® device simulator to investigate the effects of the buffer layer thickness and doping concentration on the electrical characteristics of the SiC MESFET. The variations of transconductance, output resistance, gate-source capacitance, gate-drain capacitance and (cutoff frequency) f T with respect to the change in buffer layer thickness and doping concentration have been investigated. It is observed that the performances of MESFET can be improved by reducing the leakage of channel carrier into the substrate at high drain bias, which is achieved by increasing buffer layer doping density and/or increasing buffer layer thickness. For a SiC MESFET with buffer layer thickness of 0.3μm and gate length of 1μm, drain current increases from 0.1A/ μm to above 0.45A/ μm as the buffer layer doping density is decreased from 1.9 × 1017 cm -3 to 1 × 1016 cm -3. The simulations were carried out at a gate-source voltage of –1V and a drain-source voltage of 15V. Under similar conditions, the output resistance decreases from 1.2 × 106 Ω/μ m to 1.2 × 106 Ω/μ m , and the transconductance decreases from 5.9mS/ μm to 5.3mS/ μm, and f T decreases from 11GHz to 8GHz.
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Raphael, Johanna, Tedi Kujofsa, and J. E. Ayers. "Comparison of Buffer Layer Grading Approaches in InGaAs/GaAs (001)." International Journal of High Speed Electronics and Systems 29, no. 01n04 (March 2020): 2040002. http://dx.doi.org/10.1142/s0129156420400029.

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Metamorphic semiconductor devices often utilize compositionally-graded buffer layers for the accommodation of the lattice mismatch with controlled threading dislocation density and residual strain. Linear or step-graded buffers have been used extensively in these applications, but there are indications that sublinear, superlinear, S-graded, or overshoot graded structures could offer advantages in the control of defect densities. In this work we compare linear, step-graded, and nonlinear grading approaches in terms of the resulting strain and dislocations density profiles using a state-of-the-art model for strain relaxation and dislocation dynamics. We find that sublinear grading results in lower surface dislocation densities than either linear or superlinear grading approaches.
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Aytug, T., J. Z. Wu, B. W. Kang, D. T. Verebelyi, C. Cantoni, E. D. Specht, A. Goyal, M. Paranthaman, and D. K. Christen. "An all-sputtered buffer layer architecture for high-Jc YBa2Cu3O7−δ coated conductors." Physica C: Superconductivity 340, no. 1 (November 2000): 33–40. http://dx.doi.org/10.1016/s0921-4534(00)01331-9.

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Wang, H., S. R. Foltyn, P. N. Arendt, Q. X. Jia, J. L. MacManus-Driscoll, L. Stan, Y. Li, X. Zhang, and P. C. Dowden. "Microstructure of SrTiO3 buffer layers and itseffects on superconducting properties ofYBa2Cu3O7-δ coated conductors." Journal of Materials Research 19, no. 6 (June 2004): 1869–75. http://dx.doi.org/10.1557/jmr.2004.0244.

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A thin layer of SrTiO3 (STO) has successfully been used as a buffer layer to grow high-quality superconducting YBa2Cu3O7-δ(YBCO) thick films on polycrystalline metal substrates with a biaxially oriented MgO template produced by ion-beam-assisted deposition. Using this architecture, 1.5-μm-thick YBCO films with an in-plane mosaic spread in the range of 2.5° to 3.5° in full width at half-maximum and critical current density over 2 × 10 6A/cm2 in self-field at 75 K have routinely been achieved. It is interesting to note that the pulsed laser deposition growth conditions of SrTiO3 buffer layers, such as growth temperature and oxygen pressure, have strong effects on the superconducting properties of YBCO. Detailed studies using transmission electron microscopy, scanning electron microscopy, and atomic force microscopy were used to explore the microstructures of STO deposited at different conditions and to understand further their effects on the growth and properties of YBCO films.
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RAJAN, SIDDHARTH, ARPAN CHAKRABORTY, UMESH K. MISHRA, CHRISTIANE POBLENZ, PATRICK WALTEREIT, and JAMES S. SPECK. "MBE-Grown AlGaN/GaN HEMTs on SiC." International Journal of High Speed Electronics and Systems 14, no. 03 (September 2004): 732–37. http://dx.doi.org/10.1142/s0129156404002752.

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We report on the development of AlGaN/GaN high-electron mobility transistors (HEMTs) grown on SiC using plasma-assisted molecular beam epitaxy (MBE). In this work, we show that performance comparable to state-of-the-art AlGaN/GaN HEMTs can be achieved using MBE-grown material. Buffer leakage was an important limiting factor for these devices. The use of either carbon-doped buffers, or low Al/N ratio in the nucleation layer growth were effective in reducing buffer leakage. Studies varying the thickness and concentration of the carbon doping were carried out to determine the effect of different carbon doping profiles on the insulating and dispersive properties of buffers, On devices without field plates, at 4 GHz an output power density of 12 W/mm was obtained with a power-added efficiency (PAE) of 46 % and gain of 14 dB. 15.6 W/mm with PAE of 56 % was obtained from these devices after field-plating. Two-tone linearity measurements of these devices were also carried out. At a C/I 3 level of 30 dBc, the devices measured had an output power of 1.9 W/mm with a PAE of 53 %. The effect of the Al/N ratio in the AlN nucleation layer on buffer leakage was studied. N -rich conditions yielded highly insulating GaN buffers without carbon doping. At 4 GHz, devices without field plates delivered 4.8 W/mm with a PAE of 62 %. At a higher drain bias (50 V), 8.1 W/mm with a PAE of 38 % was achieved.
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Dissertations / Theses on the topic "Buffer layer architecture"

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Al, Ibrahim Ali Abdullah H. "Development of CexSm1-xO2-δ as an Insulation Barrier via Chemical Deposition of Aerosol Nanoparticles for Applications for High Temperature Superconductor Power Cables in Sustainable and Renewable Energy." Thesis, Griffith University, 2016. http://hdl.handle.net/10072/365828.

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A significant effort has been made recently to develop second-generation HTSC tapes. In these tapes, ReBaCuO (rare-earth barium copper oxide - YBCO) thin films are produced on metallic substrates, such as textured Ni, NiW alloys and stainless steel. To prevent the interdiffusion of elements between metal substrate and superconducting material, and to match the YBCO lattice parameters with the substrate texture, different buffer layers were deposited on the substrate. In commercially available HTSC tapes, several buffer layers are typically used to obtain high-quality YBCO superconductor coatings (i.e. appropriate texture, defect-free and with a high critical current density, Jc,). Many existing HTS tape technologies use a variety of buffer layer architecture, which include YSZ, MgO, Y2O3 and CeO2 nm-thick layers and their combinations.
Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
Griffith School of Engineering
Science, Environment, Engineering and Technology
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Engel, Sebastian. "Chemisch deponierte Schichtsysteme zur Realisierung von YBa2Cu3O7−d-Bandleitern." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2009. http://nbn-resolving.de/urn:nbn:de:bsz:14-ds-1244452357143-40430.

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Die vorliegende Arbeit beschäftigt sich mit der Entwicklung neuer Schichtsysteme für die Realisierung biaxial texturierter hochtemperatursupraleitender Bandleiter. Bisher sind eine Vielzahl von Bandleiterarchitekturen bekannt, die sowohl durch physikalische Depositionsmethoden als auch mittels Abscheidung aus der chemischen Lösung hergestellt werden können. Während die Funktion von YBCO-Bandleitern mit Hilfe physikalischer Depositionsmethoden in den letzten Jahren demonstriert werden konnte, zeigen auf chemischem Wege deponierte Bandleiter schlechtere Eigenschaften. Seitens der Industrie besteht ein starkes Interesse, die hohen Produktionskosten, die im Hinblick auf physikalische Depositionsmethoden mit einem hohen Anlagenaufwand verbunden sind, anhand der kostengünstigen chemischen Synthese von Einzelschichten oder der gesamten Bandleiterarchitektur zu senken. Gelöst wurde diese Aufgabe innerhalb der vorliegenden Arbeit durch die Entwicklung metallorganischer Vorstufenlösungen zur Deposition von CaTiO3-, SrTiO3-Pufferschichten und supraleitender YBa2Cu3O7-Schichten.
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Engel, Sebastian. "Chemisch deponierte Schichtsysteme zur Realisierung von YBa2Cu3O7−d-Bandleitern." Doctoral thesis, Technische Universität Dresden, 2008. https://tud.qucosa.de/id/qucosa%3A23824.

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Die vorliegende Arbeit beschäftigt sich mit der Entwicklung neuer Schichtsysteme für die Realisierung biaxial texturierter hochtemperatursupraleitender Bandleiter. Bisher sind eine Vielzahl von Bandleiterarchitekturen bekannt, die sowohl durch physikalische Depositionsmethoden als auch mittels Abscheidung aus der chemischen Lösung hergestellt werden können. Während die Funktion von YBCO-Bandleitern mit Hilfe physikalischer Depositionsmethoden in den letzten Jahren demonstriert werden konnte, zeigen auf chemischem Wege deponierte Bandleiter schlechtere Eigenschaften. Seitens der Industrie besteht ein starkes Interesse, die hohen Produktionskosten, die im Hinblick auf physikalische Depositionsmethoden mit einem hohen Anlagenaufwand verbunden sind, anhand der kostengünstigen chemischen Synthese von Einzelschichten oder der gesamten Bandleiterarchitektur zu senken. Gelöst wurde diese Aufgabe innerhalb der vorliegenden Arbeit durch die Entwicklung metallorganischer Vorstufenlösungen zur Deposition von CaTiO3-, SrTiO3-Pufferschichten und supraleitender YBa2Cu3O7-Schichten.
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Brecher, Emma. "Poll- otter architecture : For an urban environment sinking under layers of barriers : With focus on the boundary wall as an architectural medium to support the urban condition." Diss., University of Pretoria, 2018. http://hdl.handle.net/2263/63677.

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The area of investigation for this study falls within a small urban island called Westbury. Situated 7km to the West of Johannesburg’s CBD, it is isolated from the adjacent urban fabric as a result of its historical and also recent development. Westbury itself also consists of a series of fragmented islands with undefined boundaries, weak urban blocks and a disorientated grid. The area has recently been identified as a high priority region for densification1 by the city of Johannesburg, supported by transport-oriented infra-structural investment. The questions raised by this study are contextualized against this backdrop. How could densification in Westbury be achieved towards the creation of a more inter-connected, cohesive, accessible and therefore sustainable urban environment? Following from this: How could Westbury be better integrated with the immediate surrounding urban fabric whilst combating its own fragmentation? What is the role of urban blocks and boundary conditions to help shape a future more integrated Westbury, and also towards meaningful place-making? In what ways can architecture contribute in order to improve the urban fabric that operates on various scales: from the very scale of the house to that of an urban boundary to that of the urban block and ultimately the greater urban network? The hypothesis outlined in this study is that architecture is too weak to stand in isolation, that a network of buildings is necessary to achieve a more sustainable, accessible, cohesive, and inter-connected urban environment. This is tested through a rigorous analysis of boundary conditions at different scales as reflected in the urban blocks of Westbury and the resultant architectural strategies. Finally, a block and its attendant boundaries is singled out to test the architectural contribution towards densification of the suburb, the making of place, and better inter-connectivity. The process is envisaged as driven from both the scale at which urban issues inform the architecture, and the reverse scale the architecture in Westbury informs the urban master plan. The architecture in style and scale sets the conditions for the proposed urban blocks. The boundary wall being the medium where urban meets architecture. “For these dreams to flourish in reality, we must recognise that there can be no ready-made solutions in housing, no recipes or
Mini Dissertation (MArch (Prof))--University of Pretoria, 2018.
Architecture
MArch (Prof)
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Book chapters on the topic "Buffer layer architecture"

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Paranthaman, M. Parans, T. Aytug, H. Y. Zhai, H. M. Christen, D. K. Christen, A. Goyal, L. Heatherly, and D. M. Kroeger. "Development of Low-Cost Alternative Buffer Layer Architectures for Ybco Coated Conductors." In Ceramic Transactions Series, 33–42. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2012. http://dx.doi.org/10.1002/9781118406106.ch5.

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Conference papers on the topic "Buffer layer architecture"

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Eugin Hyun and Kwang-Su Seong. "The effective buffer architecture for data link layer of PCI express." In International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004. IEEE, 2004. http://dx.doi.org/10.1109/itcc.2004.1286569.

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Su, Zonghui, Jonathan A. Malen, Li Huang, and Robert F. Davis. "Temperature Dependent Thermal Properties in LEDs for Solid State Lighting." In ASME 2012 Third International Conference on Micro/Nanoscale Heat and Mass Transfer. American Society of Mechanical Engineers, 2012. http://dx.doi.org/10.1115/mnhmt2012-75077.

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Over 20% of electricity in US is used by lighting. Solid state lighting (SSL) efficiency can surpass that of incandescent and fluorescent lighting techniques. Nonetheless SSL efficiency is greatly reduced at high temperatures that result from inadequate heat dissipation. SSL requires blue and green light emitting diodes (LEDs) made from Gallium Nitride (GaN) and Indium Gallium Nitride (InGaN) to eventually generate white light. Conduction within the LED is a major thermal resistance for heat dissipation, and motivates study of thermal properties of LED materials, including GaN and InGaN. Bulk thermal properties are poor estimates of thin film properties due to increased boundary and defect scattering of phonons in the films. By examining real nitride based LED architectures with the 3-omega technique, thin film thermal conductivities of nucleation, buffer, contact, and active regions were measured from 100–400K. We find that the AlN nucleation layer is a bottleneck to heat transfer, having a thermal conductivity (κ) two orders of magnitude less than bulk crystalline AlN. Further, the temperature dependent behavior is characteristic of an amorphous solid. TEM images of the AlN layer show a very high dislocation density (4×1010 cm−2). We hypothesize that scattering from these dislocations as well as the film boundaries, causes the observed behavior.
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Lu, Taiwei, Kyusun Choi, Shudong Wu, Xin Xu, and Francis T. S. Yu. "Optical disk-based neural network." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1989. http://dx.doi.org/10.1364/oam.1989.wj4.

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The rapid growth of optical disk storage techniques provides an advantage for optics in large capacity information storage and processing. Here we propose an optical disk-based neural network architecture for high speed and large capacity associative processing. The interpattern association (IPA) neural network model is used to generate the tristate interconnection weight matrices (IWMs). Each IWM is stored in two blocks (i.e., positive and negative matrices) on the disk, and read out in parallel by separate pulse laser beams. The two readout beams are encoded in perpendicular polarizations and then directed to a parallel optical matrix-vector processor, which consists of a lenslet array, an input SLM, and two photodetector arrays. Parallel buffers and a postprocessing circuit would be used to alleviate the electronic bottleneck to some extent.
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Zhang, Xin, Yingxin Li, Yulong Zhang, Zuhui Chen, Shi Liu, Richard D. Nelson, and John C. LaRue. "Design of Microcontroller Based Test Bench for a Multichannel Integrated Biosensor Chip." In ASME 2009 Summer Bioengineering Conference. American Society of Mechanical Engineers, 2009. http://dx.doi.org/10.1115/sbc2009-206841.

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The planar microelectrode array (pMEA) is an important tool for non-invasive recording in the fields of neuroscience and biosensing. It can be used for extra-cellular measurement of the induced voltage on an electrode underneath a cell upon the occurrence of an action potential. With the principle of capacitive coupling, the sensed electrode signal amplitudes typically range between 100 μV and 1 mV, depending on the cell type. Due to the small amplitude of original neural signals, signal conditioning and processing microelectronics units are necessary to integrate with the pMEA sensor for achievement of best measurement performance. Introducing fully customized ASIC into the microelectrode array substrate provides an efficient solution, which establishes the possibility of creating the biosensor system on chip (SoC) with a large number of sensing-sites for simultaneous measurement without introducing significant noise from the signal conditioning and processing circuitry [1]. In this research work, we have developed a fully customized biosensor chip for sensing the propagation of action potentials. With the paralleled multiple sub-circuits, this prototype multi-site planar microelectrode array biosensor integrates 24 (4 × 6) microelectrode array sensing sites, 24 parallel analog neural signal buffers and a shared OTA based high gain amplifier on the same substrate. Figure 1 depicts the biosensor chip architecture and the functional blocks of the biosensor system setup. The prototyped biosensor chip was fabricated by MOSIS using AMI C5 0.5μm, double poly, triple metal layer CMOS technology. The electroless gold plating process post-CMOS processing and packaging techniques were applied to the biosensor chip to promote the biocompatibility and stability in the aqueous cell culture environment. To interface the biosensor chip with PC, a microcontroller based electronic system is necessary to implement the functions of A/D conversion, biosensor chip control signal generation, digital signal processing and data/command communication between biosensor chip and GUI software running on PC. In this research work, a Motorola ColdFire MCF5307 microcontroller based electronic system was setup to serve as the interface between the biosensor chip and PC, which realized the full functions listed above. The firmware running on MCF5307 microcontroller was implemented with ColdFire assembly language where on the PC client Matlab platform was chosen to simply the software design work.
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