Relevant bibliographies by topics / Built-in self test

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Built-in self test'

Author: Grafiati
Published: 4 June 2021
Last updated: 26 July 2025

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Journal articles on the topic "Built-in self test"

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Kiran, Kumar Gopathoti, and Sunil Kumar G. "Built-in Self-Test Algorithm for Functional Broadside Tests." Journals of Advancement in Electronics Design 5, no. 3 (2022): 1–9. https://doi.org/10.5281/zenodo.7476638.

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<em>In this paper, we propose a technique for weighted test sequence generation for synchronous sequential circuit&rsquo;s on-chip. Three weights&mdash;0, 0.5, and 1&mdash;are adequate for combinational circuits to completely cover stuck-at failures because they can accurately duplicate any given test pattern. We define the weights for sequential circuits based on subsequences of a deterministic test sequence. These weights enable us to partially replicate the test sequence and assure that the resulting weighted test sequences would receive full fault coverage. This accumulator-based 3-weight
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Zorian, Yervant. "Built-in self-test." Microelectronic Engineering 49, no. 1-2 (1999): 135–38. http://dx.doi.org/10.1016/s0167-9317(99)00434-7.

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McCluskey, Edward. "Built-In Self-Test Techniques." IEEE Design & Test of Computers 2, no. 2 (1985): 21–28. http://dx.doi.org/10.1109/mdt.1985.294856.

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McCluskey, Edward. "Built-In Self-Test Structures." IEEE Design & Test of Computers 2, no. 2 (1985): 29–36. http://dx.doi.org/10.1109/mdt.1985.294857.

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Ungar, L. Y., and T. Ambler. "Economics of built-in self-test." IEEE Design & Test of Computers 18, no. 5 (2001): 70–79. http://dx.doi.org/10.1109/54.953274.

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Seuring, Markus. "Combining Scan Test and Built-in Self Test." Journal of Electronic Testing 22, no. 3 (2006): 297–99. http://dx.doi.org/10.1007/s10836-006-8950-7.

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Adham, S., M. Kassab, J. Rajski, and J. Tyszer. "Built-in self test of digital decimators." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 42, no. 7 (1995): 486–92. http://dx.doi.org/10.1109/82.401174.

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Gloster, C. S., and F. Brglez. "Boundary scan with built-in self-test." IEEE Design & Test of Computers 6, no. 1 (1989): 36–44. http://dx.doi.org/10.1109/54.20388.

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Deb, N., and R. D. Blanton. "Built-In Self-Test of MEMS Accelerometers." Journal of Microelectromechanical Systems 15, no. 1 (2006): 52–68. http://dx.doi.org/10.1109/jmems.2006.864239.

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Mir, S., L. Rufer, and A. Dhayni. "Built-in-self-test techniques for MEMS." Microelectronics Journal 37, no. 12 (2006): 1591–97. http://dx.doi.org/10.1016/j.mejo.2006.04.016.

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Dissertations / Theses on the topic "Built-in self test"

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Zhang, Shujian. "Evaluation in built-in self-test." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ34293.pdf.

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Bogue, Tracey M. "Aliasing reduction in built-in self-test." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/nq21280.pdf.

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Dhawan, Sanjay. "A built-in self-test PLA generator." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-08042009-040315/.

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XIONG, XINGGUO. "BUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1123038236.

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Ho, Thanh Huong. "Test compaction technique for built-in self-test in VLSI circuits." Thesis, University of Ottawa (Canada), 1994. http://hdl.handle.net/10393/6460.

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In recent years, many test output data compression techniques have been introduced, which reduce the storage requirements of reference signatures for the circuit under test. A major problem, however, is that the compression always results in loss of error coverage. This work proposes a space compression technique for digital circuits with the objective of minimizing the storage for the circuits under test while maintaining the fault coverage information. The technique introduced is called a Modified Dynamic Space Compression method. For a circuit under test, a compaction tree is generated base
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Muradali, Fidel. "A self-driven test methodology for built-in self-test of sequential circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ30348.pdf.

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Muradali, Fidel. "A self-driven test methodology for built-in self-test of sequential circuits /." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=42106.

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Test cost comprises a substantial portion of producing an integrated circuit. As a result, structural modifications of the circuit via design for test (DFT) techniques are commonly used as an aid to reduce test cost to the lowest possible level. One important class of DFT is Built-In Self-Test (BIST). In BIST, test generation and response analysis logic is integrated into the original circuit and are transparent during normal operation. In this manner, in-circuit tests can be performed with minimal need of external test equipment, if any.<br>Test strategies based on pseudorandom test stimuli a
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Khalaf, Arkan. "A self-reconfigurable platform for built-in-self-test applications." Thesis, University of Ottawa (Canada), 2007. http://hdl.handle.net/10393/27865.

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This thesis introduces a novel architecture of a run-time reconfigurable microsystem on chip (SoC). This system consists of a logic block that can be reconfigured at run time, and an embedded multi-microprocessor system that connects to this logic block and can reconfigure it at run time using special resources of Field Programmable Gate Arrays (FPGA). A design flow for run-time reconfigurable logic circuits has been developed and is presented in the context of the implementation of the SoC on a FPGA. This reconfigurable architecture is validated by an application that implements the novel ide
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Radecka, Katarzyna. "Arithmetical built-in self test for DSP architectures." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ29624.pdf.

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Olbrich, Thomas. "Design-for-Test and Built-In-Self-Test for integrated systems." Thesis, Lancaster University, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.312594.

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Books on the topic "Built-in self test"

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Jerzy, Tyszer, ed. Arithmetic built-in self-test for embedded systems. Prentice Hall PTR, 1998.

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Barus, Jasa. An analysis of aliasing in built-in self test procedure. Naval Postgraduate School, 1991.

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Bou-Sleiman, Sleiman, and Mohammed Ismail. Built-in-Self-Test and Digital Self-Calibration for RF SoCs. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4419-9548-3.

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Bou-Sleiman, Sleiman. Built-in-Self-Test and Digital Self-Calibration for RF SoCs. Springer Science+Business Media, LLC, 2012.

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Jervan, Gert. Hybrid built-in self-test and test generation techniques for digital systems. Dept. of Computer and Information Science, Univ., 2005.

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Jervan, Gert. High-level test generation and built-in self-test techniques for digital systems. Department of Computer and Information Science, Linköpings universitet, 2002.

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Roberts, Gordon W., and Albert K. Lu. Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2341-3.

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Roberts, Gordon W. Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits. Springer US, 1995.

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Roberts, Gordon W. Analog signal generation for built-in-self-test of mixed-signal integrated circuits. Kluwer Academic Publishers, 1995.

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Plaskova, Nataliya. Analysis of financial statements prepared in accordance with IFRS. INFRA-M Academic Publishing LLC., 2021. http://dx.doi.org/10.12737/1121571.

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The textbook introduces modern methods and techniques for analyzing the activities of a commercial organization using the information contained in its financial statements prepared in accordance with International Financial Reporting Standards. Considerable attention is paid to the disclosure of calculation and analytical procedures for identifying and quantifying the impact of factors on the level of business performance. The presentation of each chapter is accompanied by practical calculation and analytical materials using the "cross-cutting task" technique, the initial information base of w
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Book chapters on the topic "Built-in self test"

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Wang, Ran, and Krishnendu Chakrabarty. "Built-In Self-Test." In Testing of Interposer-Based 2.5D Integrated Circuits. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-54714-5_5.

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Lala, Parag K. "Built-in Self-Test." In An Introduction to Logic Circuit Testing. Springer International Publishing, 2009. http://dx.doi.org/10.1007/978-3-031-79785-9_4.

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Bou-Sleiman, Sleiman, and Mohammed Ismail. "RF Built-in-Self-Test." In Built-in-Self-Test and Digital Self-Calibration for RF SoCs. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9548-3_4.

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Navabi, Zainalabedin. "Logic Built-in Self-test." In Digital System Test and Testable Design. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_9.

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Zhao, Yang, and Krishnendu Chakrabarty. "Built-In Self Test and Diagnosis." In Design and Testing of Digital Microfluidic Biochips. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0370-8_5.

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Noia, Brandon, and Krishnendu Chakrabarty. "Built-In Self-Test for TSVs." In Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs. Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-02378-6_3.

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Bou-Sleiman, Sleiman, and Mohammed Ismail. "RF Built-in-Self-Calibration." In Built-in-Self-Test and Digital Self-Calibration for RF SoCs. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9548-3_5.

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Corno, Fulvio, Matteo Sonza Reorda, and Giovanni Squillero. "Built-In Self Test of Sequential Circuits." In Evolutionary Algorithms for Embedded System Design. Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-1035-2_5.

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Bou-Sleiman, Sleiman, and Mohammed Ismail. "Radio Systems Overview: Architecture, Performance, and Built-in-Test." In Built-in-Self-Test and Digital Self-Calibration for RF SoCs. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9548-3_2.

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Vanithamani, P., G. Sudhagar, and T. Prathiba. "Robust test pattern generators for secure built-in self-test implementation." In Recent Trends in VLSI and Semiconductor Packaging. CRC Press, 2025. https://doi.org/10.1201/9781003616399-67.

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Conference papers on the topic "Built-in self test"

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Govindaraj, V., and Haritha M. "A Low Transition Built-In Self-Test with Compressed Tests for Test Power Reduction." In 2025 7th International Conference on Inventive Material Science and Applications (ICIMA). IEEE, 2025. https://doi.org/10.1109/icima64861.2025.11074065.

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Kamath M, Shrinivas Anand, and Sujatha Hiremath. "Design and Verification of Power Efficient Built-In Self-Test." In 2024 8th International Conference on Computational System and Information Technology for Sustainable Solutions (CSITSS). IEEE, 2024. https://doi.org/10.1109/csitss64042.2024.10816809.

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Hakmi, Abdul-Wahid, Hans-Joachim Wunderlich, Christian G. Zoellin, Andreas Glowatz, and Friedrich Hapke. "Programmable deterministic Built-In Self-Test." In 2007 IEEE International Test Conference. IEEE, 2007. http://dx.doi.org/10.1109/test.2007.4437611.

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"Session TB3: Built-in-Test and Self-Test." In 2005 IEEE Instrumentationand Measurement Technology Conference Proceedings. IEEE, 2005. http://dx.doi.org/10.1109/imtc.2005.1604092.

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Ravi, R., S. Kannadhasan, K. Ramachandran, K. Deepa, R. Thabathi, and S. Kalaivani. "Built in Self Test on Random Test Pattern Generation for Test Compression." In 2023 International Conference on Self Sustainable Artificial Intelligence Systems (ICSSAS). IEEE, 2023. http://dx.doi.org/10.1109/icssas57918.2023.10331724.

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Boey, Kean Hong, Kok Sing Yap, and Wai Mun Ng. "USB2.0 Logic Built In Self Test Methodology." In 2008 17th Asian Test Symposium (ATS). IEEE, 2008. http://dx.doi.org/10.1109/ats.2008.84.

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Tsai, Yu-Chih, Wen-Chien Ting, Chia-Chun Wang, Chia-Cheng Chang, and Ren-Shuo Liu. "Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory." In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2023. http://dx.doi.org/10.23919/date56975.2023.10137074.

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Abielmona, Rami, Voicu Groza, and Arkan Khalaf. "Run-Time Reconfigurable Built-in-Self-Test." In 2006 Canadian Conference on Electrical and Computer Engineering. IEEE, 2006. http://dx.doi.org/10.1109/ccece.2006.277610.

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Muthammal, R., and K. O. Joseph. "Low power efficient built in self test." In 2011 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS). IEEE, 2011. http://dx.doi.org/10.1109/comcas.2011.6105942.

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Pulukuri, Mary D., George J. Starr, and Charles E. Stroud. "On Built-In Self-Test for multipliers." In SOUTHEASTCON 2010. IEEE, 2010. http://dx.doi.org/10.1109/secon.2010.5453929.

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Reports on the topic "Built-in self test"

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Huatian, Xu, and Bi Wuxi. PR469-183600-R01 The Influence of Solid State Decouplers on Pipeline CP Surveys. Pipeline Research Council International, Inc. (PRCI), 2020. http://dx.doi.org/10.55274/r0011935.

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The objectives of this research are to figure out how solid state decouplers (SSDs) influence the surveys related to pipeline cathodic protection (CP) and provide corresponding field guidelines on how to mitigate the adverse effects of SSDs. Firstly, by combining the classical capacitor discharge theory and the equivalent circuit of the CP system, a four-stage physical model is built to explain how SSDs' discharge current pulse influences the CP related readings. From the physical model, we can obtain the following conclusions: (1) The driving force behind the discharging of an SSD's capacitor
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Wu, Yingjie, Selim Gunay, and Khalid Mosalam. Hybrid Simulations for the Seismic Evaluation of Resilient Highway Bridge Systems. Pacific Earthquake Engineering Research Center, University of California, Berkeley, CA, 2020. http://dx.doi.org/10.55461/ytgv8834.

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Bridges often serve as key links in local and national transportation networks. Bridge closures can result in severe costs, not only in the form of repair or replacement, but also in the form of economic losses related to medium- and long-term interruption of businesses and disruption to surrounding communities. In addition, continuous functionality of bridges is very important after any seismic event for emergency response and recovery purposes. Considering the importance of these structures, the associated structural design philosophy is shifting from collapse prevention to maintaining funct
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