Relevant bibliographies by topics / Built-In Self Test (BIST) techniques

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Built-In Self Test (BIST) techniques'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 February 2022

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Journal articles on the topic "Built-In Self Test (BIST) techniques"

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Lu, Shyue-Kung, Yuang-Cheng Hsiao, Chia-Hsiu Liu, and Chun-Lin Yang. "Low-Power Built-In Self-Test Techniques for Embedded SRAMs." VLSI Design 2007 (October 29, 2007): 1–6. http://dx.doi.org/10.1155/2007/67019.

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The severity of power consumption during parallel BIST of embedded memory cores is growing significantly. In order to alleviate this problem, a row bank-based precharge technique based on the divided wordline (DWL) architecture is proposed for low-power testing of embedded SRAMs. The memory cell array is first divided into row banks. The effectiveness of the row bank-based precharge technique is due to the predictable address sequence during test. In low-power test mode, instead of precharging the entire memory array, only the current accessed row bank is precharged. This will result in significant power saving for the precharge circuitry. The precharge power can be reduced to 1/b of that of the traditional precharge techniques, where b denotes the number of row banks in the memory array. With simple transmission gates and inverters, the modified precharge control circuitry was also designed. The hardware overhead for implementing the low-power technique is almost negligible. Moreover, the corresponding BIST design to implement the low-power technique is almost the same as the conventional BIST designs. It is also notable that the inherent low-power characteristics of the DWL architecture can be preserved. According to experimental results, 48.9% power reduction can be achieved for a 256 × 256 bit-oriented SRAM. The memory is divided into 8 row banks. Moreover, if the number of row banks increases, the power saving will also increase.
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Chen, Chien-In Henry. "Partitioning Techniques for Built-In Self-Test Design." VLSI Design 2, no. 3 (January 1, 1994): 185–98. http://dx.doi.org/10.1155/1994/25656.

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An efficient, unified algorithm, Advanced Two-Phase Cluster Partitioning, is proposed for automated synthesis of pseudo-exhaustive test generator for Built-In Self-Test (BIST) design. A prototype of the algorithm, Two-Phase Cluster Partitioning, has been proposed and the hierarchical design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. However, in certain worst case, the algorithm may generate a sub-optimal design which requires more test patterns and/or hardware overhead. In order to generate a globally optimal design, further improvement of two-phase algorithm can be achieved by expanding the design space for the formation of linear sum so that the number of test signals required for pseudo-exhaustive testing can be reduced. We demonstrate the effectiveness of our approach by presenting detailed comparisons of our results against those that would be obtained by existing techniques.
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Savir, Jacob, and Paul H. Bardell. "Built-In Self-Test: Milestones and Challenges." VLSI Design 1, no. 1 (January 1, 1993): 23–44. http://dx.doi.org/10.1155/1993/81360.

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This paper describes the progress in built-in self-test (BIST) since its inception, and the important problems that still need to be solved to make the technique widely acceptable. The paper includes a reference list and an extensive bibliography on the subject matter.
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Imocha Singh, Nongthombam, and Prashant V. Joshi. "A Brief Review for Semiconductor Memory Testing Based on BIST Techniques." International Journal of Engineering & Technology 7, no. 3.1 (August 4, 2018): 98. http://dx.doi.org/10.14419/ijet.v7i3.1.16807.

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With rapid growth of semiconductor industry and increase in complexity of semiconductor based memory, necessity of stringent testing methodology has become one of top most criteria for memory evaluation. This paper describes the fundamental concepts and overview of Built-In-Self-Test (BIST). It describes different functional faults modeling of RAM and flash memory. This review mentions about testing approaches for memory and illustrates BIST techniques for finding faults, power dissipation, area overhead and test time during testing, also includes research gap and future scope regarding the testing of memory.
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Ince, Mehmet, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, Leroy Winemberg, and Sule Ozev. "Fault-based Built-in Self-test and Evaluation of Phase Locked Loops." ACM Transactions on Design Automation of Electronic Systems 26, no. 3 (February 2021): 1–18. http://dx.doi.org/10.1145/3427911.

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With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.
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Balasubramanian, Anitha, B. L. Bhuva, L. W. Massengill, B. Narasimham, R. L. Shuler, T. D. Loveless, and W. Timothy Holman. "A Built-In Self-Test (BIST) Technique for Single-Event Testing in Digital Circuits." IEEE Transactions on Nuclear Science 55, no. 6 (December 2008): 3130–35. http://dx.doi.org/10.1109/tns.2008.2006499.

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Varaprasad, B. K. S. V. L., L. M. Patnaik, H. S. Jamadagni, and V. K. Agrawal. "An Efficient Test Pattern Generation Scheme for an On Chip BIST." VLSI Design 12, no. 4 (January 1, 2001): 551–62. http://dx.doi.org/10.1155/2001/45324.

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Testing and power consumption are becoming two critical issues in VLSI design due to the growing complexity of VLSI circuits and remarkable success and growth of low power applications (viz. portable consumer electronics and space applications). On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip. This paper deals with cost-effective Test Pattern Generation (TPG) schemes in BIST. We present a novel methodology based on the use of a suitable Linear Feedback Shift Register (LFSR) which cycles through the required sequences (test vectors) aiming at a desired fault coverage causing minimum circuit toggling and hence low power consumption while testing. The proposed technique uses circuit simulation data for modeling. We show how to identify the LFSR using graph theory techniques and compute its feedback coefficients (i.e., its characteristic polynomial) for realization of a Test Pattern Generator.
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, Dr. K Deepti, P. Aishwarya. "Design and Implementation of FSM Based MBIST using March Algorithm." International Journal for Modern Trends in Science and Technology, no. 8 (August 5, 2020): 18–21. http://dx.doi.org/10.46501/ijmtst060804.

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The research article aims at identifying memory testing in static random access memory which is significant in deep sub micron era. Built in self test provides a best solution replacing the external Automatic test equipment. Built in Self Test is a technique of designing additional hardware and software feature into Integrated circuits to allow them to perform testing. BIST works in the background checking memories for faults without interfering with actual functionality of the memory. The objective of the proposed work is to identify faults associated with the memory, perform test algorithms to detect the faults in memory BIST architecture.The implementation of Memory BIST is done using Finite state machine model. The design of memory BIST is accomplished using Xilinx Vivado IDE for 32X8 memory.
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Gopal, P. Bala, and K. Hari Kishore. "An FPGA Implementation of On Chip UART Testing with BIST Techniques." International Journal of Reconfigurable and Embedded Systems (IJRES) 5, no. 3 (November 1, 2016): 176. http://dx.doi.org/10.11591/ijres.v5.i3.pp176-182.

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A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.
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Sharma, Rajiv, and Kewal K. Saluja. "Theory, Analysis and Implementation of an On-Line BIST Technique." VLSI Design 1, no. 1 (January 1, 1993): 9–22. http://dx.doi.org/10.1155/1993/34963.

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A Built-ln Concurrent Self-Test (BICST) technique for testing combinational logic circuits concurrently with their normal operation is proposed. Concept of sharing the test hardware between identical circuits to reduce the overall area overhead is introduced. The method was implemented in the design of an ALU with on-line test capability in CMOS technology. The additional hardware used for a 12-bit ALU was 19% of the total chip area and it did not impose any timing overhead on the operation of the ALU. The overhead decreases with an increase in the size of the ALU.Following the description of the BICST technique, measures for evaluating the performance of the BICST technique are defined. Methods for the computation of the performance measures using analytical and simulation techniques are discussed and results of these methods are reported. Methods for detecting intermittent faults and for computing the transient fault coverage using BICST are also described. The impact of BICST on the system diagnostics and system maintenance is discussed.
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Dissertations / Theses on the topic "Built-In Self Test (BIST) techniques"

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Jervan, Gert. "Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems." Doctoral thesis, Linköping : Dept. of Computer and Information Science, Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2994.

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Allott, Stephen. "The development and implementation of automatic test techniques for Analogue to Digital Converter characterization using a deterministic approach." Thesis, University of Huddersfield, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.385712.

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Liang, Huaguo [Verfasser]. "A New Technique for Deterministic Scan-Based Built-In Self-Test (BIST) / Huaguo Liang." Aachen : Shaker, 2003. http://d-nb.info/1174513713/34.

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Rolindez, Luis. "Technique d’auto test pour des convertisseurs de signal Sigma-Delta." Grenoble INPG, 2007. http://www.theses.fr/2007INPG0020.

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Le test de circuits analogiques et mixtes est de plus en plus coûteux, représentant parfois jusqu’à 50% du coût total de fabrication du circuit. Les techniques de BIST (Built-In Self-Test) permettent de réduire ce coût en intégrant sur la puce les ressources nécessaires au test. Dans cette thèse, nous présentons une nouvelle technique de BIST pour les Convertisseurs Analogiques-Numériques Sigma-Delta (CAN). Cette approche combine un surcoût en surface et un temps de test très réduits. Puisque les circuits numériques sont de plus en plus petits, nous avons choisi une technique principalement numérique, ce qui est en phase avec la philosophie des convertisseurs Sigma-Delta. Comme signal de test nous utilisons un stimulus numérique qui codifie avec une grande précision un signal sinusoïdal. Le même stimulus binaire est employé pour l’analyse de la réponse, effectuée au moyen d’une régression sinusoïdale (sine-wave fitting algorithm). La réutilisation de ressources présentes dans le circuit permet de calculer le SINAD (Signal-to-Noise And Distortion ratio) du convertisseur de manière très efficace. Afin de valider cette technique, un prototype a été conçu et fabriqué dans une technologie CMOS 0. 13 µm de STMicroelectronics. Les résultats expérimentaux confirment la capacité de notre technique à mesurer le SINAD dans un convertisseur audio de 16 bits
The test of analogue and mixed-signal circuits is becoming very costly, sometimes taking up to 50% of the total product cost. Built-In Self-Techniques (BIST) have the potential to reduce these costs, moving most of the test complexity to the design domain and making the circuit auto-testable. In this thesis, we present a new BIST technique for Sigma-Delta Analogue-to-Digital Converters (ADC). This approach exhibits both a very low area overhead and a short test time. Considering the continuous downscaling of digital circuits, we propose a strategy mainly digital, which is in-line with the philosophy of Sigma-Delta converters. As test signal, we generate on-chip a binary stimulus which encodes a very-high precision sinusoidal signal. The same binary stimulus is used for the response analysis, performed on-chip by means of a sine-wave fitting algorithm. The reuse of the resources already present in the circuit allow us to calculate the converter SINAD (SIgnal-to-Noise And Distortion ratio) in a very efficient way. As result of this work, a prototype has been designed and fabricated in a 0. 13 µm CMOS technology from STMicroelectronics. The experimental results confirm the capacity of the BIST technique to measure the SINAD in a 16-bit audio Sigma Delta Converter
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Rehman, Saif Ur. "Développement des techniques de test et de diagnostic pour les FPGA hiérarchique de type mesh." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT110/document.

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L’évolution tendant à réduire la taille et augmenter la complexité des circuits électroniques modernes, est en train de ralentir du fait des limitations technologiques, qui génèrent beaucoup de d’imperfections et de defaults durant la fabrication ou la durée de vie de la puce. Les FPGAs sont utilisés dans les systèmes numériques complexes, essentiellement parce qu’ils sont reconfigurables et rapide à commercialiser. Pour garder une grande fiabilité de tels systèmes, les FPGAs doivent être testés minutieusement pour les defaults. L’optimisation de l’architecture des FPGAs pour l’économie de surface et une meilleure routabilité est un processus continue qui impacte directement la testabilité globale et de ce fait, la fiabilité. Cette thèse présente une stratégie complète pour le test et le diagnostique des defaults de fabrication des “mesh-based FPGA” contenant une nouvelle topologie d’interconnections à plusieurs niveaux, ce qui promet d’apporter une meilleure routabilité. Efficacité des schémas proposes est analysée en termes de temps de test, couverture de faute et résolution de diagnostique
The evolution trend of shrinking feature size and increasing complexity in modern electronics is being slowed down due to physical limits that generate numerous imperfections and defects during fabrication steps or projected life time of the chip. Field Programmable Gate Arrays (FPGAs) are used in complex digital systems mainly due to their reconfigurability and shorter time-to-market. To maintain a high reliability of such systems, FPGAs should be tested thoroughly for defects. FPGA architecture optimization for area saving and better signal routability is an ongoing process which directly impacts the overall FPGA testability, hence the reliability. This thesis presents a complete strategy for test and diagnosis of manufacturing defects in mesh-based FPGAs containing a novel multilevel interconnects topology which promises to provide better area and routability. Efficiency of the proposed test schemes is analyzed in terms of test cost, respective fault coverage and diagnostic resolution
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Akour, Amneh M. "Design Techniques for Manufacturable 60GHz CMOS LNAs." The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1306443049.

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Dubois, Matthieu. "Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00633056.

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L'expansion du marché des semi-conducteurs dans tous les secteurs d'activité résulte de la capacité de créer de nouvelles applications grâce à l'intégration de plus en plus de fonctionnalités sur une surface de plus en plus faible. Pour chaque entreprise, la compétitivité dépend du coût de fabrication mais aussi de la fiabilité du produit. Ainsi, la phase de test d'un circuit intégré, et plus particulièrement des circuits analogiques et mixtes, est le facteur prédominant dans les choix d'un compromis entre ces deux critères antagonistes, car son coût est désormais proche du coût de production. Cette tendance contraint les acteurs du marché à mettre en place de nouvelles solutions moins onéreuses. Parmi les recherches dans ce domaine, la conception en vue du test (DfT) consiste à intégrer pendant le développement de la puce, une circuiterie additionnelle susceptible d'en faciliter le test, voire d'effectuer un auto-test (BIST). Mais la sélection d'une de ces techniques nécessite une évaluation de leur capacité de différencier les circuits fonctionnels des circuits défaillants. Ces travaux de recherche introduisent une méthodologie d'estimation de la qualité d'une DfT ou d'un BIST dans le flot de conception de circuits analogiques et mixtes. Basée sur la génération d'un large échantillon prenant en compte l'impact des variations d'un procédé technologique sur les performances et les mesures de test du circuit, cette méthodologie calcule les métriques de test exprimant la capacité de chaque technique de détecter les circuits défaillants sans rejeter des circuits fonctionnels et d'accepter les circuits fonctionnels en rejetant les circuits défaillant. Ensuite, le fonctionnement d'un auto-test numérique adapté aux convertisseurs sigma-delta est présenté ainsi qu'une nouvelle méthode de génération et d'injection du stimulus de test. La qualité de ces techniques d'auto-test est démontrée en utilisant la méthodologie d'estimation des métriques de test. Enfin, un démonstrateur développé sur un circuit programmable démontre la possibilité d'employer une technique d'auto-test dans un système de calibrage intégré.
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Olbrich, Thomas. "Design-for-Test and Built-In-Self-Test for integrated systems." Thesis, Lancaster University, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.312594.

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Cilici, Florent. "Développement de solutions BIST (Built-In Self-Test) pour circuits intégrés radiofréquences/millimétriques." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT072.

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Les technologies silicium récentes sont particulièrement prônes aux imperfections durant la fabrication des circuits. La variation des procédés peut entrainer une dégradation des performances, notamment aux hautes fréquences. Dans cette thèse, plusieurs contributions visant la réduction des coûts et de la complexité du test des circuits millimétriques sont présentées. Dans ce sens, deux sujets principaux ont fait l'objet de notre attention : a) le test indirect non-intrusif basé sur l’apprentissage automatique et b) la calibration non-itérative "one-shot". Nous avons en particulier développé une méthode générique pour implémenter un test indirect non-intrusif basé sur l’apprentissage automatique. La méthode vise à être aussi automatisée que possible de façon à pouvoir être appliquée à pratiquement n'importe quel circuit millimétrique. Elle exploite les modèles Monte Carlo du design kit et des informations de variations du BEOL pour proposer un jeu de capteurs non-intrusifs. Des mesures à basses fréquences permettent ensuite d'extraire des signatures qui contiennent des données pertinentes concernant la qualité des procédés de fabrication, et donc a fortiori de la performance du circuit. Cette méthode est supportée par des résultats expérimentaux sur des PAs fonctionnant à 65 GHz, conçus dans une technologie 55 nm de STMicroelectronics. Pour s'attaquer plus encore à la dégradation des performances induite par les variations des procédés de fabrication, nous nous sommes également penchés sur une procédure de calibration non-itérative. Nous avons ainsi présenté un PA à deux étages qui peut être calibré en post-fabrication. La méthode de calibration exploite une cellule de découplage variable comme moyen de modifier les performances de l'amplificateur. Des moniteurs de variations des procédés de fabrication, placés dans les espaces vides du circuit, sont utilisés afin de prédire la meilleure configuration possible pour les cellules de découplage variables. La faisabilité et les performances de cette approche ont été validés en simulation
Recent silicon technologies are especially prone to imperfections during the fabrication of the circuits. Process variations can induce a noticeable performance shift, especially for high frequency devices. In this thesis we present several contributions to tackle the cost and complexity associated with testing mm-wave ICs. In this sense, we have focused on two main topics: a) non-intrusive machine learning indirect test and b) one-shot calibration. We have in particular developed a generic method to implement a non-intrusive machine learning indirect test based on process variation sensors. The method is aimed at being as automated as possible and can be applied to virtually any mm-wave circuit. It leverages the Monte Carlo models of the design kit and the BEOL variability information to propose a set of non-intrusive sensors. Low frequency measurements can be performed on these sensors to extract signatures that provide relevant information about the process quality, and consequently about the device performance. The method is supported by experimental results in a set of 65 GHz PAs designed in a 55 nm technology from STMicroelectronics. To further tackle the performance degradation induced by process variations, we have also focused on the implementation of a one-shot calibration procedure. In this line, we have presented a two-stage 60 GHz PA with one-shot calibration capability. The proposed calibration takes advantage of a novel tuning knob, implemented as a variable decoupling cell. Non-intrusive process monitors, placed within the empty spaces of the circuit, are used for predicting the best tuning knob configuration based on a machine learning regression model. The feasibility and performance of the proposed calibration strategy have been validated in simulation
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XIONG, XINGGUO. "BUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1123038236.

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Books on the topic "Built-In Self Test (BIST) techniques"

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Jervan, Gert. Hybrid built-in self-test and test generation techniques for digital systems. Linko ping: Dept. of Computer and Information Science, Univ., 2005.

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Jervan, Gert. High-level test generation and built-in self-test techniques for digital systems. Linköping: Department of Computer and Information Science, Linköpings universitet, 2002.

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Roberts, Gordon W. Analog signal generation for built-in-self-test of mixed-signal integrated circuits. Boston: Kluwer Academic Publishers, 1995.

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Book chapters on the topic "Built-In Self Test (BIST) techniques"

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Noia, Brandon, and Krishnendu Chakrabarty. "Built-In Self-Test for TSVs." In Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs, 55–79. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-02378-6_3.

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Li, Jin-Fu, Ruey-Shing Tzeng, Cheng-Wen Wu, and Krishnendu Chakrabarty. "Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test." In SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, 151–63. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-1-4757-6527-4_10.

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Gupta, Ravi, and Kriti Suneja. "Comparison of Logic Built-in-Self Test Techniques Based on FPGA in Verilog." In Lecture Notes in Electrical Engineering, 309–15. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7395-3_35.

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Tripathi, Suman Lata. "Design for Testability of High-Speed Advance Multipliers." In AI Techniques for Reliability Prediction for Electronic Components, 175–90. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1464-1.ch010.

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An efficient design for testability (DFT) has been a major thrust of area for today's VLSI engineers. A poorly designed DFT would result in losses for manufacturers with a considerable rework for the designers. BIST (built-in self-test), one of the promising DFT techniques, is rapidly modifying with the advances in technology as the device shrinks. The increasing complexities of the hardware have shifted the trend to include BISTs in high performance circuitry for offline as well as online testing. Work done here involves testing a circuit under test (CUT) with built in response analyser and vector generator with a monitor to control all the activities.
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Wang, Francis C. "Built-In Self Test and Boundary Scan Techniques." In Digital Circuit Testing, 146–90. Elsevier, 1991. http://dx.doi.org/10.1016/b978-0-08-050434-6.50008-0.

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Dhanunjay, Nalla, and Alok Barua. "An oscillation-based built-in self-test (BIST) system for dynamic performance parameter evaluation of an 8 bit, 100 MSPS pipelined ADC." In Pipelined Analog to Digital Converter and Fault Diagnosis, 4–1. IOP Publishing, 2020. http://dx.doi.org/10.1088/978-0-7503-1732-0ch4.

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"which a social group or individual thinks is wrong. So the first port of call will be the courts, where we should be able to expect an independent judiciary. However, it is also true that sometimes actions and decisions are taken which, although in themselves not contentious, accumulate along with other legislation to create a highly questionable situation. Note here that the situation becomes questionable: an interpretation of the rules becomes possible which some would simply not agree with. For example, progressive attitudes towards free speech has resulted in the situation being taken advantage of by extreme groups for political ends. There are a number of very specific points which can be made about the use of DNA by society and more especially the construction and use of DNA databases. It is unlikely that anybody would really object to construction of anonymous databases so that we can produce a precise and reliable figure for the probability of finding a DNA profile in the general population by chance alone. What many people do have objections to is the construction of databases of named individuals. Strangely, it would seem that the country that has always been in the van of development of DNA technology is developing a rather poorer reputation for riding roughshod over the rights of its population, the UK. The problems and objections with databases of named individuals start with the practitioners and political will by successive governments. Luckily, there is an outspoken reaction to the UK government’s belief that all uses of DNA are good, but we should be aware that this is not so. Current thinking is that in the future it will be possible to determine facial shape, such as nose type and eye colour, with a simple test. This is put forward as a distinct possibility by the Forensic Science Service, with little regard to the extreme complexity of both the genetics and the environmental input into such things, not to mention plastic surgery. While it was always the belief that rapid turnaround of DNA results would be a good thing, this is only if the techniques are highly controlled. The idea that a hand held machine, as has been suggested, could be taken to a scene of crime and the DNA analysed in situ should fill any self-respecting scientist with horror. It has already been stated that there is a 40% chance of a stain found at a crime scene being linked to a name on the database of named individuals. As databases become larger as well as the number of individuals putting data on the database, so the likelihood of error increases; remember that error in this sense is quite likely to ruin a life. Names get onto databases for perfectly innocent reasons. Two of these are the husband or partner of a rape victim and, which is even more demeaning, the DNA profile of the victim herself. This was admitted in the House of Lords. So why is the British public so lacking in interest or apparently not in the least bit bothered by this staggering lack of feeling for the innocent? There is no mechanism for the removal of a DNA sample from the database after consent has been given. It is of interest here that both the police, forensic scientists and politicians are extremely reluctant to give a sample which can be held on the named database. Why is this? Fear? Fear of what may be done with such intimate information. This includes medical analysis and data which they have no right to access. It would be." In Genetics and DNA Technology: Legal Aspects, 109. Routledge-Cavendish, 2013. http://dx.doi.org/10.4324/9781843146995-17.

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Conference papers on the topic "Built-In Self Test (BIST) techniques"

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Shyue-Kung Lu and Shih-Chang Huang. "Built-in self-test and repair (BISTR) techniques for embedded RAMs." In Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004. IEEE, 2004. http://dx.doi.org/10.1109/mtdt.2004.1327985.

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Dutta, Amit, Malav Shah, G. Swathi, and Rubin A. Parekhji. "Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test." In 2009 15th IEEE International On-Line Testing Symposium (IOLTS 2009). IEEE, 2009. http://dx.doi.org/10.1109/iolts.2009.5196022.

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Kim, KeonIl, Yoseop Lim, GhilGeun Oh, ShinYoung Chung, and Brandon Lee. "Failure Analysis of SRAM DQ Fault Using BIST Pattern." In ISTFA 2018. ASM International, 2018. http://dx.doi.org/10.31399/asm.cp.istfa2018p0474.

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Abstract SRAM failure analysis (FA) provides significant value to process improvement and yield enhancement. This paper introduces an innovative method to analyze the SRAM peripheral, particularly its input/output (DQ) failures, which is not easy to isolate the fault location. In this paper, SRAM Built-In Self-Test (BIST) logic is used to generate the vectors to toggle only DQ of SRAM and an optical fault isolation technique applies to isolate the fault location. Experimental results show that the proposed method is very effective to isolate timing fault and hard defect of SRAM DQ failures.
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Kennen, Alan, John F. Guravage, Lauren Foster, and John Kornblum. "Investigation of High Frequency Failures on a 0.35μm CMOS IC." In ISTFA 1999. ASM International, 1999. http://dx.doi.org/10.31399/asm.cp.istfa1999p0359.

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Abstract Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.
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A'ain, Abu Khari bin, Muhamad Ridzuan bin Radin Muhamad Amin, and Mahmud Adnan. "Hybrid built-in self test (BIST) for sequential circuits." In 2009 Conference on Innovative Technologies in Intelligent Systems and Industrial Applications (CITISIA). IEEE, 2009. http://dx.doi.org/10.1109/citisia.2009.5224205.

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Lall, Pradeep, Prashant Gupta, Arjun Angral, and Jeff Suhling. "Feature Vector Based Failure Mode Identification and Prognostication of Electronics Subjected to Shock and Vibration." In ASME 2009 International Mechanical Engineering Congress and Exposition. ASMEDC, 2009. http://dx.doi.org/10.1115/imece2009-12495.

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Failures in electronics subjected to shock and vibration are typically diagnosed using the built-in self test (BIST) or using continuity monitoring of daisy-chained packages. The BIST which is extensively used for diagnostics or identification of failure, is focused on reactive failure detection and provides limited insight into reliability and residual life. In this paper, a new technique has been developed for health monitoring and failure mode classification based on measured damage precursors. A feature extraction technique in the joint-time frequency domain has been developed along with pattern classifiers for fault diagnosis of electronics at product-level. The Karhunen Loe´ve transform (KLT) has been used for feature reduction and de-correlation of the feature vectors for fault mode classification in electronic assemblies. Euclidean, and Mahalanobis, and Bayesian distance classifiers based on joint-time frequency analysis, have been used for classification of the resulting feature space. Previously, the authors have developed damage pre-cursors based on time and spectral techniques for health monitoring of electronics without reliance on continuity data from daisy-chained packages. Statistical Pattern Recognition techniques based on wavelet packet energy decomposition [Lall 2006a] have been studied by authors for quantification of shock damage in electronic assemblies, and auto-regressive moving average, and time-frequency techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in electronic systems [Lall 2008]. However, identification of specific failure modes was not possible. In this paper, various fault modes such as solder inter-connect failure, inter-connect missing, chip delamination chip cracking etc in various packaging architectures have been classified using clustering of feature vectors based on the KLT approach [Goumas 2002]. The KLT de-correlates the feature space and identifies dominant directions to describe the space, eliminating directions that encode little useful information about the features [Qian 1996, Schalkoff 1972, Theodoridis 1998, Tou 1974]. The clustered damage pre-cursors have been correlated with underlying damage. Several chip-scale packages have been studied, with leadfree second-level interconnects including SAC105, SAC305 alloys. Transient strain has been measured during the drop-event using digital image correlation and high-speed cameras operating at 100,000 fps. Continuity has been monitored simultaneously for failure identification. Fault-mode classification has been done using KLT and joint-time-frequency analysis of the experimental data. In addition, explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, trace fracture, package falloff and solder ball failure. Models using cohesive elements present at the solder joint-copper pad interface at both the PCB and package side have also been created to study the traction-separation behavior of solder. Fault modes predicted by simulation based pre-cursors have been correlated with those from experimental data.
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Lall, Pradeep, Prashant Gupta, Arjun Angral, and Jeff Suhling. "Anomaly-Detection and Prognostication of Electronics Subjected to Shock and Vibration." In ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability. ASMEDC, 2009. http://dx.doi.org/10.1115/interpack2009-89298.

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Abstract:
Failures in electronics subjected to shock and vibration are typically diagnosed using the built-in self test (BIST) or using continuity monitoring of daisy-chained packages. The BIST which is extensively used for diagnostics or identification of failure, is focused on reactive failure detection and provides limited insight into reliability and residual life. In this paper, a new technique has been developed for health monitoring and failure mode classification based on measured damage precursors. A feature extraction technique in the joint-time frequency domain has been developed along with pattern classifiers for fault diagnosis of electronics at product-level. The Karhunen Loe´ve transform (KLT) has been used for feature reduction and de-correlation of the feature vectors for fault mode classification in electronic assemblies. Euclidean, and Mahalanobis, and Bayesian distance classifiers based on joint-time frequency analysis, have been used for classification of the resulting feature space. Previously, the authors have developed damage pre-cursors based on time and spectral techniques for health monitoring of electronics without reliance on continuity data from daisy-chained packages. Statistical Pattern Recognition techniques based on wavelet packet energy decomposition [Lall 2006a] have been studied by authors for quantification of shock damage in electronic assemblies, and auto-regressive moving average, and time-frequency techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in electronic systems [Lall 2008]. However, identification of specific failure modes was not possible. In this paper, various fault modes such as solder inter-connect failure, inter-connect missing, chip delamination chip cracking etc in various packaging architectures have been classified using clustering of feature vectors based on the KLT approach [Goumas 2002]. The KLT de-correlates the feature space and identifies dominant directions to describe the space, eliminating directions that encode little useful information about the features [Qian 1996, Schalkoff 1972, Theodoridis 1998, Tou 1974]. The clustered damage pre-cursors have been correlated with underlying damage. Several chip-scale packages have been studied, with leadfree second-level interconnects including SAC105, SAC305 alloys. Transient strain has been measured during the drop-event using digital image correlation and high-speed cameras operating at 100,000 fps. Continuity has been monitored simultaneously for failure identification. Fault-mode classification has been done using KLT and joint-time-frequency analysis of the experimental data. In addition, explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, trace fracture, package falloff and solder ball failure. Models using cohesive elements present at the solder joint-copper pad interface at both the PCB and package side have also been created to study the traction-separation behavior of solder. Fault modes predicted by simulation based pre-cursors have been correlated with those from experimental data.
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Sengar, Jitendra Singh, Sudipta Ghosh, S. Raj Shekhar, Praveen Verma, and Rajat Sharma. "Contriving of a novel BIST (built in self-test) digital combinational lock." In 2013 Fourth International Conference on Computing, Communications and Networking Technologies (ICCCNT). IEEE, 2013. http://dx.doi.org/10.1109/icccnt.2013.6726738.

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Conroy, Zoe, Hui Li, and Jun Balangue. "Built In Self Test (BIST) Survey - an industry snapshot of HVM component BIST usage at board and system test." In 2010 34th International Electronics Manufacturing Technology Conference (IEMT). IEEE, 2010. http://dx.doi.org/10.1109/iemt.2010.5746723.

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Liu, C. Y., K. K. Saluja, and J. S. Upadhyaya. "BIST-PLA: a built-in self-test design of large programmable logic arrays." In 24th ACM/IEEE conference proceedings. New York, New York, USA: ACM Press, 1987. http://dx.doi.org/10.1145/37888.37946.

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