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Jervan, Gert. "Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems." Doctoral thesis, Linköping : Dept. of Computer and Information Science, Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2994.
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Allott, Stephen. "The development and implementation of automatic test techniques for Analogue to Digital Converter characterization using a deterministic approach." Thesis, University of Huddersfield, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.385712.
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Liang, Huaguo [Verfasser]. "A New Technique for Deterministic Scan-Based Built-In Self-Test (BIST) / Huaguo Liang." Aachen : Shaker, 2003. http://d-nb.info/1174513713/34.
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Rolindez, Luis. "Technique d’auto test pour des convertisseurs de signal Sigma-Delta." Grenoble INPG, 2007. http://www.theses.fr/2007INPG0020.
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Le test de circuits analogiques et mixtes est de plus en plus coûteux, représentant parfois jusqu’à 50% du coût total de fabrication du circuit. Les techniques de BIST (Built-In Self-Test) permettent de réduire ce coût en intégrant sur la puce les ressources nécessaires au test. Dans cette thèse, nous présentons une nouvelle technique de BIST pour les Convertisseurs Analogiques-Numériques Sigma-Delta (CAN). Cette approche combine un surcoût en surface et un temps de test très réduits. Puisque les circuits numériques sont de plus en plus petits, nous avons choisi une technique principalement numérique, ce qui est en phase avec la philosophie des convertisseurs Sigma-Delta. Comme signal de test nous utilisons un stimulus numérique qui codifie avec une grande précision un signal sinusoïdal. Le même stimulus binaire est employé pour l’analyse de la réponse, effectuée au moyen d’une régression sinusoïdale (sine-wave fitting algorithm). La réutilisation de ressources présentes dans le circuit permet de calculer le SINAD (Signal-to-Noise And Distortion ratio) du convertisseur de manière très efficace. Afin de valider cette technique, un prototype a été conçu et fabriqué dans une technologie CMOS 0. 13 µm de STMicroelectronics. Les résultats expérimentaux confirment la capacité de notre technique à mesurer le SINAD dans un convertisseur audio de 16 bitsThe test of analogue and mixed-signal circuits is becoming very costly, sometimes taking up to 50% of the total product cost. Built-In Self-Techniques (BIST) have the potential to reduce these costs, moving most of the test complexity to the design domain and making the circuit auto-testable. In this thesis, we present a new BIST technique for Sigma-Delta Analogue-to-Digital Converters (ADC). This approach exhibits both a very low area overhead and a short test time. Considering the continuous downscaling of digital circuits, we propose a strategy mainly digital, which is in-line with the philosophy of Sigma-Delta converters. As test signal, we generate on-chip a binary stimulus which encodes a very-high precision sinusoidal signal. The same binary stimulus is used for the response analysis, performed on-chip by means of a sine-wave fitting algorithm. The reuse of the resources already present in the circuit allow us to calculate the converter SINAD (SIgnal-to-Noise And Distortion ratio) in a very efficient way. As result of this work, a prototype has been designed and fabricated in a 0. 13 µm CMOS technology from STMicroelectronics. The experimental results confirm the capacity of the BIST technique to measure the SINAD in a 16-bit audio Sigma Delta Converter
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Rehman, Saif Ur. "Développement des techniques de test et de diagnostic pour les FPGA hiérarchique de type mesh." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT110/document.
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L’évolution tendant à réduire la taille et augmenter la complexité des circuits électroniques modernes, est en train de ralentir du fait des limitations technologiques, qui génèrent beaucoup de d’imperfections et de defaults durant la fabrication ou la durée de vie de la puce. Les FPGAs sont utilisés dans les systèmes numériques complexes, essentiellement parce qu’ils sont reconfigurables et rapide à commercialiser. Pour garder une grande fiabilité de tels systèmes, les FPGAs doivent être testés minutieusement pour les defaults. L’optimisation de l’architecture des FPGAs pour l’économie de surface et une meilleure routabilité est un processus continue qui impacte directement la testabilité globale et de ce fait, la fiabilité. Cette thèse présente une stratégie complète pour le test et le diagnostique des defaults de fabrication des “mesh-based FPGA” contenant une nouvelle topologie d’interconnections à plusieurs niveaux, ce qui promet d’apporter une meilleure routabilité. Efficacité des schémas proposes est analysée en termes de temps de test, couverture de faute et résolution de diagnostiqueThe evolution trend of shrinking feature size and increasing complexity in modern electronics is being slowed down due to physical limits that generate numerous imperfections and defects during fabrication steps or projected life time of the chip. Field Programmable Gate Arrays (FPGAs) are used in complex digital systems mainly due to their reconfigurability and shorter time-to-market. To maintain a high reliability of such systems, FPGAs should be tested thoroughly for defects. FPGA architecture optimization for area saving and better signal routability is an ongoing process which directly impacts the overall FPGA testability, hence the reliability. This thesis presents a complete strategy for test and diagnosis of manufacturing defects in mesh-based FPGAs containing a novel multilevel interconnects topology which promises to provide better area and routability. Efficiency of the proposed test schemes is analyzed in terms of test cost, respective fault coverage and diagnostic resolution
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Akour, Amneh M. "Design Techniques for Manufacturable 60GHz CMOS LNAs." The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1306443049.
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Dubois, Matthieu. "Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00633056.
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L'expansion du marché des semi-conducteurs dans tous les secteurs d'activité résulte de la capacité de créer de nouvelles applications grâce à l'intégration de plus en plus de fonctionnalités sur une surface de plus en plus faible. Pour chaque entreprise, la compétitivité dépend du coût de fabrication mais aussi de la fiabilité du produit. Ainsi, la phase de test d'un circuit intégré, et plus particulièrement des circuits analogiques et mixtes, est le facteur prédominant dans les choix d'un compromis entre ces deux critères antagonistes, car son coût est désormais proche du coût de production. Cette tendance contraint les acteurs du marché à mettre en place de nouvelles solutions moins onéreuses. Parmi les recherches dans ce domaine, la conception en vue du test (DfT) consiste à intégrer pendant le développement de la puce, une circuiterie additionnelle susceptible d'en faciliter le test, voire d'effectuer un auto-test (BIST). Mais la sélection d'une de ces techniques nécessite une évaluation de leur capacité de différencier les circuits fonctionnels des circuits défaillants. Ces travaux de recherche introduisent une méthodologie d'estimation de la qualité d'une DfT ou d'un BIST dans le flot de conception de circuits analogiques et mixtes. Basée sur la génération d'un large échantillon prenant en compte l'impact des variations d'un procédé technologique sur les performances et les mesures de test du circuit, cette méthodologie calcule les métriques de test exprimant la capacité de chaque technique de détecter les circuits défaillants sans rejeter des circuits fonctionnels et d'accepter les circuits fonctionnels en rejetant les circuits défaillant. Ensuite, le fonctionnement d'un auto-test numérique adapté aux convertisseurs sigma-delta est présenté ainsi qu'une nouvelle méthode de génération et d'injection du stimulus de test. La qualité de ces techniques d'auto-test est démontrée en utilisant la méthodologie d'estimation des métriques de test. Enfin, un démonstrateur développé sur un circuit programmable démontre la possibilité d'employer une technique d'auto-test dans un système de calibrage intégré.
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Olbrich, Thomas. "Design-for-Test and Built-In-Self-Test for integrated systems." Thesis, Lancaster University, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.312594.
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Cilici, Florent. "Développement de solutions BIST (Built-In Self-Test) pour circuits intégrés radiofréquences/millimétriques." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT072.
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Les technologies silicium récentes sont particulièrement prônes aux imperfections durant la fabrication des circuits. La variation des procédés peut entrainer une dégradation des performances, notamment aux hautes fréquences. Dans cette thèse, plusieurs contributions visant la réduction des coûts et de la complexité du test des circuits millimétriques sont présentées. Dans ce sens, deux sujets principaux ont fait l'objet de notre attention : a) le test indirect non-intrusif basé sur l’apprentissage automatique et b) la calibration non-itérative "one-shot". Nous avons en particulier développé une méthode générique pour implémenter un test indirect non-intrusif basé sur l’apprentissage automatique. La méthode vise à être aussi automatisée que possible de façon à pouvoir être appliquée à pratiquement n'importe quel circuit millimétrique. Elle exploite les modèles Monte Carlo du design kit et des informations de variations du BEOL pour proposer un jeu de capteurs non-intrusifs. Des mesures à basses fréquences permettent ensuite d'extraire des signatures qui contiennent des données pertinentes concernant la qualité des procédés de fabrication, et donc a fortiori de la performance du circuit. Cette méthode est supportée par des résultats expérimentaux sur des PAs fonctionnant à 65 GHz, conçus dans une technologie 55 nm de STMicroelectronics. Pour s'attaquer plus encore à la dégradation des performances induite par les variations des procédés de fabrication, nous nous sommes également penchés sur une procédure de calibration non-itérative. Nous avons ainsi présenté un PA à deux étages qui peut être calibré en post-fabrication. La méthode de calibration exploite une cellule de découplage variable comme moyen de modifier les performances de l'amplificateur. Des moniteurs de variations des procédés de fabrication, placés dans les espaces vides du circuit, sont utilisés afin de prédire la meilleure configuration possible pour les cellules de découplage variables. La faisabilité et les performances de cette approche ont été validés en simulationRecent silicon technologies are especially prone to imperfections during the fabrication of the circuits. Process variations can induce a noticeable performance shift, especially for high frequency devices. In this thesis we present several contributions to tackle the cost and complexity associated with testing mm-wave ICs. In this sense, we have focused on two main topics: a) non-intrusive machine learning indirect test and b) one-shot calibration. We have in particular developed a generic method to implement a non-intrusive machine learning indirect test based on process variation sensors. The method is aimed at being as automated as possible and can be applied to virtually any mm-wave circuit. It leverages the Monte Carlo models of the design kit and the BEOL variability information to propose a set of non-intrusive sensors. Low frequency measurements can be performed on these sensors to extract signatures that provide relevant information about the process quality, and consequently about the device performance. The method is supported by experimental results in a set of 65 GHz PAs designed in a 55 nm technology from STMicroelectronics. To further tackle the performance degradation induced by process variations, we have also focused on the implementation of a one-shot calibration procedure. In this line, we have presented a two-stage 60 GHz PA with one-shot calibration capability. The proposed calibration takes advantage of a novel tuning knob, implemented as a variable decoupling cell. Non-intrusive process monitors, placed within the empty spaces of the circuit, are used for predicting the best tuning knob configuration based on a machine learning regression model. The feasibility and performance of the proposed calibration strategy have been validated in simulation
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XIONG, XINGGUO. "BUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1123038236.
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Testa, Luca. "Contribution to the Built-In Self-Test for RF VCOs." Thesis, Bordeaux 1, 2010. http://www.theses.fr/2010BOR14011/document.
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Ce travail concerne l'étude et la réalisation de stratégies d'auto-test intégrées pour VCO radiofréquence (RF). La complexité des circuits intégrés RF devient un obstacle pour la mesure des principaux blocs RF des chaines de transmission/réception. Certains nœuds ne sont pas accessibles, l'excursion en tension des signaux baisse et les signaux haute fréquence ne peuvent pas être amenés à l'extérieur de la puce sans une forte dégradation. Le s techniques habituelles de test deviennent très couteuses et lentes. Le test pour le wafer-sort est étudié en premier. La solution proposée est la mise en œuvre d'une stratégie d'auto-test intégrée (BIST) qui puisse discriminer entre circuits sans fautes et circuits avec fautes pendant le wafer-test. La méthodologie utilisée est le test structurel. La couverture des fautes est étudiée pour connaitre la quantité à capter au niveau intégré afin de maximiser la probabilité de trouver tous les défauts physiques dans le VCO. Le résultat de cette analyse montre que la couverture des fautes est maximisée quand la tension crête-crête en sortie du VCO est captée. La caractérisation complète (validation de la puce et process-monitoring) du VCO est étudiée dans la deuxième étape. Les informations à extraire de la puce sont: amplitude des signaux, consommation du VCO, fréquence d'oscillation, gain de conversion (Kvco) et une information à propos du bruit de phase. Un démonstrateur pour le test au niveau wafer est réalisé en technologie ST CMOS 65nm. Le démonstrateur est composé d'un VCO 3.5GHz (le circuit sous test), un LDO, une référence de tension indépendante de température et variations d'alimentation, un capteur de tension crête-crête et un comparateur. Le capteur Vpp donne en sortie une information DC qui est comparée avec une plage de valeurs acceptables. Le BIST donne en sortie une information numérique pass/failThis work deals with the study and the realization of Built-In Self-Tests (BIST) for RF VCOs (Voltage Controlled Oscillators) The increasing complexity of RF integrated circuits is creating an obstacle for the correct measurement of the main RF blocks of any transceiver. Some nodes are not accessible, the voltage excursion of the signals is getting lower and lower and high frequency signals cannot be driven off the die without a main degradation. The common test techniques become then very expensive and time consuming. The wafer sort is firstly approached. The proposed solution is the implementation of a BIST strategy able to discriminate between faulty and good circuits during the wafer test. The chosen methodology is the structural test (fault-oriented). A fault coverage campaign is carried out in order to find the quantity to monitor on-chip that maximizes the probability to find all possible physical defects in the VCO. The result of the analysis reveals that the fault coverage is maximized if the peak-to-peak output voltage is monitored. The complete on-chip characterization of the VCO is then addressed, for chip validation and process monitoring. The information that need to be extracted on-chip concern: amplitude of the signal, consumption of the VCO, frequency of oscillation, its conversion gain (voltage-to-frequency) and eventually some information on the phase noise. A silicon demonstrator for wafer sort purposes is implemented using the ST CMOS 65nm process. It includes a 3.5GHz VCO, an LDO, a temperature and supply-voltage independent voltage reference, a peak-to-peak voltage detector and a comparator. The Vpp detector outputs a DC-voltage that is compared to a predefined acceptance boundary. A logic pass/fail signal is output by the BIST. The attention is then turned to the study of the proposed architecture for an on-chip frequency-meter able to measure the RF frequency with high accuracy. Behavioral simulations using VHDL-AMS lead to the conclusion that a TDC (Time-to-Digital Converter) is the best solution for our goal. The road is then opened to the measure of long-time jitter making use of the same TDC
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Bou, Sleiman Sleiman. "Built-in-Self-Test and Digital Self-Calibration for Radio Frequency Integrated Circuits." The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1311685013.
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Venkatasubramanian, Radhika. "High frequency continuous-time circuits and built-in-self-test using CMOS RMS detector." Texas A&M University, 2005. http://hdl.handle.net/1969.1/4746.
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The expanding wireless market has resulted in complex integrated transceivers
that involve RF, analog and mixed-signal circuits, resulting in expensive and complicated
testing. The most important challenges that test engineering faces today are (1) providing
a fast and accurate fault-diagnosis and performance characterization so as to accelerate
the time-to-market and (2) providing an inexpensive test strategy that can be integrated
with the design so as to aid the high-volume manufacturing process. The first part of the
research focuses on the design of an RMS detector for built-in-self-test (BIST) of an RF
integrated transceiver that can directly provide information at various test points in the
design. A cascode low noise amplifier (LNA) has been chosen as the device under test
(DUT). A compact (< 0.031 mm2) RF RMS detector with negligible input capacitance (<
13 fF) has been implemented in 0.35 õm CMOS technology along with the DUT.
Experimental results are currently being assimilated and compared with the simulation
results. Frequency limitations were encountered during the testing process due to
unexpected increase in the value of the N-well resistors. All other problems faced during
the testing, as well as the results obtained so far, are presented in this thesis. In the second part of the research, the use of the RMS detector for BIST has been
extended to a continuous-time high-frequency boost-filter. The proposed HF RMS
detector has been implemented along with a 24 dB 350 MHz boost filter as the DUT on
0.35 õm CMOS technology. The HF RMS detector occupies 0.07 mm2 and has an input
capacitance of 7 fF. The HF RMS detector has a dynamic range greater than 24 dB
starting from -38 dBm of input power. The bandwidth and boost of the filter have been
accurately estimated in simulation using the HF RMS detector. The sensitivity of an
intermediate band pass node of the filter has also been monitored to predict the filter's
sensitivity to Q errors.
The final part of the research describes the design of a single-ended to differential
converter for use in a broadband transceiver operating from 50-850 MHz. This circuit is
used as the second stage in the transceiver after the LNA. The design has been simulated
on a 0.35 um CMOS process and has a power consumption of 13.5 mW and less than 8
dB of noise figure over the entire band. It is capable of driving a 500fF load with less
than 1dB of gain ripple over the entire band (50-850 MHz).
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Poling, Brian. "On-Chip Signal Generation and Response Waveform Extraction for Analog Built-In-Self-Test." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1190050023.
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Dogaru, Emanuel. "Built-In Self-Test of Flexible RF Transmitters Using Nonuniform Undersampling." Thesis, CentraleSupélec, 2015. http://www.theses.fr/2015SUPL0004/document.
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Le secteur de communications sécurisés et portables connait une véritable révolution avec l’apparition des plateformes dites radios logiciels (Software Defined Radios, SDRs). Les performances exceptionnelles de ces systèmes sont les résultats d’une interaction assez complexe et souvent peu évidente entre le logiciel embarqué, le circuit de traitement numérique et les blocs mixtes analogiques/RF. Cette complexité limite la testabilité du produit fini. La méthodologie de test utilisée actuellement a atteint ses limites dues au cout élevé, le long temps de test et le bas degré de généralisation. De plus, les plateformes SDRs peuvent évoluer sur le terrain et elles vont supporter des standards et des scénarios qui n’ont pas été considérés pendant le la phase de conception. Donc, une stratégie de test sur le terrain (en ligne) n’est plus une caractéristique optionnelle mais une nécessité. Dans ce contexte, le but de notre recherche est d’inventer et développer une méthodologie de test capable de garantir le bon fonctionnement d’une plateforme SDR après la production et pendant sa vie. Notre objectif final est de réduire le coût du test en profitant de la reconfigurabilité de la plateforme. Pour les radios tactiques qui doivent être mises à jour sur le terrain sans équipement spécial, les stratégies Built-In Self-Test (BIST) sont, sans doute, la seule moyenne de garantir la conformité aux spécifications. Dans cette mémoire, nous introduisons une nouvelle architecture de test RF BIST qui utilise la technique de de sous-échantillonnage nonuniform à la sortie de l’émetteur (TX) d’une SDR afin d’évaluer la conformité de la masque spectrale. Notre solution s’appuie sur une implémentation autonome, est modulable et peut être appliquée pour le test sur le terrain avec des modifications minimes. Par rapport aux autres techniques de test analogiques/RF, cet approche ne dépends pas de la architecture du TX, ni d’un modèle ad-hoc, ce qui est idéale pour le test des SDRsThe advent of increasingly powerful Integrated Circuits (IC) has led to the emergence of the Software Defined Radio (SDR) concept, which brought the sector of secured mobile communications into a new era. The outstanding performance of these systems results from optimal trade-offs among advanced analog/Radio Frequency (RF) circuitry, high-speed reconfigurable digital hardware and sophisticated real-time software. The inherent sophistication of such platforms poses a challenging problem for product testing. Currently deployed industrial test strategies face rising obstacles due to the costlier RF test equipment, longer test time and lack of flexibility. Moreover, an SDR platform is field-upgradeable, which means it will support standards and scenarii not considered during the design phase. Therefore, an in-field test strategy is not anymore 'a nice to have' feature but a mandatory requirement. In this context, our research aims to invent and develop a new test methodology able to guarantee the correct functioning of the SDR platform post-fabrication and over its operational lifetime. The overall aim of our efforts is to reduce post-manufacture test cost of SDR transceivers by leveraging the reconfigurability of the platform.For tactical radio units that must be field-upgradeable without specialized equipment, Built-in Self-Test (BIST) schemes are arguably the only way to ensure continued compliance to specifications. In this study we introduce a novel RF BIST architecture which uses Periodically Nonuniform Sampling (PNS2) of the transmitter (TX) output to evaluate compliance to spectral mask specifications. Our solution supports a stand-alone implementation, is scalable across a wide set of complex specifications and can be easily applied for in-field testing with small added hardware. Compared to existing analog/RF test techniques, this approach is not limited to a given TX architecture and does not rely on an ad-hoc TX model, which makes it ideal for SDR testing
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Yan, Wenjian. "A wideband frequency synthesizer for built-in self testing of analog integrated circuits." Texas A&M University, 2004. http://hdl.handle.net/1969.1/1059.
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The cost to test chips has risen tremendously. Additionally, the process for testing all functionalities of both analog and digital part is far from simple. One attractive option is moving some or all of the testing functions onto the chip itself leading to the use of built-in self-tests (BISTs). The frequency generator or frequency synthesizer is a key element of the BIST. It generates the clock frequencies needed for testing.
A wide-band frequency synthesizer is designed in the project. The architecture of a PLL is analyzed as well as the modifications carried out. The modified structure has three blocks: basic PLL based frequency synthesizer, frequency down-converter, and output selector. Each of these blocks is analyzed and designed. This frequency synthesizer system overcomes challenges faced by the traditional PLL based frequency synthesizer.
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Jervan, Gert. "High-Level Test Generation and Built-In Self-Test Techniques for Digital Systems." Licentiate thesis, Linköping : Univ, 2002. http://www.ep.liu.se/lic/science_technology/09/73/index.html.
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Han, Dong-Hoon. "Built-In Self Test and Calibration of RF Systems for Parametric Failures." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/14507.
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This thesis proposes a multifaceted production test and post-silicon yield enhancement framework for RF systems. The three main components of the proposed framework are the design, production test, and post-test phase of the overall integrated circuit (IC) development cycle. First, a circuit-sizing method is presented for incorporating test considerations into algorithms for automatic circuit synthesis/device resizing. The sizing problem is solved by using a cost metric that can be incorporated at minimal computational cost into existing optimization tools for manufacturing yield enhancement. Along with the circuit-sizing method introduced in the design phase, a low-cost test and diagnosis method is presented for multi-parametric faults in wireless systems. This test and diagnosis method allows accurate prediction of the end-to-end specifications as well as for the specifications of all the embedded modules. The procedure is based on application of optimized test stimulus and the use of a simple diode-based envelope detector to extract the transient test response envelope at RF signal nodes. This eliminates the need to make RF measurements using expensive standard testers. To further improve the parametric yield of RF circuits, a performance drift-aware adaptation scheme is proposed that automatically compensates for the loss of circuit performance in the presence of process variations. This work includes a diagnosis algorithm to identify faulty circuits within the system and a compensation process that adjusts tunable components to reduce the effects of performance variations. As a result, all the mentioned components contribute to producing a low-cost production test and to enhancing post-silicon parametric yield.
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Zakizadeh, Jila. "Built-in self-test techniques for analog and mixed signal circuits." Thesis, University of Ottawa (Canada), 2005. http://hdl.handle.net/10393/27094.
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The present thesis attempts to develop new techniques for testing analog parts of embedded cores-based mixed signal integrated circuits and systems. In particular, the oscillation based test methodologies have been investigated in the thesis. In the oscillation based test methods, the circuit under test (CUT) is first converted to an oscillator in the test mode and the oscillation parameters, viz. frequency, amplitude, etc. are then measured. Any deviation of these parameters causes either the oscillation frequency of the converted CUT to differ from its nominal value, or the converted CUT stops oscillation altogether. For evaluation purpose, a program has been written in C to help us in simulating our test methodologies. The program is used to inject faults to the circuit under test. The detailed experimental results provided give frequency and amplitude measurements data performed on the individual circuit blocks together with fault coverage. In this work, however, only catastrophic faults were considered. The simulation experiments carried out on different circuits not only demonstrate that the developed approaches are quite feasible but show in addition that the fault coverage is quite satisfactory (100%) in all cases.
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Gjermundnes, Øystein. "Exploiting Arithmetic Built-In-Self-Test Techniques for Path Delay Fault Testing." Doctoral thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2006. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-2149.
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This thesis describes the implementation of a system for analyzing circuits with respect to their path-delay fault testability. The system includes a path-delay fault simulator and an ATPG for path-delay faults combined into a test tool. This test tool can run standalone on a single machine, or as one of several clients that communicate through a central server. The test tool is used in this thesis in order to evaluate the performance of 14 different test vector generators that can be used in various built-in self-test arrangements.
The test generators exploit pseudo-random stimuli generation. We have used six different strategies for weighting of input signals, and performed comprehensive experiments to evaluate the efficiency of the strategies. Each of the experiments typically consists of three phases:
• In the first phase, the ATPG is used in order to find the K-longest nonrobust testable path-delay faults. The corresponding path numbers are then saved together with the corresponding test vector for later use. The paths constitute the target fault list during simulation. Experiments that consider all possible faults skip this phase.
• In the second phase, weights are generated for the weighted pseudorandom generators. These weights are stored for later use. This phase is skipped for experiments where the generator is unweighted.
• In the third phase the actual simulation takes place. In all experiments 10M single-input-change test patterns were applied and repeated ten times for each generator and circuit in order to cover some statistical variations. Only non-robust faults (including robust faults) were considered.
Two groups of pseudo-random generators have been evaluated. The first group, GA, consists of accumulator based pseudo-random generators. The second group, GT, consists of Mersenne twister based pseudo-random generators.
The result has shown that the GT group of pseudo-random patterns give marginally better results than the GA group. Since GA generators are much less computationally intensive, GA generators are reccommended over GT generators in practical applications. Experiments have also been conducted in order to evaluate the benefit of weighted stimuli compared to unweighted stimuli. The results show that test time can be reduced with up to 15 times for the circuits in the ISCAS’85 benchmark suite.
Based upon comprehensive experiments with various weighting schemes on ISCAS benchmarks, one can conclude that the following three-phase approach works well: First, generate test patterns to detect the K(20000) longest paths. Subsequently, compute weights for each input based upon the gennerated patterns. Finally, employ an accumulator based BIST scheme with the weights on non-robust path-delay faults.
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Newalkar, Aditya. "Alternative techniques for Built-In Self-Test of Field Programmable Gate Arrays." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/master's/NEWALKAR_ADITYA_6.pdf.
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Kim, Han Bin. "High-Level Synthesis and Implementation of Built-In Self-Testable Data Path Intensive Circuit." Diss., Virginia Tech, 1999. http://hdl.handle.net/10919/30257.
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A high-level built-in self-test (BIST) synthesis is a process of transforming a behavioral description into a register-transfer level structural description while minimizing BIST overhead. Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of a large design space, which may result in a local optimum.
In this thesis, we present three methods, which aim to address the problem. The first method tries to find a register assignment for each k-test session in a heuristic manner, where k=1,2,â ¦,N and N is the number of modules of the circuit. Therefore, it offers a range of designs with different figures of merit in area and test time. The second method is based on integer linear programming (ILP). The proposed ILP based method performs the three tasks, assignments of registers, interconnections, and BIST registers, concurrently to yield optimal or near-optimal designs. We describe a complete set of ILP formulations for the three tasks. The ILP based method achieves optimal solutions for most circuits in hardware overhead, but it takes long processing time. The third method, the region-wise heuristic method. It partitions a given data flow graph into smaller regions based on control steps and applies the ILP to each region successively to reduce the processing time.
To measure the performance of BIST accurately and to demonstrate the practicality of our BIST synthesis method, we implemented a DSP circuit; an 8x8 two-dimensional discrete cosine transform (DCT) processor. We implemented two versions of the algorithm, one with incorporation of our BIST method and the other without BIST, to verify the validity of our simplified cost model to estimate BIST area overhead. The two major parts of the circuit, data path and controller, were synthesized using our high-level BIST synthesis tool. All the circuits are implemented and laid out using an ASIC design flow developed at Virginia Tech.
Experimental results show that the three proposed high-level BIST synthesis methods perform better than or comparable to existing BIST synthesis systems. They indeed yield various designs that enable users to trade between area overhead and test time. The region-wise heuristic method reduces the processing time by several orders of magnitude, while the quality of the solution is slightly compromised compared with the ILP-based optimal method. The implementation of DCT circuits demonstrate that our method is applicable to industry size circuits, and the BIST area overhead measured at the layout is close to the estimated one.Ph. D.
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El, Kassir Bilal. "Contribution à la conception et à l'évaluation de circuits BIST pour application RF intégrées." Limoges, 2011. http://www.theses.fr/2011LIMO4064.
Full textAbstract:
Dans cette thèse, des solutions de DFT (Design For Test) et de BIST (Built In Self Test) pour différentes applications RF ont été étudiées. L'analyse et la comparaison de ces différentes solutions à l'ordre de performances des tests, de la complexité des circuits utilisés et le facteur d'intégration ont guidé la direction de l'étude et de la conception de cette contribution. Des circuits BIST utilisant des détecteurs MOS et Bipolaires ont été conçus pour les applications suivantes : mesure de l'EVM en utilisant un DSP (approche de conception); mesure des paramètres de LNA sur la puce (gain IP3, IMx, etc. . . ); un étalonnage des oscillateurs intégrés (VCO à PLL). Pour la mesure de l'EVM, l'utilisation de la technique BIST proposée, a démontré une réduction de la durée du test (par un facteur 1000) ainsi qu'une mise en oeuvre facile. Les limites observées de cette technique sont liées aux défis de mesure EVM BIST en raison de l'existence d'une zone aveugle pour la détection efficace. En ce qui concerne l'application de LNA, les solutions proposées ont démontré un temps de test relativement faible (estimé de - 20 %), un faible coût et une facilité de mise en oeuvre de la procédure de test. La conception de la solution BIST pour la caractérisation de circuit LNA a été développée sur la base d'une implémentation sur puce. Les principales limitations concernent la nécessité d'une surface supplémentaire de silicium, ce qui augmente la consommation et les couplages parasites. L'application de solutions BIST pour commander les oscillateurs intégrés a des avantages liés à la stabilisation de la performance de bruit indépendamment de la variation de processus, de puissance et de température. Toutefois, ces solutions de contrôle induisent une augmentation de la consommation globale du circuit et une dégradation jusqu'à 4 dBc/Hz de bruit de phase donc une dégradation de la qualité du spectre de signal critique (VCO, PLL)In this thesis, a review of DFT (Design For Test) and BIST (Built In Self Test) solutions for different RF applications was studied. The analysis and comparison of these different solutions in terms of their RF performances and testing time has been conducted. The complexity reduction of the used circuits together with the integration factor has been considered as strong enablers for the proposed contribution. BIST circuits using MOS and Bipolar detectors were designed for the following applications : measurement of the EVM through an implementation of DSP type (design approach); On-Chip measurement of the LNA parameters (gain, IP3, IMx, etc. . . ); a calibration of integrated oscillators (VCOs in PLLs). For the EVM measurement, the use of proposed BIST techniques demonstrated a reduction of test time (by a factor 1000) accompanied with an easy implementation. Main limitations observed with this technique are related to challenges relative to EVM BIST measurement due to the existence of a blind zone which hampers effective detection. In the context of WLAN applications, proposed LNA BIST solutions have demonstrated a relatively reduced test time (estimated 20 % improvement), low cost and ease of implementation of the test procedure. The design of the BIST solution for the characterization of LNA circuit has been developed based on an implementation of sensoring system with relatively low on-chip area occupation and current consumption. Perceveid limitations concern the need for additional integration of silicon area, increasing consumption and interferences/couplings. The application of BIST solutions for controlling integrated oscillators has interesting advantages related to the stabilization of noise performance regardless of processes, power and temperature variations. However, these control solutions induce an increase in overall consumption of the circuit which can reach a value of 4 dBc/Hz (add frequency) in Phase noise degradation leading to reduction in the spectral quality of signals in critical blocks such as VCOs/PLLs. Perspectives are drawn to mitigate the identified limiting factors
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Bakshi, Dhrumeel. "Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/35474.
Full textAbstract:
With the increase of device complexity and test-data volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in Self Test (LBIST) is a viable alternative test strategy as it helps reduce dependence on an elaborate external test equipment, enables the application of a large number of random tests, and allows for at-speed testing. The main problem with LBIST is suboptimal fault coverage achievable with random vectors. LFSR reseeding is used to increase the coverage. However, to achieve satisfactory coverage, one often needs a large number of seeds. Computing a small number of seeds for LBIST reseeding still remains a tremendous challenge, since the vectors needed to detect all faults may be spread across the huge LFSR vector space. In this work, we propose new methods to enable the computation of a small number of LFSR seeds to cover all stuck-at faults as a first-order satisfiability problem involving extended theories. We present a technique based on SMT (Satisfiability Modulo Theories) with the theory of bit-vectors to combine the tasks of test-generation and seed computation. We describe a seed reduction flow which is based on the `chaining' of faults instead of pre-computed vectors. We experimentally demonstrate that our method can produce very small sets of seeds for complete stuck-at fault coverage. Additionally, we present methods for inserting test-points to enhance the testability of a circuit in such a way as to allow even further reduction in the number of seeds.Master of Science
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Elbadri, Mohammed. "A reconfigurable processing unit for digital circuit testing using built-in self-test techniques." Thesis, University of Ottawa (Canada), 2007. http://hdl.handle.net/10393/27514.
Full textAbstract:
Digital circuit testing is presented in this thesis. This thesis introduces an architecture that accelerates benchmarked circuit testing. Traditionally, benchmark circuits are tested on software, because of the complexity in developing a generic hardware architecture capable of testing sequentially or concurrently. The testing is based on Built-in Self-Test (BIST) techniques. The circuit testing is accomplished by two hardware implementations, aimed at increasing execution time with respect to its counterpart, software. The implementation realized and executed in hardware, illustrates the advantages of utilizing hardware platforms for digital circuit testing and it gives a path to developing more complex benchmarked circuits; which would have higher fault coverage.
The novel architecture is targeted for digital circuit testing and adaptive embedded system applications. These applications vary in their constraints (i.e. hard and soft real-time constraints) and environmental conditions (i.e. unknown and unpredictable).
The novel architecture consists of a fixed hardware unit and a Reconfigurable Processor Unit (RPU). The RPU employs hardware functional blocks. These Hardware Blocks (HB) encompass logic that targets their respective applications. We realize and implement HBs that target digital circuit testing applications, by means of BIST techniques.
Experimental results are presented in this thesis. In simple terms, the speedup factors are as high as 1 x 104 for sequential testing.
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Gadde, Priyanka. "A BIST Architecture for Testing LUTs in a Virtex-4 FPGA." University of Toledo / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199.
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Abdallah, Louay. "Capteurs embarqués non-intrusifs pour le test des circuits RF." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-01062479.
Full textAbstract:
Cette thèse vise l'étude de techniques de type BIST pour un front-end RF, considérant des nouveaux types des capteurs intégrés très simples pour l'extraction de signaux. Ces signaux et les stimuli de test associés seront par la suite traités par des algorithmes de l'apprentissage automatique qui devront permettre une prédiction des performances des différents blocs du système. Une évaluation des capteur proposés en tant que métriques de test paramétrique et couverture des fautes catastrophique sera nécessaire pour pouvoir aboutir à des techniques de test à bas coût pour le test de production, permettant une réduction importante du coût de revient des produits.
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Cowhig, Patrick Carpenter. "A Complete & Practical Approach to Ensure the Legality of a Signal Transmitted by a Cognitive Radio." Thesis, Virginia Tech, 2006. http://hdl.handle.net/10919/34969.
Full textAbstract:
The computational power and algorithms needed to create a cognitive radio are quickly becoming available. There are many advantages to having a radio operated by cognitive engine, and so cognitive radios are likely to become very popular in the future. One of the main difficulties associated with the cognitive radio is ensuring the signal transmitted will follow all FCC rules. The work presented in this thesis provides a methodology to guarantee that all signals will be legal and valid. The first part to achieving this is a practical and easy to use software testing program based on the tabu search algorithm that tests the software off-line. The primary purpose of the software testing program is to find most of the errors, specially structural errors, while the radio is
not in use so that it does not affect the performance of the system. The software testing
program does not provide a complete assurance that no errors exist, so to supplement this deficit, a built-in self-test (BIST) is employed. The BIST is designed with two parts, one that is embedded into the cognitive engine and one that is placed into the radio's API.
These two systems ensure that all signals transmitted by the cognitive radio will follow
FCC rules while consuming a minimal amount of computational power. The software testing approach based on the tabu search is shown to be a viable method to test software with improved results over previous methods. Also, the software BIST demonstrated its ability to find errors in the signal production and is dem to only require an insignificant amount of computational power. Overall, the methods presented in this paper provide a complete and practical approach to assure the FCC of the legality of all signals in order to obtain a license for the product.Master of Science
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Kakade, Jayawant Shridhar. "METHODS TO MINIMIZE LINEAR DEPENDENCIES IN TWO-DIMENSIONAL SCAN DESIGNS." OpenSIUC, 2008. https://opensiuc.lib.siu.edu/dissertations/256.
Full textAbstract:
Two-dimensional scan design is an effective BIST architecture that uses multiple scan chains in parallel to test the Circuit Under Test (CUT). Linear Finite State Machines (LFSMs) are often used as on-board Pseudo Random Pattern Generators (PRPGs) in two-dimensional scan designs. However, linear dependencies present in the LFSM generated test-bit sequences adversely affect the resultant fault coverage in two-dimensional scan designs. In this work, we present methods that improve the resultant fault coverage in two-dimensional scan designs through the minimization of linear dependencies. Currently, metric of channel separation and matrix-based metric are used in order to estimate linear dependencies in a CUT. When the underlying sub-circuit (cone) structure of a CUT is available, the matrix-based metric can be used more effectively. Fisrt, we present two methods that use matrix-based metric and minimize the overall linear dependencies in a CUT through explicitly minimizing linear dependencies in the highest number of underlying cones of the CUT. The first method minimizes linear dependencies in a CUT through the selection of an appropriate LFSM structure. On the other hand, the second method synthesizes a phase shifter for a specified LFSM structure such that the overall linear dependencies in a CUT are minimized. However, the underlying structure of a CUT is not always available and in such cases the metric of channel separation can be used more effectively. The metric of channel separation is an empirical measure of linear dependencies and an ad-hoc large channel separation is imposed between the successive scan chains of a two-dimensional scan design in order to minimize the linear dependencies. Present techniques use LFSMs with additional phase shifters (LFSM/PS) as PRPGs in order to obtain desired levels of channel separation. We demonstrate that Generalized LFSRs (GLFSRs) are a better choice as PRPGs compared to LFSM/PS and obtain desired levels of channel separations at a lower hardware cost than the LFSM/PS. Experimental results corroborate the effectiveness of the proposed methods through increased levels of the resultant fault coverage in two-dimensional scan designs.
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AlShaibi, Mohammed F. "Built-in self-test Fixed bit, biased pseudorandom techniques /." 1996. http://catalog.hathitrust.org/api/volumes/oclc/35684116.html.
Full textAbstract:
Thesis (Ph. D.)--University of Wisconsin--Madison, 1996.Typescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 156-164).
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Balasubramanian, Anitha. "A built-in self test (BIST) technique for single-event transient testing in digital circuits." Diss., 2008. http://etd.library.vanderbilt.edu/ETD-db/available/etd-07292008-093802/.
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Varaprasad, B. K. S. V. L. "Testing Of Analog Circuits - Built In Self Test." Thesis, 2006. http://hdl.handle.net/2005/434.
Full textAbstract:
On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip (SoC). This work deals with cost-effective BIST methods and Test Pattern Generation (TPG) schemes in BIST for fault detection and diagnosis of analog circuits. Fault-based testing is used in analog domain due to the applicable test methods/ techniques being general and cost-effective. We propose a novel test method causing the Device Under Test (DUT) to saturate or get out of saturation to detect a fault with simple detection hardware. The proposed test method is best suited for use of existing building blocks in Systems-on-Chip (SoC) for implementation of an on-chip test signal generator and test response analyzer. Test generation for a fault in analog circuit is a compute intensive task. A good test generator produces a highly compact test set with less computational effort without trading the fault coverage. In this context, three new test generation methods viz., MultiDetect, ExpoTan, and MultiDiag for testing analog circuits are presented in this thesis. Testing of analog blocks based on circuit transfer function makes the proposed ATPG methods as general-purpose methods for all kinds of LTI circuits. The principle of MultiDetect method, (i.e., selecting a test signal for which the output amplitude difference between good and faulty circuits is minimum when compared to other test signals in an initial test set), helps in the generation of high quality compacted test set with less fault simulations. The experimental results show that the testing of LTI circuits using MultiDetect technique for the benchmark circuits achieves the required fault coverage with much shorter testing time. The generated test set with MultiDetect method can effectively detect both soft and hard faults and does not require any precision analog signal sources or signal measurement circuits when implemented as Built In Self Test (BIST). Test generation for a list of faults and test set compaction are two different phases in an ATPG process. To build an efficient ATPG, these two phases need to be combined with a technique such that the generated test set is highly compact and efficient with less fault simulations. In this context, a novel test set selection technique known as ExpoTan for testing Linear Time Invariant (LTI) circuits is also presented in this thesis. The test generation problem is formulated with tan-1( ) and exponential functions for identification of a test signal with maximum fault coverage. Identification of a sinusoid that detects more faults results in an optimized test signal set. Fault diagnosis and fault location in analog circuits are of fundamental importance for design validation and prototype characterization in order to improve yield through design modification. In this context, we propose a procedure viz., MultiDiag for generation of a test set for analog fault diagnosis. The analog test generation methods, viz., Max, Rand, and MultiDetect etc., which are based on sensitivity analysis, may fail at times to identify a test signal for locating a fault; because the search for a test signal using these test generation methods is restricted to the limited test signals set. But, the MultiDiag method definitely identifies a test signal, if one exists, for locating a fault.
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Santin, Edinei. "A built-in self-test technique for high speed analog-to-digital converters." Doctoral thesis, 2014. http://hdl.handle.net/10362/14389.
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Vasudevamurthy, Rajath. "Time-based All-Digital Technique for Analog Built-in Self Test." Thesis, 2013. http://hdl.handle.net/2005/2841.
Full textAbstract:
A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis. With technology scaling, the inverter switching times are becoming shorter thus leading to better resolution of edges in time. This time resolution is observed to be superior to voltage resolution in the face of reducing supply voltage and increasing variations as physical dimensions shrink. In this thesis, a new method of observability of analog signals is proposed, which is digital-friendly and scalable to future deep sub-micron (DSM) processes. The low-bandwidth analog test voltage is captured as the delay between a pair of clock signals. The delay thus setup is measured digitally in accordance with the desired resolution.
Such an approach lends itself easily to distributed manner, where the routing of analog signals over long paths is minimized. A small piece of circuitry, called sampling head (SpH) placed near each test voltage, acts as a transducer converting the test voltage to a delay between a pair of low-frequency clocks. A probe clock and a sampling clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head, present at each test node consists of a pair of delay cells and a pair of flip-flops, giving rise to as many sub-sampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding sub-sampled signal pair is fed to a Delay Measurement Unit (DMU) to measure the skew between this pair. The concept is validated by designing a test chip in UMC 130 nm CMOS process. Sub-mV accuracy for static signals is demonstrated for a measurement time of few milliseconds and ENOB of 5.29 is demonstrated for low bandwidth signals in the absence of sample-and-hold circuitry.
The sampling clock is derived from the probe clock using a PLL and the design equations are worked out for optimal performance. To validate the concept, the duty-cycle of the probe clock, whose ON-time is modulated by a sine wave, is measured by the same DMU. Measurement results from FPGA implementation confirm 9 bits of resolution.
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Tamilarasan, Karthik Prabhu. "Built-In Self Test (BIST) for Realistic Delay Defects." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8923.
Full textAbstract:
Testing of delay defects is necessary in deep submicron (DSM) technologies. High coverage delay tests produced by automatic test pattern generation (ATPG) can be applied during wafer and package tests, but are difficult to apply during the board test, due to limited chip access. Delay testing at the board level is increasingly important to diagnose failures caused by supply noise or temperature in the board environment. An alternative to ATPG is the built-in self test (BIST). In combination with the insertion of test points, BIST is able to achieve high coverage of stuck-at and transition faults. The quality of BIST patterns on small delay defects is an open question. In this work we analyze the application of BIST to small delay defects using resistive short and open models in order to estimate the coverage and correlate the coverage to traditional delay fault models.
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"In-field Built-in Self-test for Measuring RF Transmitter Power and Gain." Master's thesis, 2015. http://hdl.handle.net/2286/R.I.36378.
Full textAbstract:
abstract: RF transmitter manufacturers go to great extremes and expense to ensure that their product meets the RF output power requirements for which they are designed. Therefore, there is an urgent need for in-field monitoring of output power and gain to bring down the costs of RF transceiver testing and ensure product reliability. Built-in self-test (BIST) techniques can perform such monitoring without the requirement for expensive RF test equipment. In most BIST techniques, on-chip resources, such as peak detectors, power detectors, or envelope detectors are used along with frequency down conversion to analyze the output of the design under test (DUT). However, this conversion circuitry is subject to similar process, voltage, and temperature (PVT) variations as the DUT and affects the measurement accuracy. So, it is important to monitor BIST performance over time, voltage and temperature, such that accurate in-field measurements can be performed.
In this research, a multistep BIST solution using only baseband signals for test analysis is presented. An on-chip signal generation circuit, which is robust with respect to time, supply voltage, and temperature variations is used for self-calibration of the BIST system before the DUT measurement. Using mathematical modelling, an analytical expression for the output signal is derived first and then test signals are devised to extract the output power of the DUT. By utilizing a standard 180nm IBM7RF CMOS process, a 2.4GHz low power RF IC incorporated with the proposed BIST circuitry and on-chip test signal source is designed and fabricated. Experimental results are presented, which show this BIST method can monitor the DUT’s output power with +/- 0.35dB accuracy over a 20dB power dynamic range.Dissertation/Thesis
Masters Thesis Electrical Engineering 2015
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Jin, Xiankun. "A SEIR-based ADC built-in-self-test and its application in ADC self-calibration." Thesis, 2013. http://hdl.handle.net/2152/24051.
Full textAbstract:
The static linearity test is one of the fundamental production tests used to measure DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip signal generator has made it prohibitive. The stimulus error identification and removal (SEIR) method has greatly reduced the linearity requirement. However, it requires a highly stable voltage offset, which remains a daunting task. This work exploits the inherit capacitive sample-and-hold circuit used in various ADC architectures to inject offset with very good constancy. A 16-bit successive approximate register (SAR) ADC with the proposed BIST scheme is modeled and simulated in Matlab to prove its validity. The results show that the estimation error on the maximum INL is less than 0.07 LSB. This BIST solution is then naturally extended to the calibration of an ADC. It is shown missing codes of such ADC can be effectively estimated and calibrated out.text
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Garcia, Juan Elias. "Piezoelectric transducer built-in self-test for logging while drilling instrument sensor evaluation at rig site." Thesis, 2014. http://hdl.handle.net/2152/26344.
Full textAbstract:
Logging While Drilling (LWD) instruments used in oil and gas exploration are subjected to extreme environmental conditions that make reliable operation a major challenge. The sensors directly exposed to this environment experience accelerated aging and may suffer physical damage leading to failure. The cost of drilling and rig operations is very high magnifying any failures or issues with LWD tools. The goal of this report is to present a built-in self-test for an instrument sensor that provides a means to evaluate sensor functionality. The sensor is a piezoelectric ultrasonic transducer. A brief review of the sensor physics will be given. I will review some methods for characterizing piezoelectric ceramic materials and transducers. The application of sensor test methods is applied in an ultrasound pulse-echo application. A brief review of the application circuit will be covered including state of the art in commercial ultrasound integrated circuit design. A prototype of the BIST method is evaluated using test transducers to verify the circuit provides indication of a transducers ability to function correctly. The prototype is achieved through the AD5933 demo board and MATLAB is used for data processing.text
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"An Electrical Stimulus based Built In Self Test (BIST) circuit for Capacitive MEMS accelerometer." Master's thesis, 2013. http://hdl.handle.net/2286/R.I.18677.
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abstract: Micro Electro Mechanical Systems (MEMS) is one of the fastest growing field in silicon industry. Low cost production is key for any company to improve their market share. MEMS testing is challenging since input to test a MEMS device require physical stimulus like acceleration, pressure etc. Also, MEMS device vary with process and requires calibration to make them reliable. This increases test cost and testing time. This challenge can be overcome by combining electrical stimulus based testing along with statistical analysis on MEMS response for electrical stimulus and also limited physical stimulus response data. This thesis proposes electrical stimulus based built in self test(BIST) which can be used to get MEMS data and later this data can be used for statistical analysis. A capacitive MEMS accelerometer is considered to test this BIST approach. This BIST circuit overhead is less and utilizes most of the standard readout circuit. This thesis discusses accelerometer response for electrical stimulus and BIST architecture. As a part of this BIST circuit, a second order sigma delta modulator has been designed. This modulator has a sampling frequency of 1MHz and bandwidth of 6KHz. SNDR of 60dB is achieved with 1Vpp differential input signal and 3.3V supplyDissertation/Thesis
M.S. Electrical Engineering 2013
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Lin, Chen-Wei, and 林政偉. "Built-In Self-Test and Self-Repair Techniques for TFT Array." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/51897805436172253628.
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碩士國立臺灣大學
電子工程學研究所
95
TFT array is a matrix-like structure which contains thousands to millions pixels to display information. However to it’s difficult to make sure that the TFT panel manufactured is no-defect which means all the pixels are well and all the metal wires are continuous. Therefore it’s necessary to test the array including the wires and the pixels. For testing the TFT array, large probes number of ATE and long testing time are needed traditionally. To improve this, this thesis proposed two built-in self-test techniques for testing the pixels and the scan/data line respectively. Both the technique can also be applied into SoG (System on Glass) concept.
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Lin, Chen-Wei. "Built-In Self-Test and Self-Repair Techniques for TFT Array." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1707200711552700.
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"Built-in-Self Test of Transmitter I/Q Mismatch and Nonlinearities Using Self-Mixing Envelope Detector." Master's thesis, 2012. http://hdl.handle.net/2286/R.I.15094.
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abstract: Built-in-Self-Test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to do RF signal analysis. Existing on-chip resources, such as power or envelope detectors, or small additional circuitry can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as IQ imbalance, is challenging. In this work, a BiST technique to compute transmitter IQ imbalances using measurements out of a self-mixing envelope detector is proposed. Both the linear and non linear parameters of the RF transmitter path are extracted successfully. We first derive an analytical expression for the output signal. Using this expression, we devise test signals to isolate the effects of gain and phase imbalance, DC offsets, time skews and system nonlinearity from other parameters of the system. Once isolated, these parameters are calculated easily with a few mathematical operations. Simulations and hardware measurements show that the technique can provide accurate characterization of IQ imbalances. One of the glaring advantages of this method is that, the impairments are extracted from analyzing the response at baseband frequency and thereby eliminating the need of high frequency ATE (Automated Test Equipment).Dissertation/Thesis
M.S. Electrical Engineering 2012
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Liu, Chia-Hsiu, and 劉嘉修. "Low-Power Built-in Self-Test Techniques for Embedded SRAMs." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/55675209099184789244.
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碩士輔仁大學
電子工程學系
95
The severity of power consumption during parallel BIST of embedded memory cores is growing significantly. In order to alleviate this problem, an address sequence reordering technique and a row bank-based pre-charge technique are proposed for low-power testing of embedded SRAMs. Address sequence reordering technique uses the single-bit-change (SBC) counter to replace the binary counter during the test mode. It will effectively decrease the average and peak power of the address lines. Besides, a row bank-based pre-charge technique based on the DWL (divided world line) architecture is proposed. In low-power test mode, instead of pre-charging the entire memory array, only the current accessed row bank is pre-charged. This will result in significant power saving for the pre-charge circuitry. An SRAM chip with 2 Kbits is implemented with TSMC 0.18 μm process. It integrates the hierarchical bit line with local sense amplifier technique and row bank-based pre-charge technique. According to experimental results, 48.9% power reduction can be achieved for a 256 × 256 bit-oriented SRAM. Moreover, if the number of row banks increases, the power saving will also increase.
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Tsai, Ching Hong, and 蔡慶宏. "Built-In Self-Test Techniques Using Boundary Scan Standard Circuitry." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/45121662402168740549.
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碩士國立清華大學
電機工程研究所
82
Built-in self-test (BIST) is a design method which attempts to deal with the inherent complex -ity of testing the VLSI circuits. It requires hardware overhead to incorporate a test pattern generator, an output response analyzer, and a BIST controller into the original system logic. The advantage of BIST design over traditional VLSI design for testability techniques include high speed and low pin overhead. In this thesis, we use the boundary scan regis -ter, which is a mandatory test data register required in IEEE Std. 1149.1, to perform the fun -ction of on-chip test pattern generator and output response analyzer. In addition, we use the TAP (test access port) controller which is also defined in IEEE Std. 1149.1 to control the BIST process. Detailed design of the boundary scan circuitry which has the self-test ability is presented. To verify the feasibility of our design, Verilog simulation and mask layout of the entire circuit has been completed. According to the simulation result, any desired test se -quence can be obtained by constructing the boun -dary scan register cells properly.
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Li, Hongzhi [Verfasser]. "A BIST (built-in self-test) strategy for mixed-signal integrated circuits / vorgelegt von Hongzhi, Li." 2004. http://d-nb.info/973090375/34.
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"Monitoring for Reliable and Secure Power Management Integrated Circuits via Built-In Self-Test." Master's thesis, 2019. http://hdl.handle.net/2286/R.I.54959.
Full textAbstract:
abstract: Power management circuits are employed in most electronic integrated systems, including applications for automotive, IoT, and smart wearables. Oftentimes, these power management circuits become a single point of system failure, and since they are present in most modern electronic devices, they become a target for hardware security attacks. Digital circuits are typically more prone to security attacks compared to analog circuits, but malfunctions in digital circuitry can affect the analog performance/parameters of power management circuits. This research studies the effect that these hacks will have on the analog performance of power circuits, specifically linear and switching power regulators/converters. Apart from security attacks, these circuits suffer from performance degradations due to temperature, aging, and load stress. Power management circuits usually consist of regulators or converters that regulate the load’s voltage supply by employing a feedback loop, and the stability of the feedback loop is a critical parameter in the system design. Oftentimes, the passive components employed in these circuits shift in value over varying conditions and may cause instability within the power converter. Therefore, variations in the passive components, as well as malicious hardware security attacks, can degrade regulator performance and affect the system’s stability. The traditional ways of detecting phase margin, which indicates system stability, employ techniques that require the converter to be in open loop, and hence can’t be used while the system is deployed in-the-field under normal operation. Aging of components and security attacks may occur after the power management systems have completed post-production test and have been deployed, and they may not cause catastrophic failure of the system, hence making them difficult to detect. These two issues of component variations and security attacks can be detected during normal operation over the product lifetime, if the frequency response of the power converter can be monitored in-situ and in-field. This work presents a method to monitor the phase margin (stability) of a power converter without affecting its normal mode of operation by injecting a white noise/ pseudo random binary sequence (PRBS). Furthermore, this work investigates the analog performance parameters, including phase margin, that are affected by various digital hacks on the control circuitry associated with power converters. A case study of potential hardware attacks is completed for a linear low-dropout regulator (LDO).Dissertation/Thesis
Masters Thesis Electrical Engineering 2019
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Yeh, Chien-Hung, and 葉建宏. "Efficient Built-in Self-test Techniques for Memory-Based FFT Processors." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/97345365948679046162.
Full textAbstract:
碩士輔仁大學
電子工程學系
91
An efficient built-in self-test (BIST) architecture for memory-based FFT processor has been proposed in this paper. The BIST architecture can reduces the testing time during the test mode. It is because that the memory module and the logic module of the memory-based FFT processor are tested in parallel. This approach also provide a low hardware overhead BIST structure for the memory-based FFT processor that it because the logic module and the memory module can share a common BIST controller and the output response analyzer of the BIST architecture for memory-based FFT processor can be implementation with the inherent functions of the logic module.. Based on our approach, the hardware overhead of the BIST architecture for memory-based FFT architecture is only 4.06%.
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"System Identification, Diagnosis, and Built-In Self-Test of High Switching Frequency DC-DC Converters." Doctoral diss., 2017. http://hdl.handle.net/2286/R.I.46313.
Full textAbstract:
abstract: Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to smaller solution size (higher power density) and higher efficiency. As the filter components become smaller in value and size, they are unfortunately also subject to higher process variations and worse degradation profiles jeopardizing stable operation of the power supply. This dissertation presents techniques to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation. A digital pseudo-noise (PN) based stimulus is used to excite the DC-DC system at various circuit nodes to calculate the corresponding closed-loop impulse response. The test signal energy is spread over a wide bandwidth and the signal analysis is achieved by correlating the PN input sequence with the disturbed output generated, thereby
accumulating the desired behavior over time. A mixed-signal cross-correlation circuit is used to derive on-chip impulse responses, with smaller memory and lower computational requirement in comparison to a digital correlator approach. Model reference based parametric and non-parametric techniques are discussed to analyze the impulse response results in both time and frequency domain. The proposed techniques can extract open-loop phase margin and closed-loop unity-gain frequency within 5.2% and 4.1% error, respectively, for the load current range of 30-200mA. Converter parameters such as natural frequency (ω_n ), quality factor (Q), and center frequency (ω_c ) can be estimated within 3.6%, 4.7%, and 3.8% error respectively, over load inductance of 4.7-10.3µH, and filter capacitance of 200-400nF. A 5-MHz switching frequency, 5-8.125V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed built-in self-test (BIST) analysis. The converter output voltage range is 3.3-5V and the supported maximum
load current is 450mA. The peak efficiency of the converter is 87.93%. The proposed converter is fabricated on a 0.6µm 6-layer-metal Silicon-On-Insulator (SOI) technology with a die area of 9mm^2 . The area impact due to the system identification blocks including related I/O structures is 3.8% and they consume 530µA quiescent current during operation.Dissertation/Thesis
Doctoral Dissertation Electrical Engineering 2017
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Liang, Sheng-Chuan, and 梁聖泉. "Built-in Self-Test Techniques for Sigma-Delta Analog-to-Digital Converters." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/00689419825762506294.
Full textAbstract:
博士國立交通大學
電機與控制工程系所
97
Testing high resolution analog-to-digital converters (ADCs) such as Σ-Δ modulators is very costly because of the requirements of a high-end mixed-signal automatic test equipment (ATE) and a long test time. Besides, the test setup is also very bothersome since the cost of an ultra-low noise testing environment is substantial. Furthermore, the testability of the ADC under test (AUT) becomes worse when the high resolution AUT is embedded in a complex system-on-chip (SoC) device. To address these issues, build-in self-test (BIST) techniques are drawing more and more attention. In this dissertation, we propose the BIST techniques for Σ-Δ ADC to address these testing issues. The first part of this dissertation proposes a BIST Σ-Δ ADC design. The AUT is a second-order design-for-digital-testability (DfDT) Σ-Δ modulator. The DfDT scheme enables the AUT to be tested by the digital stimuli. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with the conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order DfDT Σ-Δ modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) difference between the conventional FFT analysis and the proposed BIST design is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications. Although the BIST design is very successful, we notice that the digital tests present somewhat lower SNDR than that of the conventional analog test. The most significant difference between the digital tests and the corresponding analog tests is found in the the tests with the largest stimuli. In the second part of this dissertation, we investigated the root causes of the SNDR difference and found the shaped noise of the digital stimulus reduces the BIST accuracy. To alleviate the impacts of the shaped noise of the digital stimulus, we proposed a decorrelating design-for-digital-testability (D3T) scheme to replace the DfDT scheme for Σ-Δ modulators so as to improve digital test accuracy. The modulator under test (MUT) employs the D3T scheme has two operation modes: the normal mode and the digital test mode. In the digital test mode, the input switched-capacitor network of the D3T modulator is reconfigured as two sub-digital-to-charge converters (sub-DCCs). Each of the sub-DCCs accepts a Σ-Δ modulated bit-stream as its test stimulus. By inputting the two sub-DCCs with the same Σ-Δ modulated bit-stream but with different delays, the MUT is equivalently tested by the result of filtering the bit-stream with a finite-impulse-response low-pass filter. Consequently, the D3T MUT suffers less from the undesired shaped noise of the digital stimuli, and enhances the test accuracy. A test chip has been designed and fabricated in order to verify the effectiveness of the proposed D3T scheme. The measurement results show that the MUT achieves a peak SNDR of 80.1 dB using the digital tests at an oversampling ratio of 128. The differences of the SNDR values in the digital and conventional analog tests are no more than 1.9 dB except for the -3 dBFS test. The analog hardware overhead of the D3T MUT consists of only 18 switches. In addition, the D3T scheme also provides a high fault observability and at-speed testability, because most of the MUT's components are active and have the same loads in both modes.
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Chen, Sheng-Tai, and 陳生泰. "Built-In Self-Test Techniques for Dynamic Specifications of ADC and DAC." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/55684320547727152864.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
94
In this thesis, we present an on-chip BIST scheme for testing the dynamic specifications of A/D and D/A converters. For dynamic ADC testing, rather than building a sinusoidal waveform generator on chip, we instead emulate the input transitions of a sinusoidal waveform by using a ramp generator together with a DAC. For dynamic DAC testing, we use a ramp generator and a comparator to under-sample the DAC''s output waveform and thus don’t require a digital storage oscilloscope to measure the DAC output. The main contribution in this work is that our proposed BIST scheme is no longer confined to static testing. It can measure the dynamic parameters of A/D and D/A converters. Moreover, it can easily be implemented to perform both static testing and dynamic testing. Test time can be traded for test accuracy depending on the applications.