Journal articles: 'Built-In Self Test (BIST) techniques'

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Lu, Shyue-Kung, Yuang-Cheng Hsiao, Chia-Hsiu Liu, and Chun-Lin Yang. "Low-Power Built-In Self-Test Techniques for Embedded SRAMs." VLSI Design 2007 (October 29, 2007): 1–6. http://dx.doi.org/10.1155/2007/67019.

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The severity of power consumption during parallel BIST of embedded memory cores is growing significantly. In order to alleviate this problem, a row bank-based precharge technique based on the divided wordline (DWL) architecture is proposed for low-power testing of embedded SRAMs. The memory cell array is first divided into row banks. The effectiveness of the row bank-based precharge technique is due to the predictable address sequence during test. In low-power test mode, instead of precharging the entire memory array, only the current accessed row bank is precharged. This will result in significant power saving for the precharge circuitry. The precharge power can be reduced to 1/b of that of the traditional precharge techniques, where b denotes the number of row banks in the memory array. With simple transmission gates and inverters, the modified precharge control circuitry was also designed. The hardware overhead for implementing the low-power technique is almost negligible. Moreover, the corresponding BIST design to implement the low-power technique is almost the same as the conventional BIST designs. It is also notable that the inherent low-power characteristics of the DWL architecture can be preserved. According to experimental results, 48.9% power reduction can be achieved for a 256 × 256 bit-oriented SRAM. The memory is divided into 8 row banks. Moreover, if the number of row banks increases, the power saving will also increase.

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Chen, Chien-In Henry. "Partitioning Techniques for Built-In Self-Test Design." VLSI Design 2, no. 3 (January 1, 1994): 185–98. http://dx.doi.org/10.1155/1994/25656.

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An efficient, unified algorithm, Advanced Two-Phase Cluster Partitioning, is proposed for automated synthesis of pseudo-exhaustive test generator for Built-In Self-Test (BIST) design. A prototype of the algorithm, Two-Phase Cluster Partitioning, has been proposed and the hierarchical design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. However, in certain worst case, the algorithm may generate a sub-optimal design which requires more test patterns and/or hardware overhead. In order to generate a globally optimal design, further improvement of two-phase algorithm can be achieved by expanding the design space for the formation of linear sum so that the number of test signals required for pseudo-exhaustive testing can be reduced. We demonstrate the effectiveness of our approach by presenting detailed comparisons of our results against those that would be obtained by existing techniques.

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Savir, Jacob, and Paul H. Bardell. "Built-In Self-Test: Milestones and Challenges." VLSI Design 1, no. 1 (January 1, 1993): 23–44. http://dx.doi.org/10.1155/1993/81360.

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This paper describes the progress in built-in self-test (BIST) since its inception, and the important problems that still need to be solved to make the technique widely acceptable. The paper includes a reference list and an extensive bibliography on the subject matter.

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Imocha Singh, Nongthombam, and Prashant V. Joshi. "A Brief Review for Semiconductor Memory Testing Based on BIST Techniques." International Journal of Engineering & Technology 7, no. 3.1 (August 4, 2018): 98. http://dx.doi.org/10.14419/ijet.v7i3.1.16807.

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With rapid growth of semiconductor industry and increase in complexity of semiconductor based memory, necessity of stringent testing methodology has become one of top most criteria for memory evaluation. This paper describes the fundamental concepts and overview of Built-In-Self-Test (BIST). It describes different functional faults modeling of RAM and flash memory. This review mentions about testing approaches for memory and illustrates BIST techniques for finding faults, power dissipation, area overhead and test time during testing, also includes research gap and future scope regarding the testing of memory.

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Ince, Mehmet, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, Leroy Winemberg, and Sule Ozev. "Fault-based Built-in Self-test and Evaluation of Phase Locked Loops." ACM Transactions on Design Automation of Electronic Systems 26, no. 3 (February 2021): 1–18. http://dx.doi.org/10.1145/3427911.

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With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

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Balasubramanian, Anitha, B. L. Bhuva, L. W. Massengill, B. Narasimham, R. L. Shuler, T. D. Loveless, and W. Timothy Holman. "A Built-In Self-Test (BIST) Technique for Single-Event Testing in Digital Circuits." IEEE Transactions on Nuclear Science 55, no. 6 (December 2008): 3130–35. http://dx.doi.org/10.1109/tns.2008.2006499.

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Varaprasad, B. K. S. V. L., L. M. Patnaik, H. S. Jamadagni, and V. K. Agrawal. "An Efficient Test Pattern Generation Scheme for an On Chip BIST." VLSI Design 12, no. 4 (January 1, 2001): 551–62. http://dx.doi.org/10.1155/2001/45324.

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Testing and power consumption are becoming two critical issues in VLSI design due to the growing complexity of VLSI circuits and remarkable success and growth of low power applications (viz. portable consumer electronics and space applications). On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip. This paper deals with cost-effective Test Pattern Generation (TPG) schemes in BIST. We present a novel methodology based on the use of a suitable Linear Feedback Shift Register (LFSR) which cycles through the required sequences (test vectors) aiming at a desired fault coverage causing minimum circuit toggling and hence low power consumption while testing. The proposed technique uses circuit simulation data for modeling. We show how to identify the LFSR using graph theory techniques and compute its feedback coefficients (i.e., its characteristic polynomial) for realization of a Test Pattern Generator.

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, Dr. K Deepti, P. Aishwarya. "Design and Implementation of FSM Based MBIST using March Algorithm." International Journal for Modern Trends in Science and Technology, no. 8 (August 5, 2020): 18–21. http://dx.doi.org/10.46501/ijmtst060804.

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The research article aims at identifying memory testing in static random access memory which is significant in deep sub micron era. Built in self test provides a best solution replacing the external Automatic test equipment. Built in Self Test is a technique of designing additional hardware and software feature into Integrated circuits to allow them to perform testing. BIST works in the background checking memories for faults without interfering with actual functionality of the memory. The objective of the proposed work is to identify faults associated with the memory, perform test algorithms to detect the faults in memory BIST architecture.The implementation of Memory BIST is done using Finite state machine model. The design of memory BIST is accomplished using Xilinx Vivado IDE for 32X8 memory.

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Gopal, P. Bala, and K. Hari Kishore. "An FPGA Implementation of On Chip UART Testing with BIST Techniques." International Journal of Reconfigurable and Embedded Systems (IJRES) 5, no. 3 (November 1, 2016): 176. http://dx.doi.org/10.11591/ijres.v5.i3.pp176-182.

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A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.

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Sharma, Rajiv, and Kewal K. Saluja. "Theory, Analysis and Implementation of an On-Line BIST Technique." VLSI Design 1, no. 1 (January 1, 1993): 9–22. http://dx.doi.org/10.1155/1993/34963.

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A Built-ln Concurrent Self-Test (BICST) technique for testing combinational logic circuits concurrently with their normal operation is proposed. Concept of sharing the test hardware between identical circuits to reduce the overall area overhead is introduced. The method was implemented in the design of an ALU with on-line test capability in CMOS technology. The additional hardware used for a 12-bit ALU was 19% of the total chip area and it did not impose any timing overhead on the operation of the ALU. The overhead decreases with an increase in the size of the ALU.Following the description of the BICST technique, measures for evaluating the performance of the BICST technique are defined. Methods for the computation of the performance measures using analytical and simulation techniques are discussed and results of these methods are reported. Methods for detecting intermittent faults and for computing the transient fault coverage using BICST are also described. The impact of BICST on the system diagnostics and system maintenance is discussed.

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VOYIATZIS, I., and D. KEHAGIAS. "A SIC PAIR GENERATOR FOR A BILBO ENVIRONMENT." Journal of Circuits, Systems and Computers 15, no. 05 (October 2006): 739–56. http://dx.doi.org/10.1142/s0218126606003350.

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Built-In Self Test (BIST) techniques are commonly used as an efficient alternative to external testing in today's high-complexity VLSI chips since they provide on-chip test pattern generation and response verification. Among the BIST techniques, Built-In Logic Block Observation (BILBO) has been widely used in practice. Test patterns generated by BILBO structures target the detection of stuck-at faults. It has been shown that most common failure mechanisms that appear into current CMOS VLSI circuits cannot be modeled as stuck-at faults. These mechanisms, modeled by sequential (i.e., stuck-open and delay) faults models, require the application of two-pattern tests (vector pairs) in the circuit-under-test inputs. Single Input Change (SIC) pairs are pairs of patterns where the second pattern differs from the first in only one bit and have been successfully used for two-pattern testing. In this paper we present the BILBO-oriented SIC pair Generator technique that extends BILBO in order to generate SIC pairs; in this way, sequential faults are also detected.

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Praveen, J., and M. N. Shanmukha Swamy. "BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture." Journal of Circuits, Systems and Computers 27, no. 05 (February 6, 2018): 1850078. http://dx.doi.org/10.1142/s0218126618500780.

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In several pseudorandom built-in self-test (BIST) circuits, the applied test vectors will be generated by a linear feedback shift register (LFSR). This type of test pattern generator (TPG) may generate some repeated test patterns, which unnecessarily increases the test power without contributing much to the fault coverage. Based on the vast designs of TPG engine, the chip area also increases by contributing for the overall power consumption of the IC. This paper presents an approach called low power — bit complements test vector generation (LP-BCTVG) technique with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. In order to reduce the test power, the LP-BCTVG inserts appropriate intermediate vectors in between consecutive test vectors generated by LFSR circuit. Hence, the application of final output vectors of LP-BCTVG circuit over circuit under test decreases the test power compared with LFSR-based BIST. By complementing the output bits of LP-BCTVG, we can reduce the bulkiness of TPG engine approximately by half. This further contributes to the reduced IC size. The obtained simulation results prove that this technique can reduce the overall test power consumption along with better fault coverage when compared with LFSR-based BIST and other recent methods. Here, the proposed approach has been tested on several ISCAS’85, ISCAS’89 and ITC’99 benchmark circuits.

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Shirol, Suhas B., and Rajashekar B. Shettar. "A Comparative Study of Low Power Testing Techniques for Digital Circuits." International Journal of Advanced Research in Computer Science and Software Engineering 7, no. 7 (July 30, 2017): 412. http://dx.doi.org/10.23956/ijarcsse/v7i7/0180.

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In recent years, with fast growth of mobile communication and portable computing systems, design for low power has become the challenge in the field of Digital VLSI design. The main focus of the paper is to make a comparative study of low power Linear Feedback Shift Register (LFSR) architecture such as Built In Self Test (BIST), it has been often seen that during test mode process the power consumed is much higher, when compared to that of normal mode process test as there is high switching activity in the nodes of Circuit Under Test(CUT) during testing.

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Karpovsky, Mark G. "Integrated On-Line and Off-Line Error Detection Mechanisms in the Coding Theory Framework." VLSI Design 5, no. 4 (January 1, 1998): 313–31. http://dx.doi.org/10.1155/1998/63013.

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In this paper we present an approach for combining on-line concurrent checking (CC) with off-line built-in self-test (BIST). We will show that a reduction of an aliasing probability can be obtained for manufacturing testing by monitoring the output of a concurrent checker and a reduction of a probability of not detecting an error in the computing mode can be obtained by a short periodic BIST. We will present a technique for optimal selection of error-detecting codes for combined on-line CC and off-line space-time compression of test responses for BIST and estimate probabilities of not detecting an error for the approach based on integrating CC and BIST. We also present a technique for on-line error-detection in space-time compressors of test responses for BIST.

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Zaleski, Dariusz, and Romuald Zielonko. "Two-functional µBIST for Testing and Self-Diagnosis of Analog Circuits in Electronic Embedded Systems." ACTA IMEKO 3, no. 4 (December 1, 2014): 10. http://dx.doi.org/10.21014/acta_imeko.v3i4.150.

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The paper concerns the testing of analog circuits and blocks in mixed-signal Electronic Embedded Systems (EESs), using the Built-in Self-Test (BIST) technique. An integrated, two-functional, embedded microtester (µBIST) based on reuse of signal blocks already present in an EES, such as microprocessors, memories, ADCs, DACs, is presented. The novelty of the µBIST solution is its extended functionality. It can perform 2 testing functions: functional testing and fault diagnosis on the level of localization of a faulty element. For functional testing the Complementary Signals (CSs), and for fault diagnosis the Simulation Before Test (SBT) vocabulary techniques have been used. In the fault vocabulary the graphical signatures in the form of identification curves in multidimensional spaces have been applied.

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Voyiatzis, Ioannis. "A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences." VLSI Design 2008 (March 17, 2008): 1–8. http://dx.doi.org/10.1155/2008/680157.

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Test set embedding built-in self test (BIST) schemes are a class of pseudorandom BIST techniques where the test set is embedded into the sequence generated by the BIST pattern generator, and they displace common pseudorandom schemes in cases where reverse-order simulation cannot be applied. Single-seed embedding schemes embed the test set into a single sequence and demand extremely small hardware overhead since no additional control or memory to reconfigure the test pattern generator is required. The challenge in this class of schemes is to choose the best pattern generator among various candidate configurations. This, in turn, calls for a need to evaluate the location of each test pattern in the sequence as fast as possible, in order to try as many candidate configurations as possible for the test pattern generator. This problem is known as the test vector-embedding problem. In this paper we present a novel solution to the test vector-embedding problem for sequences generated by accumulators. The time overhead of the solution is of the order O(1). The applicability of the presented method for embedding test sets for the testing of real-world circuits is investigated through experimental results in some well-known benchmarks; comparisons with previously proposed schemes indicate that comparable test lengths are achieved, while the time required for the calculations is accelerated by more than 30 times.

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Zhang, Jun Bin, Jin Yan Cai, and Dan Yang Li. "A Novel Fault Orientation Technique of FPGA Configurable Logic Blocks Based on Improved Shift Register." Applied Mechanics and Materials 347-350 (August 2013): 1602–6. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1602.

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With the development of digital integrate circuit system which is based on Field Programmable Gate Arrays (FPGA), the request on FPGA test technique is becoming higher and higher. The Boundary Scan Technique and Built-In Self-Test (BIST) technique appear in succession, however, these techniques dont implement Configurable Logic Block (CLB) fault diagnose and fault orientation. Arrays-based technique was advanced, which also have some problems about masking of faults and too many reconfiguration times. According to these problems, A Novel Shift Register-based technique for Fault Orientation of FPGA Configurable Logic Blocks was advanced. The paper analyses the design theory about core circuit configure, and has important significance impact on Fault Orientation of FPGA Configurable Logic Blocks.

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Savir, Jacob. "BIST Analysis of an Embedded Memory Associated Logic." VLSI Design 12, no. 4 (January 1, 2001): 563–78. http://dx.doi.org/10.1155/2001/91710.

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Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other.This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory.The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs [2, 11, 17], but may also be suitable for use with other detection probability tools [9, 19], and simulation tools [20].

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Ahmad, A., D. Al Abri, S. S. Al Busaidi, and M. M. Bait-Suwailam. "What Causes to Tune a Condition of Exactly Identical Fault-Masks Behaviors in an LFSR based BIST Methodology." Oriental journal of computer science and technology 10, no. 04 (December 25, 2017): 710–17. http://dx.doi.org/10.13005/ojcst/10.04.02.

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The authors show that in a Built-In Self-Test (BIST) technique, based on linear-feedback shift registers, when the feedback connections in pseudo-random test-sequence generator and signature analyzer are images of each other and corresponds to primitive characteristic polynomial then behaviors of faults masking remains identical. The simulation results of single stuck-at faults show how the use of such feedback connections in pseudo-random test-sequence generator and signature analyzer yields to mask the same faults.

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Lahbib, Imene, Mohamed Aziz Doukkali, Philippe Descamps, Patrice Gamand, Christophe Kelma, and Olivier Tesson. "Design and characterization of an integrated microwave generator for BIST applications." International Journal of Microwave and Wireless Technologies 6, no. 2 (February 27, 2014): 195–200. http://dx.doi.org/10.1017/s1759078714000105.

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This paper presents a circuit architecture for a new integrated on chip test method for microwave circuits. The proposed built-in-self-test (BIST) cell targets a direct low-cost measurement technique of the gain and the 1 dB input compression point (CP1) of a K-band satellite receiver in the 18–22 GHz frequency bandwidth. A signal generator at the radiofrequency (RF) front end input of the device under test (DUT) has been integrated on the same chip. To inject this RF signal, a loopback technique has been used and the design has been accommodated for it. This paper focuses on the design of the most sensitive block of the BIST circuit, i.e. the RF signal generator. This circuit, fabricated in a SIGe:C BiCMOS process, consumes 10 mA. It presents a dynamic power range of 17 dB (−41; −24 dBm) and operates in a frequency range of 5.6 GHz (17.5; 23 GHz). This BIST circuit gives new perspectives in terms of test strategy, cost reduction, and measurement accuracy for microwave-integrated circuits and could be adapted for mm-wave circuits.

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B., Nadimulla, and Aruna Mastani, S. "Adjustable PRPG for Low Power Test Patterns." International Journal of Recent Technology and Engineering 9, no. 6 (March 30, 2021): 195–201. http://dx.doi.org/10.35940/ijrte.f5500.039621.

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As the power consumption is more in the processes of testing, test vector set compression and controlling of toggling plays a crucial role in reducing the power consumption during test mode. In exploring the controlling techniques of toggling, Pre-Selected Toggling (PRESTO) of test patterns is a technique that can control the toggling of a test patterns in a precise manner in Built-in Self -Test (BIST) architectures. In this paper we modify the architecture of existing Full Version PRESTO that can be used to generate test vectors and in addition binary sequences used as scan chins such that the controlling of sequence of test vectors depends on number of 1’s present in the switch code which is user defined thus reducing the testing time with significant fault coverage, and in addition the optimization is also observed in area and power. The area has decreased by 12.2% and power consumption by 15.43%. The Synthesis and implementation of the architectures are done using Artix7 (xc7a100tcsg324-3) FPGA family. The simulation results have been analyzed through Mentor-graphics Questa-sim 10.7C

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Du, Min Jie, Jin Yan Ai, Li Min Liu, and Sai Zhu. "Summarization on the Techniques of Testing Electronical System." Advanced Materials Research 433-440 (January 2012): 6437–40. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.6437.

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With the fast development of electronic industry,the techniques of testing electronical system have varied from traditional functional test to structured test accordingly.The principel of functional test is presented in this paper and the representative techniques of structured test, as in-circuit test(ICT),boundary-scan test(BST),build-in self-test(BIST) and scan-path test,are explored subsequently.Finally,the developmenting trends in the future are looked forward to.

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Huang, Shi-Yu. "Improving the Timing of Extended Finite State Machines Via Catalyst." VLSI Design 15, no. 3 (January 1, 2002): 629–35. http://dx.doi.org/10.1080/1065514021000012246.

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We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical path often forms a cycle and thus cannot be cut down easily by popular techniques such as pipelining or retiming. The proposed technique, based on the concept of catalyst, adds a functionally redundant block—which includes a piece of combinational logic and several other registers—to the circuits under consideration so that the timing critical paths are divided into stages. During this transformation, the circuit's functionality is not affected, while the speed is improved significantly. This technique has been successfully applied to an industrial application—a Built-In Self-Test (BIST) circuit for static random access memories (SRAMs). The synthesis result indicates a 47% clock cycle time reduction.

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O.S., Nisha, and Sivasankar K. "Architecture for an efficient MBIST using modified March-y algorithms to achieve optimized communication delay and computational speed." International Journal of Pervasive Computing and Communications 17, no. 1 (January 15, 2021): 135–47. http://dx.doi.org/10.1108/ijpcc-05-2020-0032.

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Purpose In this work, an efficient architecture for memory built in self-test (MBIST) that incorporates a modified March Y algorithm using concurrent technique and a modified linear feedback shift register (LFSR)–based address generator is proposed. Design/methodology/approach Built in self-test (BIST) is emerging as the essential ingredient of the system on chip. In the ongoing high speed, high tech sophistication technology of the very large-scale integrated circuits, testing of these memories is a very tedious and challenging job, since the area overhead, the testing time and the cost of the test play an important role. Findings With the efficient service of the adapted architecture, switching activity is considerably cut down. As the switching activity is in direct proportion to the power consumed scaling down, the switching process of the address generator inevitably leads to the reduction in power consumption of the MBIST. Originality/value To improve the yield and fault tolerance of on-chip memories without degradation on its performance self-repair mechanisms can be implemented on chip.

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Sahu, Anil Kumar, Vivek Kumar Chandra, and G. R. Sinha. "Optimized System Level Hardware Realization of Built-in-Self-Test Approach for Sigma-Delta Analog-to-Digital Converter." International Journal of Electrical and Electronics Research 4, no. 3 (September 30, 2016): 85–90. http://dx.doi.org/10.37391/ijeer.040305.

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System-level modeling is generally needed due to simultaneous increase in design complexity with multi-million gate designs in today’s system-on-chips (SoCs). System C is generally applied to system-level modeling of Sigma-Delta ADC. CORDIC technique and test generation for the testing of mixed signal circuit components such as analog-to-digital converter is mostly implemented in system level modeling. This work focuses on developing fast and yet accurate model of BIST approach for Sigma-Delta ADC. The Sigma-Delta modulator’s ADC static parameters as well as dynamic parameters are degraded. One of the dynamic parameters, signal-to-noise ratio (SNR) is directly obtained by the SIMSIDES (MATLAB SIMULINK tool). Then, the obtained parameters are tested by using Built-in-self-test that is desirable for the VLSI system in order to reduce the non-recurring cost (NRE) per chip by the manufacturer. This paper demonstrates a possibility to realize a simulation of testing strategy of high-resolution Sigma-Delta modulator using MATLAB SIMULINK and Xilinx EDA tool environment. This work also contributes towards the Output Response Analyzer (ORA) being used for testing parameters which help in reducing the difficulties in design of the complete ORA circuit. Moreover, the reusable features of hardware in the computation of different parameters are also improved in the ORA design.

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Lu, Shyue-Kung, Fu-Min Yeh, and Jen-Sheng Shih. "Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs." VLSI Design 15, no. 1 (January 1, 2002): 397–406. http://dx.doi.org/10.1080/1065514021000012011.

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In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.

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Edirisooriya, Geetani. "Closed Form Aliasing Probability For Q-ary Symmetric Errors." VLSI Design 4, no. 3 (January 1, 1996): 199–205. http://dx.doi.org/10.1155/1996/29412.

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In Built-In Self-Test (BIST) techniques, test data reduction can be achieved using Linear Feedback Shift Registers (LFSRs). A faulty circuit may escape detection due to loss of information inherent to data compaction schemes. This is referred to as aliasing. The probability of aliasing in Multiple-Input Shift-Registers (MISRs) has been studied under various bit error models. By modeling the signature analyzer as a Markov process we show that the closed form expression derived for aliasing probability previously, for MISRs with primitive polynomials under q-ary symmetric error model holds for all MISRs irrespective of their feedback polynomials and for group cellular automata signature analyzers as well. If the erroneous behaviour of a circuit can be modelled with q-ary symmetric errors, then the test circuit complexity and propagation delay associated with the signature analyzer can be minimized by using a set of m single bit LFSRs without increasing the probability of aliasing.

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Mrozek, Ireneusz, and Vyacheslav Yarmolik. "Two-Run RAM March Testing with Address Decimation." Journal of Circuits, Systems and Computers 26, no. 02 (November 3, 2016): 1750031. http://dx.doi.org/10.1142/s0218126617500311.

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Conventional march memory tests have high fault coverage, especially for simple faults like stack-at fault (SAF), transition fault (TF) or coupling fault (CF). The same-time standard march tests, which are based on only one run, are becoming insufficient for complex faults like pattern-sensitive faults (PSFs). To increase fault coverage, the multi-run transparent march test algorithms have been used. This solution is especially suitable for built-in self-test (BIST) implementation. The transparent BIST approach presents the incomparable advantage of preserving the content of the random access memory (RAM) after testing. We do not need to save the memory content before the test session or to restore it at the end of the session. Therefore, these techniques are widely used in critical applications (medical electronics, railway control, avionics, telecommunications, etc.) for periodic testing in the field. Unfortunately, in many cases, there is very limited time for such test sessions. Taking into account the above limitations, we focus on short, two-run march test procedures based on counter address sequences. The advantage of this paper is that it defines requirements that must be taken into account in the address sequence selection process and presents a deeply analytical investigation of the optimal address decimation parameter. From the experiments we can conclude that the fault coverage of the test sessions generated according to the described method is higher than in the case of pseudorandom address sequences. Moreover, the benefit of this solution seems to be low hardware overhead in implementation of an address generator.

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Beal, Aubrey N., and Robert N. Dean. "A Random Stimulation Source for Evaluating MEMS Devices using an Exact Solvable Chaotic Oscillator." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (January 1, 2015): 001594–625. http://dx.doi.org/10.4071/2015dpc-wp32.

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MEMS devices are nearly ubiquitous, with applications ranging from automobiles to toys, medical equipment to missiles, and cell phones to industrial equipment. At the microscale, fabrication tolerances are significantly less precise than at the scale of traditional machining techniques. This can result in significant differences in the operating characteristics between otherwise identical MEMS devices. A wide bandwidth random excitation source is ideal for evaluating these components, whether used as the forcing function for an electromechanical shaker employed to measure transmissibility, or as a voltage source to evaluate actuator structure resonances and instabilities. An electronic chaotic oscillator provides an ideal wide bandwidth voltage source which is provably random from first principles and may be simply integrated for the aforementioned MEMS testing. This type of system is easily integrated through standard Si MEMS processes and readily lends itself to application as a built-in-self test (BIST) component. These systems guarantee uniform frequency content from D.C. up to 100kHz due to their characteristically random behavior and serve as a strong candidate for providing uniform spectral density to a device under test. The proposed system is a simple, electronic circuit that creates a random, wideband excitation voltage for observing characteristics of MEMS devices. This functionality is achieved by the analog, digital or mixed signal computation of nonlinear differential equations that describe various exactly solvable chaotic systems. By creating Si microsystems which perform these computations, these test sources may be readily fabricated as integrated BIST components for MEMS devices or fabricated separately and integrated by flip chip assembly techniques. Furthermore, by considering the iterated map of this particular category of stimulation source, a direct and easy measurement of the stimulation entropy may be monitored and corrected. This work begins as a theoretical treatment involving the Nonlinear Dynamics of these types of systems including chaotic systems which permit closed form solutions. These systems are described classically through nonlinear differential equations and intuitively through iterated maps. These techniques reveal inherent methods for entropy measurement in these sources which may be implemented and controlled easily using electronic circuits. Subsequently, the simulation, circuit design methodology, circuit simulation, fabrication, testing and hardware verification of these wideband chaotic sources is presented. The development of this work delineates simple, wideband electronic testing circuits which may be fully integrated with MEMS devices using standard Si MEMS processes. The resulting microsystem may be used as the forcing function when measuring transmissibility of MEMS devices, or as a BIST element to evaluate MEMS microstructure characteristics through direct microelectronic fabrication or flip chip integration.

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Seetharaman, G., B. Venkataramani, and G. Lakshminarayanan. "VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme." VLSI Design 2008 (July 20, 2008): 1–8. http://dx.doi.org/10.1155/2008/512746.

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A novel approach is proposed in this paper for the implementation of 2D DWT using hybrid wave-pipelining (WP). A digital circuit may be operated at a higher frequency by using either pipelining or WP. Pipelining requires additional registers and it results in more area, power dissipation and clock routing complexity. Wave-pipelining does not have any of these disadvantages but requires complex trial and error procedure for tuning the clock period and clock skew between input and output registers. In this paper, a hybrid scheme is proposed to get the benefits of both pipelining and WP techniques. In this paper, two automation schemes are proposed for the implementation of 2D DWT using hybrid WP on both Xilinx, San Jose, CA, USA and Altera FPGAs. In the first scheme, Built-in self-test (BIST) approach is used to choose the clock skew and clock period for I/O registers between the wave-pipelined blocks. In the second approach, an on-chip soft-core processor is used to choose the clock skew and clock period. The results for the hybrid WP are compared with nonpipelined and pipelined approaches. From the implementation results, the hybrid WP scheme requires the same area but faster than the nonpipelined scheme by a factor of 1.25–1.39. The pipelined scheme is faster than the hybrid scheme by a factor of 1.15–1.39 at the cost of an increase in the number of registers by a factor of 1.78–2.73, increase in the number of LEs by a factor of 1.11–1.32 and it increases the clock routing complexity.

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Hantos, Gergely, David Flynn, and Marc P. Y. Desmulliez. "Built-In Self-Test (BIST) Methods for MEMS: A Review." Micromachines 12, no. 1 (December 31, 2020): 40. http://dx.doi.org/10.3390/mi12010040.

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A novel taxonomy of built-in self-test (BIST) methods is presented for the testing of micro-electro-mechanical systems (MEMS). With MEMS testing representing 50% of the total costs of the end product, BIST solutions that are cost-effective, non-intrusive and able to operate non-intrusively during system operation are being actively sought after. After an extensive review of the various testing methods, a classification table is provided that benchmarks such methods according to four performance metrics: ease of implementation, usefulness, test duration and power consumption. The performance table provides also the domain of application of the method that includes field test, power-on test or assembly phase test. Although BIST methods are application dependent, the use of the inherent multi-modal sensing capability of most sensors offers interesting prospects for effective BIST, as well as built-in self-repair (BISR).

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Praneeth, B. V. S. Sai. "Finite State Machine based Programmable Memory Built-in Self-Test." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 30, 2021): 3805–9. http://dx.doi.org/10.22214/ijraset.2021.35875.

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We propose a methodology to design a Finite State Machine(FSM)-based Programmable Memory Built-In Self Test (PMBIST) which includes a planned procedure for Memory BIST which has a controller to select a test algorithm from a fixed set of algorithms that are built in the memory BIST. In general, it is not possible to test all the different memory modules present in System-on-Chip (SoC) with a single Test algorithm. Subsequently it is desirable to have a programmable Memory BIST controller which can execute multiple test algorithms. The proposed Memory BIST controller is designed as a FSM (Finite State Machine) written in Verilog HDL and this scheme greatly simplifies the testing process and it achieves a good flexibility with smaller circuit size compared with Individual Testing designs. We have used March test algorithms like MATS+, March X, March C- to build the project.

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Cai, Zhi Kuang, Kai Huang, Jun Yang, and Long Xing Shi. "Built-In Self-Test Scheme for All-Digital Phase-Locked Loops." Advanced Materials Research 546-547 (July 2012): 922–27. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.922.

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This paper presents a low-cost Built-In Self-Test (BIST) scheme, which is based on the principle of parity check code. The proposed circuit is consisted of a XOR network, a frequency decrease module, a BIST controller and a fault detector module. Different from the previous methods of PLL BIST, digital signals from the divide-by-N are grouped as transmission codes, and parity check codes are produced synchronously by the BIST controller. Then the results of parity checking are imported to the fault detector and final test results are generated. Purely digital design flow is adopted and hybrid faults models are used to evaluate the efficiency of the circuit. Experimental results indicates that the proposed method can provide the highest test coverage and lower area overhead, which are 98.3% and 4.2%, respectively.

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Bakalist, D., X. Kavousianos, H. T. Vergos, D. Nikolos, and G. Ph Alexiou. "Low Power Built-In Self-Test Schemes for Array and Booth Multipliers." VLSI Design 12, no. 3 (January 1, 2001): 431–48. http://dx.doi.org/10.1155/2001/67893.

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Recent trends in IC technology have given rise to a new requirement, that of low power dissipation during testing, that Built-In Self-Test (BIST) structures must target along with the traditional requirements. To this end, by exploiting the inherent properties of Carry Save, Carry Propagate and modified Booth multipliers, in this paper we propose new power-efficient BIST structures for them. The proposed BIST schemes are derived by: (a) properly assigning the Test Pattern Generator (TPG) outputs to the multiplier inputs, (b) modifying the TPG circuits and (c) reducing the test set length. Our results indicate that the total power dissipated during testing can be reduced from 29.3% to 54.9%, while the average power per test vector applied can be reduced from 5.8% to 36.5% and the peak power dissipation can be reduced from 15.5% to 50.2% depending on the implementation of the basic cells and the size of the multiplier. The test application time is also significantly reduced, while the introduced BIST schemes implementation area is small.

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Hong, Sheng, Wen Hui Tao, Yun Ping Qi, Cheng Gao, Xiao Zhang Liu, Jiao Ying Huang, and Dong Zhang. "Built-in Self-Test Design for Fault Detection of MUXFXs in SRAM-Based FPGAs." Applied Mechanics and Materials 39 (November 2010): 220–25. http://dx.doi.org/10.4028/www.scientific.net/amm.39.220.

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This paper proposes a built-in self-test (BIST) design for MUXFXs in SRAM-based FPGAs. This approach can test both the interconnect resources and MUXFXs in the configurable logic blocks (CLBs). Because the test pattern generator (TPG) and output response analyzer (ORA)are configured by existing CLBs in FPGAs, no extra area overhead is needed for the proposed BIST structure. Open/short , stuck on/off faults in PSs, and stuck-at-0/1 faults in MUXFXs will be detected through the target fault detection/diagnosis of the proposed BIST structure.

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36

McCluskey, Edward. "Built-In Self-Test Techniques." IEEE Design & Test of Computers 2, no. 2 (1985): 21–28. http://dx.doi.org/10.1109/mdt.1985.294856.

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Wey, C. L. "Built-in self-test (BIST) structure for analog circuit fault diagnosis." IEEE Transactions on Instrumentation and Measurement 39, no. 3 (June 1990): 517–21. http://dx.doi.org/10.1109/19.106284.

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Wey, C. L. "Alternative built-in self-test (BIST) structures for analogue circuit fault diagnosis." Electronics Letters 27, no. 18 (1991): 1627. http://dx.doi.org/10.1049/el:19911017.

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Chin-Long Wey. "Built-in self-test (BIST) design of high-speed carry-free dividers." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 4, no. 1 (March 1996): 141–45. http://dx.doi.org/10.1109/92.486089.

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40

Mir, S., L. Rufer, and A. Dhayni. "Built-in-self-test techniques for MEMS." Microelectronics Journal 37, no. 12 (December 2006): 1591–97. http://dx.doi.org/10.1016/j.mejo.2006.04.016.

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Lupea, D., U. Pursche, and H. J. Jentschel. "Spectral Signature Analysis – BIST for RF Front-Ends." Advances in Radio Science 1 (May 5, 2003): 155–60. http://dx.doi.org/10.5194/ars-1-155-2003.

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Abstract. In this paper, the Spectral Signature Analysis is presented as a concept for an integrable self-test system (Built-In Self-Test – BIST) for RF front-ends is presented. It is based on modelling the whole RF front-end (transmitter and receiver) on system level, on generating of a Spectral Signature and of evaluating of the Signature Response. Because of using multi-carrier signal as the test signature, the concept is especially useful for tests of linearity and frequency response of front-ends. Due to the presented method of signature response evaluation, this concept can be used for Built-In Self-Correction (BISC) at critical building blocks.

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42

Wey, C. L., and S. Krishman. "Built-in self-test (BIST) structures for analog circuit fault diagnosis with current test data." IEEE Transactions on Instrumentation and Measurement 41, no. 4 (1992): 535–39. http://dx.doi.org/10.1109/19.155921.

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Ahmad, A., and D. Al-Abri. "Design of a Realistic Test Simulator For a Built-In Self Test Environment." Journal of Engineering Research [TJER] 7, no. 2 (December 1, 2010): 69. http://dx.doi.org/10.24200/tjer.vol7iss2pp69-79.

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This paper presents a realistic test approach suitable to Design For Testability (DFT) and Built- In Self Test (BIST) environments. The approach is culminated in the form of a test simulator which is capable of providing a required goal of test for the System Under Test (SUT). The simulator uses the approach of fault diagnostics with fault grading procedure to provide the tests. The tool is developed on a common PC platform and hence no special software is required. Thereby, it is a low cost tool and hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any SUT. The developed tool incorporates a flexible Graphical User Interface (GUI) procedure and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe - reliable - testable digital logic designs.

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Kumar, Mahesh. "An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]." American Journal of Electrical and Computer Engineering 3, no. 1 (2019): 38. http://dx.doi.org/10.11648/j.ajece.20190301.15.

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Chen, Dongliang, Xiaowei Liu, Liang Yin, Yinhang Wang, Zhaohe Shi, and Guorui Zhang. "A ΣΔ Closed-Loop Interface for a MEMS Accelerometer with Digital Built-In Self-Test Function." Micromachines 9, no. 9 (September 6, 2018): 444. http://dx.doi.org/10.3390/mi9090444.

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Sigma-delta (ΣΔ) closed-loop operation is the best candidate for realizing the interface circuit of MEMS accelerometers. However, stability and reliability problems are still the main obstacles hindering its further development for high-end applications. In situ self-testing and calibration is an alternative way to solve these problems in the current process condition, and thus, has received a lot of attention in recent years. However, circuit methods for self-testing of ΣΔ closed-loop accelerometers are rarely reported. In this paper, we propose a fifth-order ΣΔ closed-loop interface for a capacitive MEMS accelerometer. The nonlinearity problem of the system is detailed discussed, the source of it is analyzed, and the solutions are given. Furthermore, a built-in self-test (BIST) unit is integrated on-chip for in situ self-testing of the loop distortion. In BIST mode, a digital electrostatic excitation is generated by an on-chip digital resonator, which is also ΣΔ modulated. By single-bit ΣΔ-modulation, the noise and linearity of excitation is effectively improved, and a higher detection level for distortion is easily achieved, as opposed to the physical excitation generated by the motion of laboratory equipment.

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CHEN, ZE-WANG, JIAN-HUA SU, and YOU-REN WANG. "AN EFFECTIVE TEST ALGORITHM AND DIAGNOSTIC IMPLEMENTATION FOR EMBEDDED STATIC RANDOM ACCESS MEMORIES." Journal of Circuits, Systems and Computers 20, no. 07 (November 2011): 1389–402. http://dx.doi.org/10.1142/s0218126611007931.

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An effective test algorithm and built-in self-test (BIST) with diagnostic support for embedded static random access memories (SRAM) is proposed. This work focuses on implementing the algorithm using the BIST with diagnostic support for a 64 × 8 bit embedded SRAM. The algorithm can locate and identify all the target faults in SRAM. The BIST with diagnostic support is realized by programming using very high speed integrated circuit hardware description language codes and proved very valuable for diagnosing the target faults. When analyzing experimental results, the fault dictionary is constructed from the simulated responses under the given test algorithm and fault models. The fault dictionary shows that the algorithm has a completely diagnostic ratio.

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Zhang, Guohe, Ye Yuan, Feng Liang, Sufen Wei, and Cheng-Fu Yang. "Low Cost Test Pattern Generation in Scan-Based BIST Schemes." Electronics 8, no. 3 (March 12, 2019): 314. http://dx.doi.org/10.3390/electronics8030314.

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This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.

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Tang, Xiao-Bin, and Masayoshi Tachibana. "A BIST Scheme for Bootstrapped Switches." Electronics 10, no. 14 (July 12, 2021): 1661. http://dx.doi.org/10.3390/electronics10141661.

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This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in bootstrapped switches. The clock signal and the gate voltage of the sampling MOS transistor are taken as the observation signals in the proposed BIST scheme. Usually, the gate voltage of the sampling MOS transistor is greater than or equal to the supply voltage when the switch is turn on, and such a voltage is not suitable for observation. To solve this problem, a low power supply voltage is provided for the bootstrapped switch to obtain a suitable observation voltage. The proposed BIST scheme and the circuit under test (CUT) are realized with transistor level. The proposed BIST scheme was simulated by HSPICE. The simulated fault coverage is approximately 87.9% with 66 test circuits.

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Yuan, Jun, and Wei Wang. "A TDC Based BIST Scheme for Operational Amplifier." Applied Mechanics and Materials 644-650 (September 2014): 3583–87. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3583.

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This paper presents a time-to-digital converter (TDC) based built-in self-test (BIST) scheme for operational amplifier (Op Amp). The propagation delay exiting in the transient response of the Op Amp is monitored by the inverter based TDC, and converted into a digital code based on the referenced delay interval of the inverter used in the TDC, as a result, the digital code is finally employed to determine the test rsults. The circuit-level simualtion results of the proposed BIST syetem for a two-stage Op Amp are presented to demonstrated the feasility of the proposed BIST scheme with high fault coverage.

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Chen, Chien-In Henry, and Yingjie Zhou. "Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs." VLSI Design 11, no. 2 (January 1, 2000): 149–59. http://dx.doi.org/10.1155/2000/60904.

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Recently a multiple-sequence test generator was presented based on two-dimensional linear feedback shift registers (2-D LFSR). This generator can generate a set of precomputed test vectors obtained by an ATPG tool for detecting random-pattern-resistant faults and particular hard-to-detect faults. In addition, it can generate better random patterns than a conventional LFSR. In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. Starting from a set of stuck-at faults and a corresponding set of test vectors detecting these faults, the corresponding test pattern generator is determined automatically. A synthesis procedure of designing this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators.

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Journal articles on the topic 'Built-In Self Test (BIST) techniques'

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