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Olbrich, Thomas. "Design-for-Test and Built-In-Self-Test for integrated systems." Thesis, Lancaster University, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.312594.
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XIONG, XINGGUO. "BUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1123038236.
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Jervan, Gert. "Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems." Doctoral thesis, Linköping : Dept. of Computer and Information Science, Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2994.
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Bou, Sleiman Sleiman. "Built-in-Self-Test and Digital Self-Calibration for Radio Frequency Integrated Circuits." The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1311685013.
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Testa, Luca. "Contribution to the Built-In Self-Test for RF VCOs." Thesis, Bordeaux 1, 2010. http://www.theses.fr/2010BOR14011/document.
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Ce travail concerne l'étude et la réalisation de stratégies d'auto-test intégrées pour VCO radiofréquence (RF). La complexité des circuits intégrés RF devient un obstacle pour la mesure des principaux blocs RF des chaines de transmission/réception. Certains nœuds ne sont pas accessibles, l'excursion en tension des signaux baisse et les signaux haute fréquence ne peuvent pas être amenés à l'extérieur de la puce sans une forte dégradation. Le s techniques habituelles de test deviennent très couteuses et lentes. Le test pour le wafer-sort est étudié en premier. La solution proposée est la mise en œuvre d'une stratégie d'auto-test intégrée (BIST) qui puisse discriminer entre circuits sans fautes et circuits avec fautes pendant le wafer-test. La méthodologie utilisée est le test structurel. La couverture des fautes est étudiée pour connaitre la quantité à capter au niveau intégré afin de maximiser la probabilité de trouver tous les défauts physiques dans le VCO. Le résultat de cette analyse montre que la couverture des fautes est maximisée quand la tension crête-crête en sortie du VCO est captée. La caractérisation complète (validation de la puce et process-monitoring) du VCO est étudiée dans la deuxième étape. Les informations à extraire de la puce sont: amplitude des signaux, consommation du VCO, fréquence d'oscillation, gain de conversion (Kvco) et une information à propos du bruit de phase. Un démonstrateur pour le test au niveau wafer est réalisé en technologie ST CMOS 65nm. Le démonstrateur est composé d'un VCO 3.5GHz (le circuit sous test), un LDO, une référence de tension indépendante de température et variations d'alimentation, un capteur de tension crête-crête et un comparateur. Le capteur Vpp donne en sortie une information DC qui est comparée avec une plage de valeurs acceptables. Le BIST donne en sortie une information numérique pass/fail<br>This work deals with the study and the realization of Built-In Self-Tests (BIST) for RF VCOs (Voltage Controlled Oscillators) The increasing complexity of RF integrated circuits is creating an obstacle for the correct measurement of the main RF blocks of any transceiver. Some nodes are not accessible, the voltage excursion of the signals is getting lower and lower and high frequency signals cannot be driven off the die without a main degradation. The common test techniques become then very expensive and time consuming. The wafer sort is firstly approached. The proposed solution is the implementation of a BIST strategy able to discriminate between faulty and good circuits during the wafer test. The chosen methodology is the structural test (fault-oriented). A fault coverage campaign is carried out in order to find the quantity to monitor on-chip that maximizes the probability to find all possible physical defects in the VCO. The result of the analysis reveals that the fault coverage is maximized if the peak-to-peak output voltage is monitored. The complete on-chip characterization of the VCO is then addressed, for chip validation and process monitoring. The information that need to be extracted on-chip concern: amplitude of the signal, consumption of the VCO, frequency of oscillation, its conversion gain (voltage-to-frequency) and eventually some information on the phase noise. A silicon demonstrator for wafer sort purposes is implemented using the ST CMOS 65nm process. It includes a 3.5GHz VCO, an LDO, a temperature and supply-voltage independent voltage reference, a peak-to-peak voltage detector and a comparator. The Vpp detector outputs a DC-voltage that is compared to a predefined acceptance boundary. A logic pass/fail signal is output by the BIST. The attention is then turned to the study of the proposed architecture for an on-chip frequency-meter able to measure the RF frequency with high accuracy. Behavioral simulations using VHDL-AMS lead to the conclusion that a TDC (Time-to-Digital Converter) is the best solution for our goal. The road is then opened to the measure of long-time jitter making use of the same TDC
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Cilici, Florent. "Développement de solutions BIST (Built-In Self-Test) pour circuits intégrés radiofréquences/millimétriques." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT072.
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Les technologies silicium récentes sont particulièrement prônes aux imperfections durant la fabrication des circuits. La variation des procédés peut entrainer une dégradation des performances, notamment aux hautes fréquences. Dans cette thèse, plusieurs contributions visant la réduction des coûts et de la complexité du test des circuits millimétriques sont présentées. Dans ce sens, deux sujets principaux ont fait l'objet de notre attention : a) le test indirect non-intrusif basé sur l’apprentissage automatique et b) la calibration non-itérative "one-shot". Nous avons en particulier développé une méthode générique pour implémenter un test indirect non-intrusif basé sur l’apprentissage automatique. La méthode vise à être aussi automatisée que possible de façon à pouvoir être appliquée à pratiquement n'importe quel circuit millimétrique. Elle exploite les modèles Monte Carlo du design kit et des informations de variations du BEOL pour proposer un jeu de capteurs non-intrusifs. Des mesures à basses fréquences permettent ensuite d'extraire des signatures qui contiennent des données pertinentes concernant la qualité des procédés de fabrication, et donc a fortiori de la performance du circuit. Cette méthode est supportée par des résultats expérimentaux sur des PAs fonctionnant à 65 GHz, conçus dans une technologie 55 nm de STMicroelectronics. Pour s'attaquer plus encore à la dégradation des performances induite par les variations des procédés de fabrication, nous nous sommes également penchés sur une procédure de calibration non-itérative. Nous avons ainsi présenté un PA à deux étages qui peut être calibré en post-fabrication. La méthode de calibration exploite une cellule de découplage variable comme moyen de modifier les performances de l'amplificateur. Des moniteurs de variations des procédés de fabrication, placés dans les espaces vides du circuit, sont utilisés afin de prédire la meilleure configuration possible pour les cellules de découplage variables. La faisabilité et les performances de cette approche ont été validés en simulation<br>Recent silicon technologies are especially prone to imperfections during the fabrication of the circuits. Process variations can induce a noticeable performance shift, especially for high frequency devices. In this thesis we present several contributions to tackle the cost and complexity associated with testing mm-wave ICs. In this sense, we have focused on two main topics: a) non-intrusive machine learning indirect test and b) one-shot calibration. We have in particular developed a generic method to implement a non-intrusive machine learning indirect test based on process variation sensors. The method is aimed at being as automated as possible and can be applied to virtually any mm-wave circuit. It leverages the Monte Carlo models of the design kit and the BEOL variability information to propose a set of non-intrusive sensors. Low frequency measurements can be performed on these sensors to extract signatures that provide relevant information about the process quality, and consequently about the device performance. The method is supported by experimental results in a set of 65 GHz PAs designed in a 55 nm technology from STMicroelectronics. To further tackle the performance degradation induced by process variations, we have also focused on the implementation of a one-shot calibration procedure. In this line, we have presented a two-stage 60 GHz PA with one-shot calibration capability. The proposed calibration takes advantage of a novel tuning knob, implemented as a variable decoupling cell. Non-intrusive process monitors, placed within the empty spaces of the circuit, are used for predicting the best tuning knob configuration based on a machine learning regression model. The feasibility and performance of the proposed calibration strategy have been validated in simulation
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Venkatasubramanian, Radhika. "High frequency continuous-time circuits and built-in-self-test using CMOS RMS detector." Texas A&M University, 2005. http://hdl.handle.net/1969.1/4746.
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The expanding wireless market has resulted in complex integrated transceivers
that involve RF, analog and mixed-signal circuits, resulting in expensive and complicated
testing. The most important challenges that test engineering faces today are (1) providing
a fast and accurate fault-diagnosis and performance characterization so as to accelerate
the time-to-market and (2) providing an inexpensive test strategy that can be integrated
with the design so as to aid the high-volume manufacturing process. The first part of the
research focuses on the design of an RMS detector for built-in-self-test (BIST) of an RF
integrated transceiver that can directly provide information at various test points in the
design. A cascode low noise amplifier (LNA) has been chosen as the device under test
(DUT). A compact (< 0.031 mm2) RF RMS detector with negligible input capacitance (<
13 fF) has been implemented in 0.35 õm CMOS technology along with the DUT.
Experimental results are currently being assimilated and compared with the simulation
results. Frequency limitations were encountered during the testing process due to
unexpected increase in the value of the N-well resistors. All other problems faced during
the testing, as well as the results obtained so far, are presented in this thesis. In the second part of the research, the use of the RMS detector for BIST has been
extended to a continuous-time high-frequency boost-filter. The proposed HF RMS
detector has been implemented along with a 24 dB 350 MHz boost filter as the DUT on
0.35 õm CMOS technology. The HF RMS detector occupies 0.07 mm2 and has an input
capacitance of 7 fF. The HF RMS detector has a dynamic range greater than 24 dB
starting from -38 dBm of input power. The bandwidth and boost of the filter have been
accurately estimated in simulation using the HF RMS detector. The sensitivity of an
intermediate band pass node of the filter has also been monitored to predict the filter's
sensitivity to Q errors.
The final part of the research describes the design of a single-ended to differential
converter for use in a broadband transceiver operating from 50-850 MHz. This circuit is
used as the second stage in the transceiver after the LNA. The design has been simulated
on a 0.35 um CMOS process and has a power consumption of 13.5 mW and less than 8
dB of noise figure over the entire band. It is capable of driving a 500fF load with less
than 1dB of gain ripple over the entire band (50-850 MHz).
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Allott, Stephen. "The development and implementation of automatic test techniques for Analogue to Digital Converter characterization using a deterministic approach." Thesis, University of Huddersfield, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.385712.
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Poling, Brian. "On-Chip Signal Generation and Response Waveform Extraction for Analog Built-In-Self-Test." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1190050023.
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Dogaru, Emanuel. "Built-In Self-Test of Flexible RF Transmitters Using Nonuniform Undersampling." Thesis, CentraleSupélec, 2015. http://www.theses.fr/2015SUPL0004/document.
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Le secteur de communications sécurisés et portables connait une véritable révolution avec l’apparition des plateformes dites radios logiciels (Software Defined Radios, SDRs). Les performances exceptionnelles de ces systèmes sont les résultats d’une interaction assez complexe et souvent peu évidente entre le logiciel embarqué, le circuit de traitement numérique et les blocs mixtes analogiques/RF. Cette complexité limite la testabilité du produit fini. La méthodologie de test utilisée actuellement a atteint ses limites dues au cout élevé, le long temps de test et le bas degré de généralisation. De plus, les plateformes SDRs peuvent évoluer sur le terrain et elles vont supporter des standards et des scénarios qui n’ont pas été considérés pendant le la phase de conception. Donc, une stratégie de test sur le terrain (en ligne) n’est plus une caractéristique optionnelle mais une nécessité. Dans ce contexte, le but de notre recherche est d’inventer et développer une méthodologie de test capable de garantir le bon fonctionnement d’une plateforme SDR après la production et pendant sa vie. Notre objectif final est de réduire le coût du test en profitant de la reconfigurabilité de la plateforme. Pour les radios tactiques qui doivent être mises à jour sur le terrain sans équipement spécial, les stratégies Built-In Self-Test (BIST) sont, sans doute, la seule moyenne de garantir la conformité aux spécifications. Dans cette mémoire, nous introduisons une nouvelle architecture de test RF BIST qui utilise la technique de de sous-échantillonnage nonuniform à la sortie de l’émetteur (TX) d’une SDR afin d’évaluer la conformité de la masque spectrale. Notre solution s’appuie sur une implémentation autonome, est modulable et peut être appliquée pour le test sur le terrain avec des modifications minimes. Par rapport aux autres techniques de test analogiques/RF, cet approche ne dépends pas de la architecture du TX, ni d’un modèle ad-hoc, ce qui est idéale pour le test des SDRs<br>The advent of increasingly powerful Integrated Circuits (IC) has led to the emergence of the Software Defined Radio (SDR) concept, which brought the sector of secured mobile communications into a new era. The outstanding performance of these systems results from optimal trade-offs among advanced analog/Radio Frequency (RF) circuitry, high-speed reconfigurable digital hardware and sophisticated real-time software. The inherent sophistication of such platforms poses a challenging problem for product testing. Currently deployed industrial test strategies face rising obstacles due to the costlier RF test equipment, longer test time and lack of flexibility. Moreover, an SDR platform is field-upgradeable, which means it will support standards and scenarii not considered during the design phase. Therefore, an in-field test strategy is not anymore 'a nice to have' feature but a mandatory requirement. In this context, our research aims to invent and develop a new test methodology able to guarantee the correct functioning of the SDR platform post-fabrication and over its operational lifetime. The overall aim of our efforts is to reduce post-manufacture test cost of SDR transceivers by leveraging the reconfigurability of the platform.For tactical radio units that must be field-upgradeable without specialized equipment, Built-in Self-Test (BIST) schemes are arguably the only way to ensure continued compliance to specifications. In this study we introduce a novel RF BIST architecture which uses Periodically Nonuniform Sampling (PNS2) of the transmitter (TX) output to evaluate compliance to spectral mask specifications. Our solution supports a stand-alone implementation, is scalable across a wide set of complex specifications and can be easily applied for in-field testing with small added hardware. Compared to existing analog/RF test techniques, this approach is not limited to a given TX architecture and does not rely on an ad-hoc TX model, which makes it ideal for SDR testing
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Yan, Wenjian. "A wideband frequency synthesizer for built-in self testing of analog integrated circuits." Texas A&M University, 2004. http://hdl.handle.net/1969.1/1059.
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The cost to test chips has risen tremendously. Additionally, the process for testing all functionalities of both analog and digital part is far from simple. One attractive option is moving some or all of the testing functions onto the chip itself leading to the use of built-in self-tests (BISTs). The frequency generator or frequency synthesizer is a key element of the BIST. It generates the clock frequencies needed for testing.
A wide-band frequency synthesizer is designed in the project. The architecture of a PLL is analyzed as well as the modifications carried out. The modified structure has three blocks: basic PLL based frequency synthesizer, frequency down-converter, and output selector. Each of these blocks is analyzed and designed. This frequency synthesizer system overcomes challenges faced by the traditional PLL based frequency synthesizer.
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Liang, Huaguo [Verfasser]. "A New Technique for Deterministic Scan-Based Built-In Self-Test (BIST) / Huaguo Liang." Aachen : Shaker, 2003. http://d-nb.info/1174513713/34.
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Han, Dong-Hoon. "Built-In Self Test and Calibration of RF Systems for Parametric Failures." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/14507.
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This thesis proposes a multifaceted production test and post-silicon yield enhancement framework for RF systems. The three main components of the proposed framework are the design, production test, and post-test phase of the overall integrated circuit (IC) development cycle. First, a circuit-sizing method is presented for incorporating test considerations into algorithms for automatic circuit synthesis/device resizing. The sizing problem is solved by using a cost metric that can be incorporated at minimal computational cost into existing optimization tools for manufacturing yield enhancement. Along with the circuit-sizing method introduced in the design phase, a low-cost test and diagnosis method is presented for multi-parametric faults in wireless systems. This test and diagnosis method allows accurate prediction of the end-to-end specifications as well as for the specifications of all the embedded modules. The procedure is based on application of optimized test stimulus and the use of a simple diode-based envelope detector to extract the transient test response envelope at RF signal nodes. This eliminates the need to make RF measurements using expensive standard testers. To further improve the parametric yield of RF circuits, a performance drift-aware adaptation scheme is proposed that automatically compensates for the loss of circuit performance in the presence of process variations. This work includes a diagnosis algorithm to identify faulty circuits within the system and a compensation process that adjusts tunable components to reduce the effects of performance variations. As a result, all the mentioned components contribute to producing a low-cost production test and to enhancing post-silicon parametric yield.
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Rolindez, Luis. "Technique d’auto test pour des convertisseurs de signal Sigma-Delta." Grenoble INPG, 2007. http://www.theses.fr/2007INPG0020.
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Le test de circuits analogiques et mixtes est de plus en plus coûteux, représentant parfois jusqu’à 50% du coût total de fabrication du circuit. Les techniques de BIST (Built-In Self-Test) permettent de réduire ce coût en intégrant sur la puce les ressources nécessaires au test. Dans cette thèse, nous présentons une nouvelle technique de BIST pour les Convertisseurs Analogiques-Numériques Sigma-Delta (CAN). Cette approche combine un surcoût en surface et un temps de test très réduits. Puisque les circuits numériques sont de plus en plus petits, nous avons choisi une technique principalement numérique, ce qui est en phase avec la philosophie des convertisseurs Sigma-Delta. Comme signal de test nous utilisons un stimulus numérique qui codifie avec une grande précision un signal sinusoïdal. Le même stimulus binaire est employé pour l’analyse de la réponse, effectuée au moyen d’une régression sinusoïdale (sine-wave fitting algorithm). La réutilisation de ressources présentes dans le circuit permet de calculer le SINAD (Signal-to-Noise And Distortion ratio) du convertisseur de manière très efficace. Afin de valider cette technique, un prototype a été conçu et fabriqué dans une technologie CMOS 0. 13 µm de STMicroelectronics. Les résultats expérimentaux confirment la capacité de notre technique à mesurer le SINAD dans un convertisseur audio de 16 bits<br>The test of analogue and mixed-signal circuits is becoming very costly, sometimes taking up to 50% of the total product cost. Built-In Self-Techniques (BIST) have the potential to reduce these costs, moving most of the test complexity to the design domain and making the circuit auto-testable. In this thesis, we present a new BIST technique for Sigma-Delta Analogue-to-Digital Converters (ADC). This approach exhibits both a very low area overhead and a short test time. Considering the continuous downscaling of digital circuits, we propose a strategy mainly digital, which is in-line with the philosophy of Sigma-Delta converters. As test signal, we generate on-chip a binary stimulus which encodes a very-high precision sinusoidal signal. The same binary stimulus is used for the response analysis, performed on-chip by means of a sine-wave fitting algorithm. The reuse of the resources already present in the circuit allow us to calculate the converter SINAD (SIgnal-to-Noise And Distortion ratio) in a very efficient way. As result of this work, a prototype has been designed and fabricated in a 0. 13 µm CMOS technology from STMicroelectronics. The experimental results confirm the capacity of the BIST technique to measure the SINAD in a 16-bit audio Sigma Delta Converter
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Kim, Han Bin. "High-Level Synthesis and Implementation of Built-In Self-Testable Data Path Intensive Circuit." Diss., Virginia Tech, 1999. http://hdl.handle.net/10919/30257.
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A high-level built-in self-test (BIST) synthesis is a process of transforming a behavioral description into a register-transfer level structural description while minimizing BIST overhead. Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of a large design space, which may result in a local optimum.
In this thesis, we present three methods, which aim to address the problem. The first method tries to find a register assignment for each k-test session in a heuristic manner, where k=1,2,â ¦,N and N is the number of modules of the circuit. Therefore, it offers a range of designs with different figures of merit in area and test time. The second method is based on integer linear programming (ILP). The proposed ILP based method performs the three tasks, assignments of registers, interconnections, and BIST registers, concurrently to yield optimal or near-optimal designs. We describe a complete set of ILP formulations for the three tasks. The ILP based method achieves optimal solutions for most circuits in hardware overhead, but it takes long processing time. The third method, the region-wise heuristic method. It partitions a given data flow graph into smaller regions based on control steps and applies the ILP to each region successively to reduce the processing time.
To measure the performance of BIST accurately and to demonstrate the practicality of our BIST synthesis method, we implemented a DSP circuit; an 8x8 two-dimensional discrete cosine transform (DCT) processor. We implemented two versions of the algorithm, one with incorporation of our BIST method and the other without BIST, to verify the validity of our simplified cost model to estimate BIST area overhead. The two major parts of the circuit, data path and controller, were synthesized using our high-level BIST synthesis tool. All the circuits are implemented and laid out using an ASIC design flow developed at Virginia Tech.
Experimental results show that the three proposed high-level BIST synthesis methods perform better than or comparable to existing BIST synthesis systems. They indeed yield various designs that enable users to trade between area overhead and test time. The region-wise heuristic method reduces the processing time by several orders of magnitude, while the quality of the solution is slightly compromised compared with the ILP-based optimal method. The implementation of DCT circuits demonstrate that our method is applicable to industry size circuits, and the BIST area overhead measured at the layout is close to the estimated one.<br>Ph. D.
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El, Kassir Bilal. "Contribution à la conception et à l'évaluation de circuits BIST pour application RF intégrées." Limoges, 2011. http://www.theses.fr/2011LIMO4064.
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Dans cette thèse, des solutions de DFT (Design For Test) et de BIST (Built In Self Test) pour différentes applications RF ont été étudiées. L'analyse et la comparaison de ces différentes solutions à l'ordre de performances des tests, de la complexité des circuits utilisés et le facteur d'intégration ont guidé la direction de l'étude et de la conception de cette contribution. Des circuits BIST utilisant des détecteurs MOS et Bipolaires ont été conçus pour les applications suivantes : mesure de l'EVM en utilisant un DSP (approche de conception); mesure des paramètres de LNA sur la puce (gain IP3, IMx, etc. . . ); un étalonnage des oscillateurs intégrés (VCO à PLL). Pour la mesure de l'EVM, l'utilisation de la technique BIST proposée, a démontré une réduction de la durée du test (par un facteur 1000) ainsi qu'une mise en oeuvre facile. Les limites observées de cette technique sont liées aux défis de mesure EVM BIST en raison de l'existence d'une zone aveugle pour la détection efficace. En ce qui concerne l'application de LNA, les solutions proposées ont démontré un temps de test relativement faible (estimé de - 20 %), un faible coût et une facilité de mise en oeuvre de la procédure de test. La conception de la solution BIST pour la caractérisation de circuit LNA a été développée sur la base d'une implémentation sur puce. Les principales limitations concernent la nécessité d'une surface supplémentaire de silicium, ce qui augmente la consommation et les couplages parasites. L'application de solutions BIST pour commander les oscillateurs intégrés a des avantages liés à la stabilisation de la performance de bruit indépendamment de la variation de processus, de puissance et de température. Toutefois, ces solutions de contrôle induisent une augmentation de la consommation globale du circuit et une dégradation jusqu'à 4 dBc/Hz de bruit de phase donc une dégradation de la qualité du spectre de signal critique (VCO, PLL)<br>In this thesis, a review of DFT (Design For Test) and BIST (Built In Self Test) solutions for different RF applications was studied. The analysis and comparison of these different solutions in terms of their RF performances and testing time has been conducted. The complexity reduction of the used circuits together with the integration factor has been considered as strong enablers for the proposed contribution. BIST circuits using MOS and Bipolar detectors were designed for the following applications : measurement of the EVM through an implementation of DSP type (design approach); On-Chip measurement of the LNA parameters (gain, IP3, IMx, etc. . . ); a calibration of integrated oscillators (VCOs in PLLs). For the EVM measurement, the use of proposed BIST techniques demonstrated a reduction of test time (by a factor 1000) accompanied with an easy implementation. Main limitations observed with this technique are related to challenges relative to EVM BIST measurement due to the existence of a blind zone which hampers effective detection. In the context of WLAN applications, proposed LNA BIST solutions have demonstrated a relatively reduced test time (estimated 20 % improvement), low cost and ease of implementation of the test procedure. The design of the BIST solution for the characterization of LNA circuit has been developed based on an implementation of sensoring system with relatively low on-chip area occupation and current consumption. Perceveid limitations concern the need for additional integration of silicon area, increasing consumption and interferences/couplings. The application of BIST solutions for controlling integrated oscillators has interesting advantages related to the stabilization of noise performance regardless of processes, power and temperature variations. However, these control solutions induce an increase in overall consumption of the circuit which can reach a value of 4 dBc/Hz (add frequency) in Phase noise degradation leading to reduction in the spectral quality of signals in critical blocks such as VCOs/PLLs. Perspectives are drawn to mitigate the identified limiting factors
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Abdallah, Louay. "Capteurs embarqués non-intrusifs pour le test des circuits RF." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-01062479.
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Cette thèse vise l'étude de techniques de type BIST pour un front-end RF, considérant des nouveaux types des capteurs intégrés très simples pour l'extraction de signaux. Ces signaux et les stimuli de test associés seront par la suite traités par des algorithmes de l'apprentissage automatique qui devront permettre une prédiction des performances des différents blocs du système. Une évaluation des capteur proposés en tant que métriques de test paramétrique et couverture des fautes catastrophique sera nécessaire pour pouvoir aboutir à des techniques de test à bas coût pour le test de production, permettant une réduction importante du coût de revient des produits.
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Cowhig, Patrick Carpenter. "A Complete & Practical Approach to Ensure the Legality of a Signal Transmitted by a Cognitive Radio." Thesis, Virginia Tech, 2006. http://hdl.handle.net/10919/34969.
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The computational power and algorithms needed to create a cognitive radio are quickly becoming available. There are many advantages to having a radio operated by cognitive engine, and so cognitive radios are likely to become very popular in the future. One of the main difficulties associated with the cognitive radio is ensuring the signal transmitted will follow all FCC rules. The work presented in this thesis provides a methodology to guarantee that all signals will be legal and valid. The first part to achieving this is a practical and easy to use software testing program based on the tabu search algorithm that tests the software off-line. The primary purpose of the software testing program is to find most of the errors, specially structural errors, while the radio is
not in use so that it does not affect the performance of the system. The software testing
program does not provide a complete assurance that no errors exist, so to supplement this deficit, a built-in self-test (BIST) is employed. The BIST is designed with two parts, one that is embedded into the cognitive engine and one that is placed into the radio's API.
These two systems ensure that all signals transmitted by the cognitive radio will follow
FCC rules while consuming a minimal amount of computational power. The software testing approach based on the tabu search is shown to be a viable method to test software with improved results over previous methods. Also, the software BIST demonstrated its ability to find errors in the signal production and is dem to only require an insignificant amount of computational power. Overall, the methods presented in this paper provide a complete and practical approach to assure the FCC of the legality of all signals in order to obtain a license for the product.<br>Master of Science
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Gadde, Priyanka. "A BIST Architecture for Testing LUTs in a Virtex-4 FPGA." University of Toledo / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199.
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Rehman, Saif Ur. "Développement des techniques de test et de diagnostic pour les FPGA hiérarchique de type mesh." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT110/document.
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L’évolution tendant à réduire la taille et augmenter la complexité des circuits électroniques modernes, est en train de ralentir du fait des limitations technologiques, qui génèrent beaucoup de d’imperfections et de defaults durant la fabrication ou la durée de vie de la puce. Les FPGAs sont utilisés dans les systèmes numériques complexes, essentiellement parce qu’ils sont reconfigurables et rapide à commercialiser. Pour garder une grande fiabilité de tels systèmes, les FPGAs doivent être testés minutieusement pour les defaults. L’optimisation de l’architecture des FPGAs pour l’économie de surface et une meilleure routabilité est un processus continue qui impacte directement la testabilité globale et de ce fait, la fiabilité. Cette thèse présente une stratégie complète pour le test et le diagnostique des defaults de fabrication des “mesh-based FPGA” contenant une nouvelle topologie d’interconnections à plusieurs niveaux, ce qui promet d’apporter une meilleure routabilité. Efficacité des schémas proposes est analysée en termes de temps de test, couverture de faute et résolution de diagnostique<br>The evolution trend of shrinking feature size and increasing complexity in modern electronics is being slowed down due to physical limits that generate numerous imperfections and defects during fabrication steps or projected life time of the chip. Field Programmable Gate Arrays (FPGAs) are used in complex digital systems mainly due to their reconfigurability and shorter time-to-market. To maintain a high reliability of such systems, FPGAs should be tested thoroughly for defects. FPGA architecture optimization for area saving and better signal routability is an ongoing process which directly impacts the overall FPGA testability, hence the reliability. This thesis presents a complete strategy for test and diagnosis of manufacturing defects in mesh-based FPGAs containing a novel multilevel interconnects topology which promises to provide better area and routability. Efficiency of the proposed test schemes is analyzed in terms of test cost, respective fault coverage and diagnostic resolution
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Kakade, Jayawant Shridhar. "METHODS TO MINIMIZE LINEAR DEPENDENCIES IN TWO-DIMENSIONAL SCAN DESIGNS." OpenSIUC, 2008. https://opensiuc.lib.siu.edu/dissertations/256.
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Two-dimensional scan design is an effective BIST architecture that uses multiple scan chains in parallel to test the Circuit Under Test (CUT). Linear Finite State Machines (LFSMs) are often used as on-board Pseudo Random Pattern Generators (PRPGs) in two-dimensional scan designs. However, linear dependencies present in the LFSM generated test-bit sequences adversely affect the resultant fault coverage in two-dimensional scan designs. In this work, we present methods that improve the resultant fault coverage in two-dimensional scan designs through the minimization of linear dependencies. Currently, metric of channel separation and matrix-based metric are used in order to estimate linear dependencies in a CUT. When the underlying sub-circuit (cone) structure of a CUT is available, the matrix-based metric can be used more effectively. Fisrt, we present two methods that use matrix-based metric and minimize the overall linear dependencies in a CUT through explicitly minimizing linear dependencies in the highest number of underlying cones of the CUT. The first method minimizes linear dependencies in a CUT through the selection of an appropriate LFSM structure. On the other hand, the second method synthesizes a phase shifter for a specified LFSM structure such that the overall linear dependencies in a CUT are minimized. However, the underlying structure of a CUT is not always available and in such cases the metric of channel separation can be used more effectively. The metric of channel separation is an empirical measure of linear dependencies and an ad-hoc large channel separation is imposed between the successive scan chains of a two-dimensional scan design in order to minimize the linear dependencies. Present techniques use LFSMs with additional phase shifters (LFSM/PS) as PRPGs in order to obtain desired levels of channel separation. We demonstrate that Generalized LFSRs (GLFSRs) are a better choice as PRPGs compared to LFSM/PS and obtain desired levels of channel separations at a lower hardware cost than the LFSM/PS. Experimental results corroborate the effectiveness of the proposed methods through increased levels of the resultant fault coverage in two-dimensional scan designs.
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Akour, Amneh M. "Design Techniques for Manufacturable 60GHz CMOS LNAs." The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1306443049.
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Dubois, Matthieu. "Méthodologie d'estimation des métriques de test appliquée à une nouvelle technique de BIST de convertisseur SIGMA / DELTA." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00633056.
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L'expansion du marché des semi-conducteurs dans tous les secteurs d'activité résulte de la capacité de créer de nouvelles applications grâce à l'intégration de plus en plus de fonctionnalités sur une surface de plus en plus faible. Pour chaque entreprise, la compétitivité dépend du coût de fabrication mais aussi de la fiabilité du produit. Ainsi, la phase de test d'un circuit intégré, et plus particulièrement des circuits analogiques et mixtes, est le facteur prédominant dans les choix d'un compromis entre ces deux critères antagonistes, car son coût est désormais proche du coût de production. Cette tendance contraint les acteurs du marché à mettre en place de nouvelles solutions moins onéreuses. Parmi les recherches dans ce domaine, la conception en vue du test (DfT) consiste à intégrer pendant le développement de la puce, une circuiterie additionnelle susceptible d'en faciliter le test, voire d'effectuer un auto-test (BIST). Mais la sélection d'une de ces techniques nécessite une évaluation de leur capacité de différencier les circuits fonctionnels des circuits défaillants. Ces travaux de recherche introduisent une méthodologie d'estimation de la qualité d'une DfT ou d'un BIST dans le flot de conception de circuits analogiques et mixtes. Basée sur la génération d'un large échantillon prenant en compte l'impact des variations d'un procédé technologique sur les performances et les mesures de test du circuit, cette méthodologie calcule les métriques de test exprimant la capacité de chaque technique de détecter les circuits défaillants sans rejeter des circuits fonctionnels et d'accepter les circuits fonctionnels en rejetant les circuits défaillant. Ensuite, le fonctionnement d'un auto-test numérique adapté aux convertisseurs sigma-delta est présenté ainsi qu'une nouvelle méthode de génération et d'injection du stimulus de test. La qualité de ces techniques d'auto-test est démontrée en utilisant la méthodologie d'estimation des métriques de test. Enfin, un démonstrateur développé sur un circuit programmable démontre la possibilité d'employer une technique d'auto-test dans un système de calibrage intégré.
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Zhang, Shujian. "Evaluation in built-in self-test." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ34293.pdf.
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Akbay, Selim Sermet. "Constraint-driven RF test stimulus generation and built-in test." Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/33913.
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With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control.
RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs.
In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead.
Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows:
Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time.
Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test.
Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.
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Bogue, Tracey M. "Aliasing reduction in built-in self-test." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/nq21280.pdf.
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Dhawan, Sanjay. "A built-in self-test PLA generator." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-08042009-040315/.
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Muradali, Fidel. "A self-driven test methodology for built-in self-test of sequential circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ30348.pdf.
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Muradali, Fidel. "A self-driven test methodology for built-in self-test of sequential circuits /." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=42106.
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Test cost comprises a substantial portion of producing an integrated circuit. As a result, structural modifications of the circuit via design for test (DFT) techniques are commonly used as an aid to reduce test cost to the lowest possible level. One important class of DFT is Built-In Self-Test (BIST). In BIST, test generation and response analysis logic is integrated into the original circuit and are transparent during normal operation. In this manner, in-circuit tests can be performed with minimal need of external test equipment, if any.<br>Test strategies based on pseudorandom test stimuli are attractive since the simplicity of the pattern generation logic facilitates on-chip test application. Unfortunately, until now, these methods have been more appropriate for testing combinational rather than sequential circuits. This is largely because, unlike combinational testing, detection of sequential faults can require specific orderings of circuit operations which are prohibitively difficult to produce using a pseudorandom source.<br>This thesis introduces a new DFT technique which permits at-speed on-chip sequential testing using parallel pseudorandom test patterns applied only to the primary inputs of the circuit under test. Test network design focuses on adjusting fault free circuit activity and aiding error propagation. This is done via the strategic insertion of a small number of low area test points. The resulting system is unique in that aside from a test mode flag, all I/O signals needed for test system operation are tapped from within the circuit itself. This feature virtually eliminates the control signal generation logic typically needed in other test point strategies. Also, as opposed to the conventional approach of restricting circuit alterations to the state elements, the proposed flexibility in choosing modification sites is beneficial when considering speed constrained designs.<br>Experiments demonstrate that high single stuck-at fault coverage is achieved for a number of benchmark circuits.
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Khalaf, Arkan. "A self-reconfigurable platform for built-in-self-test applications." Thesis, University of Ottawa (Canada), 2007. http://hdl.handle.net/10393/27865.
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This thesis introduces a novel architecture of a run-time reconfigurable microsystem on chip (SoC). This system consists of a logic block that can be reconfigured at run time, and an embedded multi-microprocessor system that connects to this logic block and can reconfigure it at run time using special resources of Field Programmable Gate Arrays (FPGA). A design flow for run-time reconfigurable logic circuits has been developed and is presented in the context of the implementation of the SoC on a FPGA.
This reconfigurable architecture is validated by an application that implements the novel idea of verifying algorithms for testing digital circuits by using run-time reconfigurable techniques, in order to minimize circuit area, as well as test generation and application time. The idea revolves around the dynamic partial reconfiguration of circuits under test, in order to inject stuck-at faults at different locations of the circuit, to verify for and uncover logic structural faults.
The thesis presents the design and implementation of a self-reconfigurable platform, where faults are injected at run-time to the circuit under test. It analyzes the ways of injecting faults and the run-time reconfiguration overhead associated with it, while the rest of the circuit is present on the reconfigurable architecture, in order to validate run-time reconfigurable built-in-self-test techniques, as compared to the more traditional methods.
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Radecka, Katarzyna. "Arithmetical built-in self test for DSP architectures." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ29624.pdf.
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Ho, Thanh Huong. "Test compaction technique for built-in self-test in VLSI circuits." Thesis, University of Ottawa (Canada), 1994. http://hdl.handle.net/10393/6460.
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In recent years, many test output data compression techniques have been introduced, which reduce the storage requirements of reference signatures for the circuit under test. A major problem, however, is that the compression always results in loss of error coverage. This work proposes a space compression technique for digital circuits with the objective of minimizing the storage for the circuits under test while maintaining the fault coverage information. The technique introduced is called a Modified Dynamic Space Compression method. For a circuit under test, a compaction tree is generated based on its structure. The detectable error probability was calculated by using the Boolean Difference Method. The output data modification was employed to minimize the number of faulty output data patterns which have the same compressed form as the fault free patterns. The compressed outputs were then fed into a syndrome counter to derive the signature for the circuit. A design program is written in C language and executed on PC which combines the space compression, output data modification, and faults testing. Simulations were performed on known combinational circuits and the results indicate that the loss in fault coverage caused by compression is rather small.
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Gopalan, Anand. "Built-in-self-test of RF front-end circuitry /." Link to online version, 2005. https://ritdml.rit.edu/dspace/handle/1850/942.
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El-Mahlawy, Mohamed Hassan Mohamed. "Pseudo-exhaustive built-in self-test for boundary scan." Thesis, University of Kent, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.324714.
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Gaur, Manoj Singh. "Integration of built in self test during behavioural synthesis." Thesis, University of Southampton, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.427421.
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Garrison, Brooks Stroud Charles E. "Analysis and improvement of Virtex-4 block RAM Built-In Self-Test and introduction to Virtex-5 block RAM Built-In Self-Test." Auburn, Ala, 2009. http://hdl.handle.net/10415/1667.
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Jervan, Gert. "High-Level Test Generation and Built-In Self-Test Techniques for Digital Systems." Licentiate thesis, Linköping : Univ, 2002. http://www.ep.liu.se/lic/science_technology/09/73/index.html.
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Boutobza, Slimane. "Outils de génération de structures BIST/BISR pour mémoires." Grenoble INPG, 2002. http://www.theses.fr/2002INPG0166.
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Les Systems on Chip (SoC) actuels intègrent en général une grande proportion de mémoires enterrées. Ces mémoires sont de plus en plus denses et occupent des surfaces très importantes dans le circuit (jusqu'à 80%). Ces mémoires peuvent présenter un grand taux de défauts affectant ainsi d'une façon conséquente le rendement total du circuit. La qualité de la mémoire et donc cruciale pour la qualité de l'ensemble du circuit. D'autre part, la réduction du coût du développement passe par la réduction du coût du test. Enfin, le management de la complexité de test des structures de plus en plus complexes (e. G. , il existe actuellement des SoC contenant plus de 400 mémoires enterrées !), ne peut se faire d'une manière efficace sans la disposition et l'intégration des techniques de test les plus avancées. La clé du succès d'une bonne stratégie de test passe par les exigences d'une qualité élevée du test et de son automatisation. À travers la première partie des travaux réalisés dans cette thèse, nous avons tenté de répondre à l'exigence de la qualité de test en présentant un ensemble assez diversifié de solutions de test intégré (BIST) pour mémoires. Ces solutions couvrent les différents types de test d'une mémoire: test de caractérisation et de débuggage des processus de fabrication instables, test de production, test durant la phase opérationnelle et test d'analyse des défauts. Ces solutions permettent de palier aux limitations des techniques BIST existantes, telles que le meilleur compromis couverture de fautes/coût en surface et la garantie d'un test à la fréquence nominale. Ce dernier point a été pris en compte en proposant une technique d'optimisation temporelle (appelée Rapid BIST) des architectures BISTs élaborées, qui permet une réduction du temps de test et une meilleure couverture de faute en assurant un test à la fréquence nominale même pour les mémoires très rapides (afin de couvrir les fautes de délai). Ces différents avantages sont offerts sans pour autant négliger le coût additionnel en surface. Nous avons également développé une technique CBISR (Column BISR) qui permet d'assurer un rendement de production élevé et une durée de vie prolongée en particulier pour les mémoires de grandes tailles. La seconde partie de cette thèse adressait le problème de la génération automatique des solutions élaborées en concevant et implémentant un outil de synthèse de structures BIST/BISR pour mémoires. Cet outil innove à la fois par l'approche de son implémentation et par les fonctionnalités offertes. Afin de permettre une implémentation efficace, il utilise une approche originale de synthèse de BIST pour les tests de mémoires. Cette approche est basée sur la notion de perturbation par rapport à un axe médian représenté par les tests Marchs. Hormis quelques tests électriques, cette approche de synthèse permet de synthétiser (sur le tas) n'importe quel algorithme de test pour mémoires en une architecture BIST compacte. D'autre part, cette approche est suffisamment flexible pour pouvoir supporter la synthèse des algorithmes de test qui pourront être développés. Il suffit pour cela de supporter leurs perturbations. Les blocs matériels bas niveau sont conçus en utilisant un langage de description spéciale (CHDL) qui est lui-même modélisé sous forme de structure de données écrites dans un langage haut niveau (C++). L'outil implémente un ensemble assez large de solutions BIST/BISR notamment ceux développés dans le cadre de cette thèse. Il offre une indépendance vis à vis de : - La technologie à utiliser, en offrant des descriptions RTL synthétisables. - L'environnement de conception, en générant des scripts de synthèse pour une variété d'outils de synthèse (AMBIT, Design Compiler), et des scripts de simulation pour les simulateurs les plus connus. - Du langage de description de matériel supporté par l'environnement de conception, en décrivant les architectures implémentées dans un langage interne de haut niveau (CHDL) qui pourront ensuite être translatées en langage VHDL et/ou VERILOG. Il offre enfin un mécanisme pour explorer l'espace des solutions en prenant en compte différentes stratégies d'optimisation afin de délivrer l'architecture optimale, suivant le coût en surface, et/ou la fréquence de fonctionnement, et/ou la couverture de faute et/ou la capacité de réparation<br>Modern Systems on Chip usually include large embedded memories. These memories occupy the largest part of the circuit (up to 80% of the total circuit area). Furthermore, memories are more dense than logic and thus, more prone to faults. Therefore, the quality of the memory is crucial for the overall quality of the chip. On the other hand, the reduction of the development cost passes from the reduction of the test cost. Finally, the management of the test complexity of the increasingly complex structures cannot be made with an effective manner without the provision and integration of the advanced test techniques. In the first part of the present thesis, we try to answer to test quality requirement by presenting various memory Built In Self-Test (BIST) solutions that cover all the tests required for memory: characterization test, production test, field test and defects analysis test. The proposed solutions allow handling the limitations of the existing memory BIST techniques, such as the selection of the best trade-off between fault coverage/area overhead and the guarantee of the at-speed testing. We developed also a CBISR (Column Built In Self Repair) technique that allows a significant yield improvement and a prolonged product life in particular for large memories. The second part of this thesis addresses the problem of the automation of the BIST/BISR solutions generation. This is done by designing and implementing a synthesis tool for memories BIST/BISR. This tool innovates at the same time by its implementation approach and the offered features. In order to allow an effective implementation, it uses an original approach of BIST synthesis of the memory tests. This approach is based on the concept of disturbance by report to a median axis represented by the March tests. Except some electric tests, this synthesis approach allows to synthesize any memory test algorithm. Furthermore, by supporting the disturbances of these algorithms, this approach is flexible enough to allow supporting the synthesis of new test algorithms that could be introduced in the future. It offers finally, a mechanism to explore the solutions space by taking into account various optimization strategies in order to deliver optimal architecture, with respect to area cost, the operation frequency, the fault coverage and the repair efficiency
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Muradali, Fidel. "A new procedure for weighted random built-in self-test /." Thesis, McGill University, 1990. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59424.
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Experience has shown that an excessive time penalty can be incurred when testing large scan circuits with a uniform random test pattern generation approach. As a solution to this problem, this work explores the use of weighted random patterns (WRP) to reduce, by orders of magnitude, the test application time in self-testing circuits.<br>Much work has been done on the off-line development of compact test sets, but a problem which still remains is how to efficiently apply them on-chip. A means of transforming a given test set into a relatively short weighted sequence and pseudorandom sequence, whose cumulative fault coverages approximate that guaranteed by the original test set, is proposed.<br>The single weight set is formulated using a method which does not explicitly consider the circuit structure. Instead, sufficient circuit information contained in the given test set can be extracted using simulation techniques. This is done by analyzing a random pattern detection profile and isolating the vectors which cover faults difficult to detect using random patterns. After extracting the useful bits from these vectors, a weight set characteristic of the corresponding faults is estimated as the ratio of 1's to 0's at each bit (input) position.<br>The generation scheme is evaluated using five large scannable circuits. A local approach to on-chip pattern generation is examined.
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Barus, Jasa. "An analysis of aliasing in built-in self test procedure." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/27945.
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Tamarapalli, Nagesh V. "A method of constructive test point insertion for scan-based built-in self-test." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ30398.pdf.
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Tamarapalli, Nagesh V. "A method of constructive test point insertion for scan-based built-in-self-test /." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=34464.
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A new testing paradigm called Built-In Self-Test (BIST) has been gaining increasing acceptance over the traditional automatic test pattern generation for testing the current complex integrated circuits. The basic idea in BIST is to integrate the design with test functionalities like pattern generation, response analysis, and test control. Of the various schemes, pseudo-random pattern testing is an attractive technique for BIST because of the simple hardware required for on-chip test pattern generation. Besides, structures for pseudo-random pattern generation like linear feedback shift register (LFSR) or cellular automata (CA) can also be utilized for on-chip response analysis.<br>In general, pseudo-random BIST is effective only for combinational circuits. This is due to the difficulty associated in obtaining a specific sequence of vectors, through a pseudo-random source, that may be necessary for detecting a fault in a sequential circuit. Thus during test mode, the circuit-under-test (CUT) is transformed to a combinational circuit by configuring memory elements into scan chain(s). However, this may not suffice for circuits that contain random pattern resistant faults or faults not easily detected by random patterns.<br>Two distinct classes of solutions have been proposed to address the random pattern resistance problem--those that modify input patterns and those that modify the CUT. This thesis presents a new, effective circuit modification method for scan-based BIST of integrated circuits. The proposed circuit modification technique utilizes control and observation points to improve the fault coverage, much like the previous techniques. However, unlike the previous methods, the proposed technique is based on a constructive methodology. A divide and conquer approach is used to partition the entire test into multiple phases. In each phase control/observation points targeting a specific set of undetected faults are identified utilizing a new technique called probabilistic fault simulation. This technique blends fault-free simulation and analytical forward fault propagation to accurately compute the information necessary for the identification of control/observation points.<br>Observation points in the proposed scheme are kept enabled for the entire test. However, control points are enabled during specific test phases by fixed values. The usage of fixed values leads to a simple and inherent sharing of the logic driving them. This sharing, as well as the reduction of number of control points result in significant reduction in area overhead. Furthermore, fixed values reduce power dissipation during test mode, since control points instead of toggling are set to a constant value during the entire phase.<br>Experimental results indicate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of few test points and phases. Results show that modification of less than 1% of circuit nodes is sufficient to achieve complete coverage or greater than 99% coverage. In addition, the proposed techniques are fast and hence are applicable to large circuits.
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José, Costa Alves Diogo. "A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns." Universidade Federal de Pernambuco, 2009. https://repositorio.ufpe.br/handle/123456789/1831.
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Made available in DSpace on 2014-06-12T15:52:41Z (GMT). No. of bitstreams: 1
license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5)
Previous issue date: 2009<br>A busca por novas funcionalidades no que diz respeito a melhoria da
confiabilidade dos sistemas eletrônicos e também a necessidade de gerir
o tempo gasto durante o teste faz do mecanismo Built-in-Self-Test (BIST)
um característica promissora a ser integrada no fluxo atual de
desenvolvimento de Circuitos Integrados (IC). Existem vários tipos de
BIST: Memories BIST, Logical BIST (LBIST) e também alguns
mecanismos usados para teste as partes analógicas do circuito. O LBIST
tradicional usa um hardware on-chip para gerar todos os padrões de teste
com um gerador pseudo aleatório (PRPG) e analisa a assinatura de saída
gerada por um registrador de assinatura de múltipla entradas (MISR).
Essa abordagem requer a inserção de pontos de teste extras or
armazenagem de informação fora do chip que tornará possível alcançar
uma cobertura de teste > 98%. Também a geração de todos os estímulos
de teste implica no sacrifício no tempo aplicação do teste, o qual pode ser
aceitável para pequenos sistemas executarem auto-teste durante a
inicialização do sistema mas pode tornasse um aspecto negativo quando
testando System-on-chip (SOC) ICs. O fluxo corrente de desenvolvimento
de um IC insere scan chains e gera automaticamente padrões de teste de
scan para alcançar uma alta cobertura para o teste de manufatura.
Técnicas de compressão de dados provaram ser muito úteis para reduzir
o custo de teste enquanto reduzem o volume de dados e o tempo de
aplicação dos testes. Esse trabalho propõe o reuso de padrões de teste
comprimidos usados durante o teste de manufatura para implementar um
LBIST com objetivo de testar o circuito quando ele já está em campo. O
mecanismo LBIST proposto objetiva descobrir defeitos que podem ocorrer
devido ao desgasto do circuito. Uma arquitetura e um fluxo de
desenvolvimento semi-automático do mecanísmo LBIST baseado em
padrões de teste de scan são propostos e validados usando um SoC real
como caso de teste
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Liu, Jianxun. "Pseudo-Exhaustive Built-in Self-Testing for Signal Integrity of High-Speed SoC Interconnects." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1320174248.
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Zakizadeh, Jila. "Built-in self-test techniques for analog and mixed signal circuits." Thesis, University of Ottawa (Canada), 2005. http://hdl.handle.net/10393/27094.
Full textAbstract:
The present thesis attempts to develop new techniques for testing analog parts of embedded cores-based mixed signal integrated circuits and systems. In particular, the oscillation based test methodologies have been investigated in the thesis. In the oscillation based test methods, the circuit under test (CUT) is first converted to an oscillator in the test mode and the oscillation parameters, viz. frequency, amplitude, etc. are then measured. Any deviation of these parameters causes either the oscillation frequency of the converted CUT to differ from its nominal value, or the converted CUT stops oscillation altogether. For evaluation purpose, a program has been written in C to help us in simulating our test methodologies. The program is used to inject faults to the circuit under test. The detailed experimental results provided give frequency and amplitude measurements data performed on the individual circuit blocks together with fault coverage. In this work, however, only catastrophic faults were considered. The simulation experiments carried out on different circuits not only demonstrate that the developed approaches are quite feasible but show in addition that the fault coverage is quite satisfactory (100%) in all cases.
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Mukherjee, Nilanjan. "Built-in self-test for functional blocks in data-path architectures." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ30344.pdf.
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Cotsapas, Nicos. "Analysis of fault coverage masking in built-in self-test schemes." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63300.
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Mukherjee, Nilanjan. "Built-in self-test for functional blocks in data-path architectures." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=42102.
Full textAbstract:
Built-In Self-Test (BIST) has become one of the most efficient design-for-testability techniques for complex digital circuits, mainly because it simplifies the test generation procedure, shortens the test application time, and eliminates the necessity of expensive external test equipment. However, the addition of circuit-independent test structures have often restricted the usage of BIST for high-performance and large-volume production circuits. Recently, several new testing schemes based on the concept of an Arithmetic BIST have been proposed, where simple arithmetic functions are used to generate test vectors and perform test response compaction. This paradigm provides an efficient BIST solution for a variety of circuits featuring basic arithmetic functionality, as there is virtually no hardware overhead and no performance degradation introduced by the scheme.<br>In this thesis, the Arithmetic BIST scheme has been used as a platform to develop new and efficient test schemes for functional blocks in data-path architectures. Data paths generally have numerous arithmetic and logical blocks with very regular and structured implementations. Therefore, an exhaustive coverage of all states at the input of the sub-blocks, constituting a functional block, reduces significantly the test application time. Pseudo-exhaustive tests, unlike pseudo-random test techniques, deliver complete coverage for a much wider spectrum of combinational faults thereby providing a better defect coverage. Furthermore, the establishment of pseudo-exhaustive test conditions for functional blocks in data paths obviate the necessity for fault simulation, which is otherwise very expensive, specially with the "no fault dropping" option required in the BIST mode.<br>The application of pseudo-exhaustive test necessitates an analysis of the susceptibility of various functional blocks in data paths to pseudo-exhaustive patterns. Consequently, a detailed structural examination of several commonly used functional modules in a digital signal processing environment is presented. A relationship between the subspace size that has to be exhaustively covered at the input of the functional blocks and their corresponding structural fault coverage is determined. For certain other functional modules, customized arithmetic generators have been designed to ensure 100% fault coverage. Furthermore, several testability enhancing techniques for multipliers in fixed-width data-path architectures have been presented to ameliorate the overall testability of such designs. These schemes are based on residue number arithmetic, and reuse the existing resources in the data path for their implementation.<br>Finally, a new behavioral synthesis methodology for testable data-path architectures is proposed in the thesis. A pair of test metrics that abstracts the structural testability of data paths at the behavioral-level has been developed. Test pattern generators and output response analyzers are designated at the high-level, thereby allowing the maximum sharing of resources between the functional and test modes of circuit operation. The test metrics along with the assigned generators and compactors are subsequently, used to guide the synthesis of self-testable RT-level data-path implementations. The behavioral synthesis methodology averts adverse test related design decisions thereby avoiding additional hardware otherwise necessary to make a data path testable.
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Kassab, Mark A. "A scheme for built-in self test of a digital integrator /." Thesis, McGill University, 1993. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=68032.
Full textAbstract:
In conventional built-in self test (BIST) schemes, additional hardware is normally added to the original circuit for test pattern generation and compaction of test responses. This additional hardware not only adds significant hardware overhead, but also degrades performance, which cannot be tolerated in high performance architectures such as data-path architectures.<br>Accumulator-Based Compaction (ABC) is a recently introduced test response compaction scheme which targets a broad class of circuits featuring data-path architectures. ABC uses existing arithmetic hardware commonly available in such circuits to perform compaction of test responses with little or no modification to the circuit under test (CUT). This implies little or no area overhead or performance degradation.<br>A scheme based on ABC is introduced to test an integrator circuit commonly used to perform decimation in signal processing systems. The integrator suffers from poor testability due to the nature of the inputs supplied to it. Minor modifications to the circuit are proposed which enhance testability significantly, with negligible area overhead and no performance degradation. Those modifications also allow the CUT itself to be used for test pattern generation and test response compaction. Monte-Carlo simulations are used to verify the complete fault coverage attained after implementation of the suggested modifications. Furthermore, experiments based on measure of the average entropy, namely state coverage and transition coverage, are used to heuristically measure the testability of the circuit independent of a specific fault model.
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Tamilarasan, Karthik Prabhu. "Built-In Self Test (BIST) for Realistic Delay Defects." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8923.
Full textAbstract:
Testing of delay defects is necessary in deep submicron (DSM) technologies. High coverage delay tests produced by automatic test pattern generation (ATPG) can be applied during wafer and package tests, but are difficult to apply during the board test, due to limited chip access. Delay testing at the board level is increasingly important to diagnose failures caused by supply noise or temperature in the board environment. An alternative to ATPG is the built-in self test (BIST). In combination with the insertion of test points, BIST is able to achieve high coverage of stuck-at and transition faults. The quality of BIST patterns on small delay defects is an open question. In this work we analyze the application of BIST to small delay defects using resistive short and open models in order to estimate the coverage and correlate the coverage to traditional delay fault models.