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Journal articles on the topic 'Built-in self test'

Author: Grafiati

Published: 4 June 2021

Last updated: 15 June 2025

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1

Kiran, Kumar Gopathoti, and Sunil Kumar G. "Built-in Self-Test Algorithm for Functional Broadside Tests." Journals of Advancement in Electronics Design 5, no. 3 (2022): 1–9. https://doi.org/10.5281/zenodo.7476638.

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<em>In this paper, we propose a technique for weighted test sequence generation for synchronous sequential circuit’s on-chip. Three weights—0, 0.5, and 1—are adequate for combinational circuits to completely cover stuck-at failures because they can accurately duplicate any given test pattern. We define the weights for sequential circuits based on subsequences of a deterministic test sequence. These weights enable us to partially replicate the test sequence and assure that the resulting weighted test sequences would receive full fault coverage. This accumulator-based 3-weight test pattern generating system is demonstrated and more effectively addresses the fundamental shortcomings of the suggested scheme. Compared to traditional techniques of creating test sequences for complicated large-scale systems, the weighted random test pattern generation represents a major improvement.</em>

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2

Zorian, Yervant. "Built-in self-test." Microelectronic Engineering 49, no. 1-2 (1999): 135–38. http://dx.doi.org/10.1016/s0167-9317(99)00434-7.

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3

McCluskey, Edward. "Built-In Self-Test Techniques." IEEE Design & Test of Computers 2, no. 2 (1985): 21–28. http://dx.doi.org/10.1109/mdt.1985.294856.

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4

McCluskey, Edward. "Built-In Self-Test Structures." IEEE Design & Test of Computers 2, no. 2 (1985): 29–36. http://dx.doi.org/10.1109/mdt.1985.294857.

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5

Ungar, L. Y., and T. Ambler. "Economics of built-in self-test." IEEE Design & Test of Computers 18, no. 5 (2001): 70–79. http://dx.doi.org/10.1109/54.953274.

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6

Seuring, Markus. "Combining Scan Test and Built-in Self Test." Journal of Electronic Testing 22, no. 3 (2006): 297–99. http://dx.doi.org/10.1007/s10836-006-8950-7.

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7

Adham, S., M. Kassab, J. Rajski, and J. Tyszer. "Built-in self test of digital decimators." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 42, no. 7 (1995): 486–92. http://dx.doi.org/10.1109/82.401174.

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8

Gloster, C. S., and F. Brglez. "Boundary scan with built-in self-test." IEEE Design & Test of Computers 6, no. 1 (1989): 36–44. http://dx.doi.org/10.1109/54.20388.

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9

Deb, N., and R. D. Blanton. "Built-In Self-Test of MEMS Accelerometers." Journal of Microelectromechanical Systems 15, no. 1 (2006): 52–68. http://dx.doi.org/10.1109/jmems.2006.864239.

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10

Mir, S., L. Rufer, and A. Dhayni. "Built-in-self-test techniques for MEMS." Microelectronics Journal 37, no. 12 (2006): 1591–97. http://dx.doi.org/10.1016/j.mejo.2006.04.016.

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11

Konemann, B., B. Bennetts, N. Jarwala, and B. Nadeau-Dostie. "Built-in self-test: assuring system integrity." Computer 29, no. 11 (1996): 39–45. http://dx.doi.org/10.1109/2.544236.

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12

Savir, Jacob, and Paul H. Bardell. "Built-In Self-Test: Milestones and Challenges." VLSI Design 1, no. 1 (1993): 23–44. http://dx.doi.org/10.1155/1993/81360.

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This paper describes the progress in built-in self-test (BIST) since its inception, and the important problems that still need to be solved to make the technique widely acceptable. The paper includes a reference list and an extensive bibliography on the subject matter.

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13

Pulukuri, Mary D., and Charles E. Stroud. "On Built-In Self-Test for Adders." Journal of Electronic Testing 25, no. 6 (2009): 343–46. http://dx.doi.org/10.1007/s10836-009-5114-6.

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14

P, Nagma, Ramachandran S, and Sathishkumar E. "Fault Testing and Diagnosis of Sram based FBGA using Built-In-Self-Test-Architecture." International Journal of Trend in Scientific Research and Development Volume-2, Issue-2 (2018): 717–30. http://dx.doi.org/10.31142/ijtsrd9415.

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15

Kumar, Y. G. Praveen, B. S. Kariyappa, and M. Z. Kurian. "Design, Implementation and Performance Analysis of Test Pattern Generator for Built-In Self-Test using m-GDI Technology." Indian Journal of Science and Technology 15, no. 5 (2021): 221–26. http://dx.doi.org/10.17485/ijst/v15i5.1846.

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16

Daniels, R. Gary, and William C. Bruce. "Built-In Self-Test Trends in Motorola Microprocessors." IEEE Design & Test of Computers 2, no. 2 (1985): 64–71. http://dx.doi.org/10.1109/mdt.1985.294865.

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17

Nicolaidis, M. "Self-exercising checkers for unified built-in self-test (UBIST)." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 8, no. 3 (1989): 203–18. http://dx.doi.org/10.1109/43.21840.

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18

Groza, Voicu, Rami Abielmona, Mansour H. Assaf, Mohammed Elbadri, Mohammad El-Kadri, and Arkan Khalaf. "A Self-Reconfigurable Platform for Built-In Self-Test Applications." IEEE Transactions on Instrumentation and Measurement 56, no. 4 (2007): 1307–15. http://dx.doi.org/10.1109/tim.2007.900134.

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19

Qi, Dandan, and Jon C. Muzio. "Non-linear test pattern generators for built-in self-test." International Journal of Communication Networks and Distributed Systems 1, no. 2 (2008): 179. http://dx.doi.org/10.1504/ijcnds.2008.020259.

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20

Craig, G. L., C. R. Kine, and K. K. Saluja. "Test scheduling and control for VLSI built-in self-test." IEEE Transactions on Computers 37, no. 9 (1988): 1099–109. http://dx.doi.org/10.1109/12.2260.

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21

Anwer, Sabah Ahmed, and Al-Gayem Qais. "Self-test and calibration methods for micro electro-mechanical systems." TELKOMNIKA (Telecommunication, Computing, Electronics and Control) 21, no. 1 (2023): 186–94. https://doi.org/10.12928/telkomnika.v21i1.24251.

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For the testing of micro electro-mechanical systems, we propose a taxonomy of built-in self-testing methods. These solutions that are non-intrusive, cost-effective and are typically non-intrusive during the testing process are being actively sought after as the cost of micro-electro-mechanical systems (MEMS) testing can account for 50% of the total cost of the end product. The selection of testing methods is analyzed extensively, and a classification table for such methods is presented according to three performance metrics: ease of application, test application, usefulness. Performance table also provides a field test domain for the method. While built-in-self-test (BIST) methods do depend on the application at hand, utilizing the inherent multimodal sensing capability of most sensors could be a promising approach for effective built-in self-test.

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22

Kumar, Kota Satish, Sivasankari S.A, Gaddam Vinay, Bhaskar S, and Bala Venkateswarlu.P. "Digital Technique for Analog Built-in Self-Test." IOSR journal of VLSI and Signal Processing 4, no. 4 (2014): 38–45. http://dx.doi.org/10.9790/4200-04433845.

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23

Radecka, K., J. Rajski, and J. Tyszser. "Arithmetic built-in self-test for DSP cores." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, no. 11 (1997): 1358–69. http://dx.doi.org/10.1109/43.663825.

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24

Gala, M., D. Ross, K. Watson, B. Vasudevan, and P. Utama. "Built-in self test for C-testable ILA's." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14, no. 11 (1995): 1388–98. http://dx.doi.org/10.1109/43.469664.

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25

Treuer, Robert, Hideo Fujiwara, and Vinod Agarwal. "Implementing a Built-In Self-Test PLA Design." IEEE Design & Test of Computers 2, no. 2 (1985): 37–48. http://dx.doi.org/10.1109/mdt.1985.294859.

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26

Dekker, R., F. Beenker, and L. Thijssen. "Realistic built-in self-test for static RAMs." IEEE Design & Test of Computers 6, no. 1 (1989): 26–34. http://dx.doi.org/10.1109/54.20387.

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27

Illman, R., and S. Clarke. "Built-in self-test of the Macrolan chip." IEEE Design & Test of Computers 7, no. 2 (1990): 29–40. http://dx.doi.org/10.1109/54.53043.

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28

Gizopoulos, D., A. Paschalis, and Y. Zorian. "Effective built-in self test for Booth multipliers." IEEE Design & Test of Computers 15, no. 3 (1998): 105–11. http://dx.doi.org/10.1109/54.706041.

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29

Cerny, E., E. M. Aboulhamid, G. Bois, and J. Cloutier. "Built-in self-test of a CMOS ALU." IEEE Design & Test of Computers 5, no. 4 (1988): 38–48. http://dx.doi.org/10.1109/54.7968.

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30

Hortensius, P. D., R. D. McLeod, and B. W. Podaima. "Cellular automata circuits for built-in self-test." IBM Journal of Research and Development 34, no. 2.3 (1990): 389–405. http://dx.doi.org/10.1147/rd.342.0389.

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31

RAJASHEKHARA, T. N. "Built-in self-test design of semiconductor memory." International Journal of Electronics 70, no. 3 (1991): 645–49. http://dx.doi.org/10.1080/00207219108921316.

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32

Steininger, Andreas. "Testing and built-in self-test – A survey." Journal of Systems Architecture 46, no. 9 (2000): 721–47. http://dx.doi.org/10.1016/s1383-7621(99)00041-7.

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33

Radecka, K., J. Rajski, and J. Tyszer. "Arithmetic built-in self-test for DSP cores." Computer Standards & Interfaces 20, no. 6-7 (1999): 473. http://dx.doi.org/10.1016/s0920-5489(99)91044-9.

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34

Stojev, M. "Arithmetic built-in self-test for embedded systems." Microelectronics Journal 29, no. 12 (1998): 1045–46. http://dx.doi.org/10.1016/s0026-2692(98)80001-3.

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35

Hsu, C. L., Y. Lai, and S. W. Wang. "Built-In Self-Test for Phase-Locked Loops." IEEE Transactions on Instrumentation and Measurement 54, no. 3 (2005): 996–1002. http://dx.doi.org/10.1109/tim.2005.847343.

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36

Shrivastava, Sakshi, Sunil Malviya, and Neelesh Gupta. "Built in Self Test Architecture Using Logic Module." International Journal of VLSI Design & Communication Systems 8, no. 4 (2017): 25–34. http://dx.doi.org/10.5121/vlsic.2017.8403.

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37

Santos, M. B., and J. Paulo Teixeira. "Functional-oriented mask-based built-in self-test." IET Computers & Digital Techniques 1, no. 5 (2007): 491. http://dx.doi.org/10.1049/iet-cdt:20060073.

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38

Chen, Chien-In Henry. "Partitioning Techniques for Built-In Self-Test Design." VLSI Design 2, no. 3 (1994): 185–98. http://dx.doi.org/10.1155/1994/25656.

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An efficient, unified algorithm, Advanced Two-Phase Cluster Partitioning, is proposed for automated synthesis of pseudo-exhaustive test generator for Built-In Self-Test (BIST) design. A prototype of the algorithm, Two-Phase Cluster Partitioning, has been proposed and the hierarchical design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. However, in certain worst case, the algorithm may generate a sub-optimal design which requires more test patterns and/or hardware overhead. In order to generate a globally optimal design, further improvement of two-phase algorithm can be achieved by expanding the design space for the formation of linear sum so that the number of test signals required for pseudo-exhaustive testing can be reduced. We demonstrate the effectiveness of our approach by presenting detailed comparisons of our results against those that would be obtained by existing techniques.

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39

Agrawal, Vishwani D., Chih-Jen Lin, Paul W. Rutkowski, Shianling Wu, and Yervant Zorian. "Built-in Self-Test for Digital Integrated Circuits." AT&T Technical Journal 73, no. 2 (1994): 30–39. http://dx.doi.org/10.1002/j.1538-7305.1994.tb00576.x.

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40

Mohamed. "Low Transition Test Pattern Generator Architecture for Built-in-Self-Test." American Journal of Applied Sciences 9, no. 9 (2012): 1396–406. http://dx.doi.org/10.3844/ajassp.2012.1396.1406.

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41

Pradhan, D. K., and M. Chatterjee. "GLFSR-a new test pattern generator for built-in-self-test." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18, no. 2 (1999): 238–47. http://dx.doi.org/10.1109/43.743744.

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42

Mukherjee, N., T. J. Chakraborty, and R. Karri. "Built in self test: a complete test solution for telecommunication systems." IEEE Communications Magazine 37, no. 6 (1999): 72–78. http://dx.doi.org/10.1109/35.769277.

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43

Y, G. Praveen Kumar, S. Kariyappa B, and Z. Kurian M. "Design, Implementation and Performance Analysis of Test Pattern Generator for Built-In Self-Test using m-GDI Technology." Indian Journal of Science and Technology 15, no. 5 (2022): 221–26. https://doi.org/10.17485/IJST/v15i5.1846.

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ABSTRACT <strong>Background:</strong> A Linear Feedback Shift Register (LFSR) is typically used for generating the test patterns in built-in self-test (BIST) as it produces pseudorandom patterns at every clock cycle. These pseudo-random patterns are used as test vectors for testing the VLSI circuits. Objective: The pseudorandom patterns generated by the LFSR exhibit low-correlation among the patterns, this increases the switching activity and power dissipation while testing the VLSI circuit. Thus, to reduce the testing power, modified gate diffusion input (m-GDI) logic based LFSR in 45nm technology is proposed in this paper. <strong>Methods:</strong> The circuits are developed on m-GDI technology using the Cadence virtuoso tool and a spectre simulator is used to carry out the simulation. <strong>Findings:</strong> Comparative analysis revealed that the delay and power are reduced significantly, for the proposed design when compared to the existing LFSRs in conventional CMOS, GDI and reversible logic. <strong>Novelty and applications:</strong> In conventional LFSR, an external source is necessary to load the seed value and it dissipates more power. But in the proposed design, the seed value is generated by the circuit itself. This reduces the power and critical path delay. Further a complete zero patterns is not possible in conventional LFSR design. But in proposed design, all zero pattern is plausible. The design obtained from this study can be applied in low-power, high-speed BIST circuits. <strong>Keywords:</strong> LFSR; Seed Value; Test Patterns; Built-In-Self-Test; m-GDI

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44

Acharya, Gobinda Prasad, Muddapu Asha Rani, Ganjikunta Ganesh Kumar, and Lavanya Poluboyina. "Adaptation of March-SS algorithm to word-oriented memory built-in self-test and repair." Indonesian Journal of Electrical Engineering and Computer Science 26, no. 1 (2022): 96–104. https://doi.org/10.11591/ijeecs.v26.i1.pp96-104.

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The technology shrinkage and the increased demand for high storage memory devices in today’s system on-chips (SoCs) has been the challenges to the designers not only in the design cycle but also to the test engineers in testing these memory devices against the permanent faults, intermittent and soft errors. Around 90% of the chip area in today’s SoCs is being occupied by the embedded memories, and the cost for testing these memory devices contributes a major factor in the overall cost and the time to market. This paper proposes a strategy to develop a word-oriented March SS algorithm-basedmemory built-in self-test (MBIST), which is then applied for memory built-in self-test and repair (MBISTR) strategy. The implementation details for 1 KB of single-port static random-access memory (SRAM) depict that the modified March-SS algorithm based MBISTR-enabled SRAM facilitates self-test and self-repair of embedded memories with a marginal hardware overhead (<1%) in terms of look up tables and slice registers when compared to that of standard SRAM.

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45

Kim, Jin-Wan, and Hoon Chang. "TLC NAND-type Flash Memory Built-in Self Test." Journal of the Institute of Electronics and Information Engineers 51, no. 12 (2014): 72–82. http://dx.doi.org/10.5573/ieie.2014.51.12.072.

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46

Wurtz, L. T. "Built-in self-test structure for mixed-mode circuits." IEEE Transactions on Instrumentation and Measurement 42, no. 1 (1993): 25–29. http://dx.doi.org/10.1109/19.206674.

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47

Agrawal, V. D., C. R. Kime, and K. K. Saluja. "A tutorial on built-in self-test. I. Principles." IEEE Design & Test of Computers 10, no. 1 (1993): 73–82. http://dx.doi.org/10.1109/54.199807.

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48

Agrawal, V. D., C. R. Kime, and K. K. Saluja. "A tutorial on built-in self-test. 2. Applications." IEEE Design & Test of Computers 10, no. 2 (1993): 69–77. http://dx.doi.org/10.1109/54.211530.

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49

Chatterjee, A., B. C. Kim, and N. Nagi. "DC built-in self-test for linear analog circuits." IEEE Design & Test of Computers 13, no. 2 (1996): 26–33. http://dx.doi.org/10.1109/54.500198.

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50

Ortega, J., A. Prieto, A. Lloris, and F. Pelayo. "Universal built-in self-test procedure for CMOS PLA's." IEEE Transactions on Circuits and Systems 38, no. 8 (1991): 941–45. http://dx.doi.org/10.1109/31.85635.

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