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1
Dixon, Bobby Earl Stroud Charles E. "Built-in self-test of the programmable interconnect in field programmable gate arrays." Auburn, Ala, 2008. http://repo.lib.auburn.edu/EtdRoot/2008/FALL/Electrical_and_Computer_Engineering/Thesis/Dixon_Bobby_16.pdf.
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Zhang, Shujian. "Evaluation in built-in self-test." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ34293.pdf.
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Bogue, Tracey M. "Aliasing reduction in built-in self-test." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/nq21280.pdf.
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XIONG, XINGGUO. "BUILT-IN SELF-TEST AND SELF-REPAIR FOR CAPACITIVE MEMS DEVICES." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1123038236.
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Dhawan, Sanjay. "A built-in self-test PLA generator." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-08042009-040315/.
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Ho, Thanh Huong. "Test compaction technique for built-in self-test in VLSI circuits." Thesis, University of Ottawa (Canada), 1994. http://hdl.handle.net/10393/6460.
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In recent years, many test output data compression techniques have been introduced, which reduce the storage requirements of reference signatures for the circuit under test. A major problem, however, is that the compression always results in loss of error coverage. This work proposes a space compression technique for digital circuits with the objective of minimizing the storage for the circuits under test while maintaining the fault coverage information. The technique introduced is called a Modified Dynamic Space Compression method. For a circuit under test, a compaction tree is generated based on its structure. The detectable error probability was calculated by using the Boolean Difference Method. The output data modification was employed to minimize the number of faulty output data patterns which have the same compressed form as the fault free patterns. The compressed outputs were then fed into a syndrome counter to derive the signature for the circuit. A design program is written in C language and executed on PC which combines the space compression, output data modification, and faults testing. Simulations were performed on known combinational circuits and the results indicate that the loss in fault coverage caused by compression is rather small.
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Muradali, Fidel. "A self-driven test methodology for built-in self-test of sequential circuits /." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=42106.
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Test cost comprises a substantial portion of producing an integrated circuit. As a result, structural modifications of the circuit via design for test (DFT) techniques are commonly used as an aid to reduce test cost to the lowest possible level. One important class of DFT is Built-In Self-Test (BIST). In BIST, test generation and response analysis logic is integrated into the original circuit and are transparent during normal operation. In this manner, in-circuit tests can be performed with minimal need of external test equipment, if any.<br>Test strategies based on pseudorandom test stimuli are attractive since the simplicity of the pattern generation logic facilitates on-chip test application. Unfortunately, until now, these methods have been more appropriate for testing combinational rather than sequential circuits. This is largely because, unlike combinational testing, detection of sequential faults can require specific orderings of circuit operations which are prohibitively difficult to produce using a pseudorandom source.<br>This thesis introduces a new DFT technique which permits at-speed on-chip sequential testing using parallel pseudorandom test patterns applied only to the primary inputs of the circuit under test. Test network design focuses on adjusting fault free circuit activity and aiding error propagation. This is done via the strategic insertion of a small number of low area test points. The resulting system is unique in that aside from a test mode flag, all I/O signals needed for test system operation are tapped from within the circuit itself. This feature virtually eliminates the control signal generation logic typically needed in other test point strategies. Also, as opposed to the conventional approach of restricting circuit alterations to the state elements, the proposed flexibility in choosing modification sites is beneficial when considering speed constrained designs.<br>Experiments demonstrate that high single stuck-at fault coverage is achieved for a number of benchmark circuits.
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Muradali, Fidel. "A self-driven test methodology for built-in self-test of sequential circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ30348.pdf.
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Radecka, Katarzyna. "Arithmetical built-in self test for DSP architectures." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ29624.pdf.
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Olbrich, Thomas. "Design-for-Test and Built-In-Self-Test for integrated systems." Thesis, Lancaster University, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.312594.
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Khalaf, Arkan. "A self-reconfigurable platform for built-in-self-test applications." Thesis, University of Ottawa (Canada), 2007. http://hdl.handle.net/10393/27865.
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This thesis introduces a novel architecture of a run-time reconfigurable microsystem on chip (SoC). This system consists of a logic block that can be reconfigured at run time, and an embedded multi-microprocessor system that connects to this logic block and can reconfigure it at run time using special resources of Field Programmable Gate Arrays (FPGA). A design flow for run-time reconfigurable logic circuits has been developed and is presented in the context of the implementation of the SoC on a FPGA.
This reconfigurable architecture is validated by an application that implements the novel idea of verifying algorithms for testing digital circuits by using run-time reconfigurable techniques, in order to minimize circuit area, as well as test generation and application time. The idea revolves around the dynamic partial reconfiguration of circuits under test, in order to inject stuck-at faults at different locations of the circuit, to verify for and uncover logic structural faults.
The thesis presents the design and implementation of a self-reconfigurable platform, where faults are injected at run-time to the circuit under test. It analyzes the ways of injecting faults and the run-time reconfiguration overhead associated with it, while the rest of the circuit is present on the reconfigurable architecture, in order to validate run-time reconfigurable built-in-self-test techniques, as compared to the more traditional methods.
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Jervan, Gert. "Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems." Doctoral thesis, Linköping : Dept. of Computer and Information Science, Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2994.
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Gopalan, Anand. "Built-in-self-test of RF front-end circuitry /." Link to online version, 2005. https://ritdml.rit.edu/dspace/handle/1850/942.
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El-Mahlawy, Mohamed Hassan Mohamed. "Pseudo-exhaustive built-in self-test for boundary scan." Thesis, University of Kent, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.324714.
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Gaur, Manoj Singh. "Integration of built in self test during behavioural synthesis." Thesis, University of Southampton, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.427421.
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Garrison, Brooks Stroud Charles E. "Analysis and improvement of Virtex-4 block RAM Built-In Self-Test and introduction to Virtex-5 block RAM Built-In Self-Test." Auburn, Ala, 2009. http://hdl.handle.net/10415/1667.
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Barus, Jasa. "An analysis of aliasing in built-in self test procedure." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/27945.
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Jervan, Gert. "High-Level Test Generation and Built-In Self-Test Techniques for Digital Systems." Licentiate thesis, Linköping : Univ, 2002. http://www.ep.liu.se/lic/science_technology/09/73/index.html.
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Yao, Jia Stroud Charles E. "Built-In self-test of global routing resources in Virtex-4 FPGAs." Auburn, Ala., 2009. http://hdl.handle.net/10415/1723.
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Robson, Malcolm. "M-sequence testing of embedded analogue functions." Thesis, University of Newcastle Upon Tyne, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.242360.
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Allott, Stephen. "The development and implementation of automatic test techniques for Analogue to Digital Converter characterization using a deterministic approach." Thesis, University of Huddersfield, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.385712.
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Muradali, Fidel. "A new procedure for weighted random built-in self-test /." Thesis, McGill University, 1990. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59424.
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Experience has shown that an excessive time penalty can be incurred when testing large scan circuits with a uniform random test pattern generation approach. As a solution to this problem, this work explores the use of weighted random patterns (WRP) to reduce, by orders of magnitude, the test application time in self-testing circuits.<br>Much work has been done on the off-line development of compact test sets, but a problem which still remains is how to efficiently apply them on-chip. A means of transforming a given test set into a relatively short weighted sequence and pseudorandom sequence, whose cumulative fault coverages approximate that guaranteed by the original test set, is proposed.<br>The single weight set is formulated using a method which does not explicitly consider the circuit structure. Instead, sufficient circuit information contained in the given test set can be extracted using simulation techniques. This is done by analyzing a random pattern detection profile and isolating the vectors which cover faults difficult to detect using random patterns. After extracting the useful bits from these vectors, a weight set characteristic of the corresponding faults is estimated as the ratio of 1's to 0's at each bit (input) position.<br>The generation scheme is evaluated using five large scannable circuits. A local approach to on-chip pattern generation is examined.
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Testa, Luca. "Contribution to the Built-In Self-Test for RF VCOs." Thesis, Bordeaux 1, 2010. http://www.theses.fr/2010BOR14011/document.
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Ce travail concerne l'étude et la réalisation de stratégies d'auto-test intégrées pour VCO radiofréquence (RF). La complexité des circuits intégrés RF devient un obstacle pour la mesure des principaux blocs RF des chaines de transmission/réception. Certains nœuds ne sont pas accessibles, l'excursion en tension des signaux baisse et les signaux haute fréquence ne peuvent pas être amenés à l'extérieur de la puce sans une forte dégradation. Le s techniques habituelles de test deviennent très couteuses et lentes. Le test pour le wafer-sort est étudié en premier. La solution proposée est la mise en œuvre d'une stratégie d'auto-test intégrée (BIST) qui puisse discriminer entre circuits sans fautes et circuits avec fautes pendant le wafer-test. La méthodologie utilisée est le test structurel. La couverture des fautes est étudiée pour connaitre la quantité à capter au niveau intégré afin de maximiser la probabilité de trouver tous les défauts physiques dans le VCO. Le résultat de cette analyse montre que la couverture des fautes est maximisée quand la tension crête-crête en sortie du VCO est captée. La caractérisation complète (validation de la puce et process-monitoring) du VCO est étudiée dans la deuxième étape. Les informations à extraire de la puce sont: amplitude des signaux, consommation du VCO, fréquence d'oscillation, gain de conversion (Kvco) et une information à propos du bruit de phase. Un démonstrateur pour le test au niveau wafer est réalisé en technologie ST CMOS 65nm. Le démonstrateur est composé d'un VCO 3.5GHz (le circuit sous test), un LDO, une référence de tension indépendante de température et variations d'alimentation, un capteur de tension crête-crête et un comparateur. Le capteur Vpp donne en sortie une information DC qui est comparée avec une plage de valeurs acceptables. Le BIST donne en sortie une information numérique pass/fail<br>This work deals with the study and the realization of Built-In Self-Tests (BIST) for RF VCOs (Voltage Controlled Oscillators) The increasing complexity of RF integrated circuits is creating an obstacle for the correct measurement of the main RF blocks of any transceiver. Some nodes are not accessible, the voltage excursion of the signals is getting lower and lower and high frequency signals cannot be driven off the die without a main degradation. The common test techniques become then very expensive and time consuming. The wafer sort is firstly approached. The proposed solution is the implementation of a BIST strategy able to discriminate between faulty and good circuits during the wafer test. The chosen methodology is the structural test (fault-oriented). A fault coverage campaign is carried out in order to find the quantity to monitor on-chip that maximizes the probability to find all possible physical defects in the VCO. The result of the analysis reveals that the fault coverage is maximized if the peak-to-peak output voltage is monitored. The complete on-chip characterization of the VCO is then addressed, for chip validation and process monitoring. The information that need to be extracted on-chip concern: amplitude of the signal, consumption of the VCO, frequency of oscillation, its conversion gain (voltage-to-frequency) and eventually some information on the phase noise. A silicon demonstrator for wafer sort purposes is implemented using the ST CMOS 65nm process. It includes a 3.5GHz VCO, an LDO, a temperature and supply-voltage independent voltage reference, a peak-to-peak voltage detector and a comparator. The Vpp detector outputs a DC-voltage that is compared to a predefined acceptance boundary. A logic pass/fail signal is output by the BIST. The attention is then turned to the study of the proposed architecture for an on-chip frequency-meter able to measure the RF frequency with high accuracy. Behavioral simulations using VHDL-AMS lead to the conclusion that a TDC (Time-to-Digital Converter) is the best solution for our goal. The road is then opened to the measure of long-time jitter making use of the same TDC
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Cotsapas, Nicos. "Analysis of fault coverage masking in built-in self-test schemes." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63300.
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Mukherjee, Nilanjan. "Built-in self-test for functional blocks in data-path architectures." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=42102.
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Built-In Self-Test (BIST) has become one of the most efficient design-for-testability techniques for complex digital circuits, mainly because it simplifies the test generation procedure, shortens the test application time, and eliminates the necessity of expensive external test equipment. However, the addition of circuit-independent test structures have often restricted the usage of BIST for high-performance and large-volume production circuits. Recently, several new testing schemes based on the concept of an Arithmetic BIST have been proposed, where simple arithmetic functions are used to generate test vectors and perform test response compaction. This paradigm provides an efficient BIST solution for a variety of circuits featuring basic arithmetic functionality, as there is virtually no hardware overhead and no performance degradation introduced by the scheme.<br>In this thesis, the Arithmetic BIST scheme has been used as a platform to develop new and efficient test schemes for functional blocks in data-path architectures. Data paths generally have numerous arithmetic and logical blocks with very regular and structured implementations. Therefore, an exhaustive coverage of all states at the input of the sub-blocks, constituting a functional block, reduces significantly the test application time. Pseudo-exhaustive tests, unlike pseudo-random test techniques, deliver complete coverage for a much wider spectrum of combinational faults thereby providing a better defect coverage. Furthermore, the establishment of pseudo-exhaustive test conditions for functional blocks in data paths obviate the necessity for fault simulation, which is otherwise very expensive, specially with the "no fault dropping" option required in the BIST mode.<br>The application of pseudo-exhaustive test necessitates an analysis of the susceptibility of various functional blocks in data paths to pseudo-exhaustive patterns. Consequently, a detailed structural examination of several commonly used functional modules in a digital signal processing environment is presented. A relationship between the subspace size that has to be exhaustively covered at the input of the functional blocks and their corresponding structural fault coverage is determined. For certain other functional modules, customized arithmetic generators have been designed to ensure 100% fault coverage. Furthermore, several testability enhancing techniques for multipliers in fixed-width data-path architectures have been presented to ameliorate the overall testability of such designs. These schemes are based on residue number arithmetic, and reuse the existing resources in the data path for their implementation.<br>Finally, a new behavioral synthesis methodology for testable data-path architectures is proposed in the thesis. A pair of test metrics that abstracts the structural testability of data paths at the behavioral-level has been developed. Test pattern generators and output response analyzers are designated at the high-level, thereby allowing the maximum sharing of resources between the functional and test modes of circuit operation. The test metrics along with the assigned generators and compactors are subsequently, used to guide the synthesis of self-testable RT-level data-path implementations. The behavioral synthesis methodology averts adverse test related design decisions thereby avoiding additional hardware otherwise necessary to make a data path testable.
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Mukherjee, Nilanjan. "Built-in self-test for functional blocks in data-path architectures." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ30344.pdf.
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José, Costa Alves Diogo. "A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns." Universidade Federal de Pernambuco, 2009. https://repositorio.ufpe.br/handle/123456789/1831.
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Made available in DSpace on 2014-06-12T15:52:41Z (GMT). No. of bitstreams: 1
license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5)
Previous issue date: 2009<br>A busca por novas funcionalidades no que diz respeito a melhoria da
confiabilidade dos sistemas eletrônicos e também a necessidade de gerir
o tempo gasto durante o teste faz do mecanismo Built-in-Self-Test (BIST)
um característica promissora a ser integrada no fluxo atual de
desenvolvimento de Circuitos Integrados (IC). Existem vários tipos de
BIST: Memories BIST, Logical BIST (LBIST) e também alguns
mecanismos usados para teste as partes analógicas do circuito. O LBIST
tradicional usa um hardware on-chip para gerar todos os padrões de teste
com um gerador pseudo aleatório (PRPG) e analisa a assinatura de saída
gerada por um registrador de assinatura de múltipla entradas (MISR).
Essa abordagem requer a inserção de pontos de teste extras or
armazenagem de informação fora do chip que tornará possível alcançar
uma cobertura de teste > 98%. Também a geração de todos os estímulos
de teste implica no sacrifício no tempo aplicação do teste, o qual pode ser
aceitável para pequenos sistemas executarem auto-teste durante a
inicialização do sistema mas pode tornasse um aspecto negativo quando
testando System-on-chip (SOC) ICs. O fluxo corrente de desenvolvimento
de um IC insere scan chains e gera automaticamente padrões de teste de
scan para alcançar uma alta cobertura para o teste de manufatura.
Técnicas de compressão de dados provaram ser muito úteis para reduzir
o custo de teste enquanto reduzem o volume de dados e o tempo de
aplicação dos testes. Esse trabalho propõe o reuso de padrões de teste
comprimidos usados durante o teste de manufatura para implementar um
LBIST com objetivo de testar o circuito quando ele já está em campo. O
mecanismo LBIST proposto objetiva descobrir defeitos que podem ocorrer
devido ao desgasto do circuito. Uma arquitetura e um fluxo de
desenvolvimento semi-automático do mecanísmo LBIST baseado em
padrões de teste de scan são propostos e validados usando um SoC real
como caso de teste
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Tamarapalli, Nagesh V. "A method of constructive test point insertion for scan-based built-in-self-test /." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=34464.
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A new testing paradigm called Built-In Self-Test (BIST) has been gaining increasing acceptance over the traditional automatic test pattern generation for testing the current complex integrated circuits. The basic idea in BIST is to integrate the design with test functionalities like pattern generation, response analysis, and test control. Of the various schemes, pseudo-random pattern testing is an attractive technique for BIST because of the simple hardware required for on-chip test pattern generation. Besides, structures for pseudo-random pattern generation like linear feedback shift register (LFSR) or cellular automata (CA) can also be utilized for on-chip response analysis.<br>In general, pseudo-random BIST is effective only for combinational circuits. This is due to the difficulty associated in obtaining a specific sequence of vectors, through a pseudo-random source, that may be necessary for detecting a fault in a sequential circuit. Thus during test mode, the circuit-under-test (CUT) is transformed to a combinational circuit by configuring memory elements into scan chain(s). However, this may not suffice for circuits that contain random pattern resistant faults or faults not easily detected by random patterns.<br>Two distinct classes of solutions have been proposed to address the random pattern resistance problem--those that modify input patterns and those that modify the CUT. This thesis presents a new, effective circuit modification method for scan-based BIST of integrated circuits. The proposed circuit modification technique utilizes control and observation points to improve the fault coverage, much like the previous techniques. However, unlike the previous methods, the proposed technique is based on a constructive methodology. A divide and conquer approach is used to partition the entire test into multiple phases. In each phase control/observation points targeting a specific set of undetected faults are identified utilizing a new technique called probabilistic fault simulation. This technique blends fault-free simulation and analytical forward fault propagation to accurately compute the information necessary for the identification of control/observation points.<br>Observation points in the proposed scheme are kept enabled for the entire test. However, control points are enabled during specific test phases by fixed values. The usage of fixed values leads to a simple and inherent sharing of the logic driving them. This sharing, as well as the reduction of number of control points result in significant reduction in area overhead. Furthermore, fixed values reduce power dissipation during test mode, since control points instead of toggling are set to a constant value during the entire phase.<br>Experimental results indicate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of few test points and phases. Results show that modification of less than 1% of circuit nodes is sufficient to achieve complete coverage or greater than 99% coverage. In addition, the proposed techniques are fast and hence are applicable to large circuits.
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Tamarapalli, Nagesh V. "A method of constructive test point insertion for scan-based built-in self-test." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ30398.pdf.
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Sudireddy, Samara Simha Reddy. "Accumulator Based Test Set Embedding." OpenSIUC, 2009. https://opensiuc.lib.siu.edu/theses/18.
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In this paper a test set embedding based on accumulator driven by an odd additive constant is presented. The problem is formulated around finding the location of the test pattern in the sequence generated by the accumulator, given a odd constant C and test set T, in terms of linear Diophantine equation of two variables. We show that the search space for finding the best constant corresponding to the shortest length, is greatly reduced. Experimental results show a significant improvement in run time with practically acceptable test length.
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Bou, Sleiman Sleiman. "Built-in-Self-Test and Digital Self-Calibration for Radio Frequency Integrated Circuits." The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1311685013.
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Kassab, Mark A. "A scheme for built-in self test of a digital integrator /." Thesis, McGill University, 1993. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=68032.
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In conventional built-in self test (BIST) schemes, additional hardware is normally added to the original circuit for test pattern generation and compaction of test responses. This additional hardware not only adds significant hardware overhead, but also degrades performance, which cannot be tolerated in high performance architectures such as data-path architectures.<br>Accumulator-Based Compaction (ABC) is a recently introduced test response compaction scheme which targets a broad class of circuits featuring data-path architectures. ABC uses existing arithmetic hardware commonly available in such circuits to perform compaction of test responses with little or no modification to the circuit under test (CUT). This implies little or no area overhead or performance degradation.<br>A scheme based on ABC is introduced to test an integrator circuit commonly used to perform decimation in signal processing systems. The integrator suffers from poor testability due to the nature of the inputs supplied to it. Minor modifications to the circuit are proposed which enhance testability significantly, with negligible area overhead and no performance degradation. Those modifications also allow the CUT itself to be used for test pattern generation and test response compaction. Monte-Carlo simulations are used to verify the complete fault coverage attained after implementation of the suggested modifications. Furthermore, experiments based on measure of the average entropy, namely state coverage and transition coverage, are used to heuristically measure the testability of the circuit independent of a specific fault model.
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Kim, Seongwon. "Built-in self-test technique for high-speed phase-locked loops /." Thesis, Connect to this title online; UW restricted, 2001. http://hdl.handle.net/1773/5957.
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Dogaru, Emanuel. "Built-In Self-Test of Flexible RF Transmitters Using Nonuniform Undersampling." Thesis, CentraleSupélec, 2015. http://www.theses.fr/2015SUPL0004/document.
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Le secteur de communications sécurisés et portables connait une véritable révolution avec l’apparition des plateformes dites radios logiciels (Software Defined Radios, SDRs). Les performances exceptionnelles de ces systèmes sont les résultats d’une interaction assez complexe et souvent peu évidente entre le logiciel embarqué, le circuit de traitement numérique et les blocs mixtes analogiques/RF. Cette complexité limite la testabilité du produit fini. La méthodologie de test utilisée actuellement a atteint ses limites dues au cout élevé, le long temps de test et le bas degré de généralisation. De plus, les plateformes SDRs peuvent évoluer sur le terrain et elles vont supporter des standards et des scénarios qui n’ont pas été considérés pendant le la phase de conception. Donc, une stratégie de test sur le terrain (en ligne) n’est plus une caractéristique optionnelle mais une nécessité. Dans ce contexte, le but de notre recherche est d’inventer et développer une méthodologie de test capable de garantir le bon fonctionnement d’une plateforme SDR après la production et pendant sa vie. Notre objectif final est de réduire le coût du test en profitant de la reconfigurabilité de la plateforme. Pour les radios tactiques qui doivent être mises à jour sur le terrain sans équipement spécial, les stratégies Built-In Self-Test (BIST) sont, sans doute, la seule moyenne de garantir la conformité aux spécifications. Dans cette mémoire, nous introduisons une nouvelle architecture de test RF BIST qui utilise la technique de de sous-échantillonnage nonuniform à la sortie de l’émetteur (TX) d’une SDR afin d’évaluer la conformité de la masque spectrale. Notre solution s’appuie sur une implémentation autonome, est modulable et peut être appliquée pour le test sur le terrain avec des modifications minimes. Par rapport aux autres techniques de test analogiques/RF, cet approche ne dépends pas de la architecture du TX, ni d’un modèle ad-hoc, ce qui est idéale pour le test des SDRs<br>The advent of increasingly powerful Integrated Circuits (IC) has led to the emergence of the Software Defined Radio (SDR) concept, which brought the sector of secured mobile communications into a new era. The outstanding performance of these systems results from optimal trade-offs among advanced analog/Radio Frequency (RF) circuitry, high-speed reconfigurable digital hardware and sophisticated real-time software. The inherent sophistication of such platforms poses a challenging problem for product testing. Currently deployed industrial test strategies face rising obstacles due to the costlier RF test equipment, longer test time and lack of flexibility. Moreover, an SDR platform is field-upgradeable, which means it will support standards and scenarii not considered during the design phase. Therefore, an in-field test strategy is not anymore 'a nice to have' feature but a mandatory requirement. In this context, our research aims to invent and develop a new test methodology able to guarantee the correct functioning of the SDR platform post-fabrication and over its operational lifetime. The overall aim of our efforts is to reduce post-manufacture test cost of SDR transceivers by leveraging the reconfigurability of the platform.For tactical radio units that must be field-upgradeable without specialized equipment, Built-in Self-Test (BIST) schemes are arguably the only way to ensure continued compliance to specifications. In this study we introduce a novel RF BIST architecture which uses Periodically Nonuniform Sampling (PNS2) of the transmitter (TX) output to evaluate compliance to spectral mask specifications. Our solution supports a stand-alone implementation, is scalable across a wide set of complex specifications and can be easily applied for in-field testing with small added hardware. Compared to existing analog/RF test techniques, this approach is not limited to a given TX architecture and does not rely on an ad-hoc TX model, which makes it ideal for SDR testing
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Zakizadeh, Jila. "Built-in self-test techniques for analog and mixed signal circuits." Thesis, University of Ottawa (Canada), 2005. http://hdl.handle.net/10393/27094.
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The present thesis attempts to develop new techniques for testing analog parts of embedded cores-based mixed signal integrated circuits and systems. In particular, the oscillation based test methodologies have been investigated in the thesis. In the oscillation based test methods, the circuit under test (CUT) is first converted to an oscillator in the test mode and the oscillation parameters, viz. frequency, amplitude, etc. are then measured. Any deviation of these parameters causes either the oscillation frequency of the converted CUT to differ from its nominal value, or the converted CUT stops oscillation altogether. For evaluation purpose, a program has been written in C to help us in simulating our test methodologies. The program is used to inject faults to the circuit under test. The detailed experimental results provided give frequency and amplitude measurements data performed on the individual circuit blocks together with fault coverage. In this work, however, only catastrophic faults were considered. The simulation experiments carried out on different circuits not only demonstrate that the developed approaches are quite feasible but show in addition that the fault coverage is quite satisfactory (100%) in all cases.
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Modi, Harmish Rajeshkumar. "In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/55123.
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FPGA fault recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related techniques cannot detect permanent faults within the FPGA fabric, such as short circuits and open circuits in FPGA transistors that arise from electromigration effects. Several Built-In Self-Test (BIST) techniques have been proposed in the past to detect and isolate such faults. These techniques suffer from routing congestion problems in modern FPGAs that have a large number of logic blocks. This thesis presents an improved BIST architecture for all Xilinx 7-Series FPGAs that is scalable to large arrays. The two primary sources of overhead associated with FPGA BIST, the test time and the memory required for storing the BIST configurations, are also reduced when compared to previous FPGA-BIST approaches. The BIST techniques presented here also eliminate the need for using any of the user I/O pins, such as a clock, a reset, and test observation pins; therefore, it is suitable for immediate deployment on any system with Xilinx 7-Series FPGAs. With faults detected, isolated, and corrected, the effective MTBF of a system can be extended.<br>Master of Science
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Zorian, Yervant. "Optimized error coverage in built-in self-test by output data modification." Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=75778.
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The concept of Built-In Self-Test (BIST) has recently become an increasingly attractive solution to the complex problem of testing VLSI chips. However, the realization of BIST faces some challenging problems of its own. One of these problems is to increase the quality of fault coverage of a BIST implementation, without incurring a large overhead. In particular, the loss of information in the output data compressor, which is typically a multi-input linear feedback shift register (MISR), is a major cause of concern.<br>In the recent past, several researchers have proposed different schemes to reduce this loss of information, while maintaining the need for a small area overhead.<br>In this dissertation, a new BIST scheme, based on modifying the output data before compression, is developed. This scheme, called output data modification (ODM), exploits the knowledge of the functionality of the circuit under test to provide a circuit-specific BIST structure. This structure is developed so that it can conveniently be implemented for any general circuit under consideration. But more importantly, a proof of effectiveness is provided to show that ODM will, on the average, be orders of magnitude better than all existing schemes in its capability to reduce the information loss, for a given amount of area overhead.<br>Moreover, the constructive nature of the proof will allow one to provide a simple trade-off between the reduction tolerated in information loss to the area overhead needed to affect this reduction.
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Eatinger, Ryan Joseph. "Built-in self-test in integrated circuits - ESD event mitigation and detection." Thesis, Kansas State University, 2011. http://hdl.handle.net/2097/13538.
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Master of Science<br>Department of Electrical Engineering<br>William Kuhn<br>When enough charges accumulate on two objects, the air dielectric between them breaks down to create a phenomenon known as electrostatic discharge (ESD). ESD is of great concern in the integrated circuit industry because of the damage it can cause to ICs. The problem will only become worse as process components become smaller.
The three main types of ESD experienced by an IC are the human body model (HBM), the charged device model (CDM), and the machine model (MM). HBM ESD has the highest voltage while CDM ESD has the highest bandwidth and current of the three ESD types.
Integrated circuits generally include ESD protection circuitry connected to their pads. Pads are the connection between the IC and the outside world, making them the required location for circuitry designed to route ESD events away from the IC's internal circuitry. The most basic protection pads use diodes connected from I/O to VDD and I/O to ground. A voltage clamp between VDD and ground is also necessary to protect against CDM and MM event types where the device may not yet have a low impedance supply path connected.
The purpose of this research is to investigate the performance of ESD circuits and to develop a method for detecting the occurrence of an ESD event in an integrated circuit by utilizing IC fuses. The combination of IC fuses and detection circuitry designed to sense a broken fuse allows the IC to perform a built-in self-test (BIST) for ESD to identify compromised ICs, preventing manufacturers from shipping damaged circuits.
Simulations are used to design an optimized protection circuit to complement the proposed ESD detection circuit. Optimization of an ESD pad circuit increases the turn-on speed of its voltage clamps and decreases the series resistance of its protection diodes. These improvements minimize the stress voltage placed on internal circuitry due to an ESD event. An ESD measurement setup is established and used to verify voltage clamp operation.
This research also proposes an ESD detection circuit based on IC fuses, which fail during an ESD event. A variety of IC fuses are tested using the ESD measurement setup as well as a TLP setup in order to determine the time and current needed for them to break. Suitable IC fuses have a resistance less than 5 Ω and consistently break during the first trial.
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Yan, Wenjian. "A wideband frequency synthesizer for built-in self testing of analog integrated circuits." Texas A&M University, 2004. http://hdl.handle.net/1969.1/1059.
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The cost to test chips has risen tremendously. Additionally, the process for testing all functionalities of both analog and digital part is far from simple. One attractive option is moving some or all of the testing functions onto the chip itself leading to the use of built-in self-tests (BISTs). The frequency generator or frequency synthesizer is a key element of the BIST. It generates the clock frequencies needed for testing.
A wide-band frequency synthesizer is designed in the project. The architecture of a PLL is analyzed as well as the modifications carried out. The modified structure has three blocks: basic PLL based frequency synthesizer, frequency down-converter, and output selector. Each of these blocks is analyzed and designed. This frequency synthesizer system overcomes challenges faced by the traditional PLL based frequency synthesizer.
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Han, Dong-Hoon. "Built-In Self Test and Calibration of RF Systems for Parametric Failures." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/14507.
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This thesis proposes a multifaceted production test and post-silicon yield enhancement framework for RF systems. The three main components of the proposed framework are the design, production test, and post-test phase of the overall integrated circuit (IC) development cycle. First, a circuit-sizing method is presented for incorporating test considerations into algorithms for automatic circuit synthesis/device resizing. The sizing problem is solved by using a cost metric that can be incorporated at minimal computational cost into existing optimization tools for manufacturing yield enhancement. Along with the circuit-sizing method introduced in the design phase, a low-cost test and diagnosis method is presented for multi-parametric faults in wireless systems. This test and diagnosis method allows accurate prediction of the end-to-end specifications as well as for the specifications of all the embedded modules. The procedure is based on application of optimized test stimulus and the use of a simple diode-based envelope detector to extract the transient test response envelope at RF signal nodes. This eliminates the need to make RF measurements using expensive standard testers. To further improve the parametric yield of RF circuits, a performance drift-aware adaptation scheme is proposed that automatically compensates for the loss of circuit performance in the presence of process variations. This work includes a diagnosis algorithm to identify faulty circuits within the system and a compensation process that adjusts tunable components to reduce the effects of performance variations. As a result, all the mentioned components contribute to producing a low-cost production test and to enhancing post-silicon parametric yield.
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Venkataraman, Srikanth. "Built-in self test based on reseeding of linear feedback shift registers." Thesis, McGill University, 1993. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=69705.
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In this thesis an optimized Built-In Self Test (BIST) scheme based on reseeding of multiple polynomial Linear Feedback Shift Registers (LFSRs) is proposed. The same LFSR that is used to generate pseudo-random patterns, is loaded with seeds from which it produces vectors that cover the testcubes which detect faults that are hard to test. The scheme is compatible with scan-design and achieves full coverage as it is based on random patterns combined with a deterministic test set.<br>Two methods for processing a test set to allow for efficient encoding of testcubes as LFSR seeds are proposed. The first method involves merging pairwise consistent testcubes in the test set. The second method involves concatenating the original testcubes to form longer testcubes. This allows multiple testcubes to be encoded into a single LFSR seed. Algorithms to perform merging and concatenation of the test set are presented. An algorithm for calculating LFSR seeds from the test set is described. A method to balance testcubes with respect to the feedback polynomials of the multiple polynomial LFSR is proposed. This allows the encoding of feedback polynomials to be done implicitly by the ordering of testcubes. An algorithm for the selection and ordering of feedback polynomials is presented.<br>Experimental results are provided for the ISCAS-85 and ISCAS-89 benchmark circuits to demonstrate the effectiveness of the scheme. The scheme allows an excellent trade-off between test data storage and test application time (number of test patterns) with a very small hardware overhead. We show the trade-off between test data storage and number of test patterns under the scheme.
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Aitken, Robert Campbell. "A hierarchical method of fault diagnosis with built-in self-test applications /." Thesis, McGill University, 1990. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=74545.
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The problem of fault diagnosis in digital circuits is composed of two sub-problems: Fault detection (identifying that a fault is present) and fault location (identifying the failure responsible for faulty behaviour). Tests using randomly or pseudo-randomly selected input stimuli have been suggested both as a means of reducing the costs associated with generating deterministic tests and as a means by which circuits could test themselves (built-in self-test). The majority of research into random testing has dealt only with its fault detection properties. Fault location has typically been treated as a dictionary search problem, or ignored altogether.<br>This dissertation proposes a new approach to fault location in randomly or pseudo-randomly tested digital circuits. Faults will be isolated by a hierarchical sequence of steps, each of which identifies a particular property of the fault which has occurred. The method uses available circuit information to aid in location. The advantages of this method include greatly reduced dictionary generation costs, the ability to locate a fault without searching an entire dictionary, and the ability to partially characterize unmodelled faults. In addition, a hierarchical approach allows dictionaries to be constructed in a demand-driven fashion, avoiding unnecessary work for faults which do not occur in practice, and reducing the costs of changes in the test set.<br>Sample applications of the proposed location technique are given, for use in both random compact testing and built-in self-test. Experimental results are presented to demonstrate the performance of the method.
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Gjermundnes, Øystein. "Exploiting Arithmetic Built-In-Self-Test Techniques for Path Delay Fault Testing." Doctoral thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2006. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-2149.
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<p>This thesis describes the implementation of a system for analyzing circuits with respect to their path-delay fault testability. The system includes a path-delay fault simulator and an ATPG for path-delay faults combined into a test tool. This test tool can run standalone on a single machine, or as one of several clients that communicate through a central server. The test tool is used in this thesis in order to evaluate the performance of 14 different test vector generators that can be used in various built-in self-test arrangements.</p><p>The test generators exploit pseudo-random stimuli generation. We have used six different strategies for weighting of input signals, and performed comprehensive experiments to evaluate the efficiency of the strategies. Each of the experiments typically consists of three phases:</p><p>• In the first phase, the ATPG is used in order to find the K-longest nonrobust testable path-delay faults. The corresponding path numbers are then saved together with the corresponding test vector for later use. The paths constitute the target fault list during simulation. Experiments that consider all possible faults skip this phase.</p><p>• In the second phase, weights are generated for the weighted pseudorandom generators. These weights are stored for later use. This phase is skipped for experiments where the generator is unweighted.</p><p>• In the third phase the actual simulation takes place. In all experiments 10M single-input-change test patterns were applied and repeated ten times for each generator and circuit in order to cover some statistical variations. Only non-robust faults (including robust faults) were considered.</p><p>Two groups of pseudo-random generators have been evaluated. The first group, GA, consists of accumulator based pseudo-random generators. The second group, GT, consists of Mersenne twister based pseudo-random generators.</p><p>The result has shown that the GT group of pseudo-random patterns give marginally better results than the GA group. Since GA generators are much less computationally intensive, GA generators are reccommended over GT generators in practical applications. Experiments have also been conducted in order to evaluate the benefit of weighted stimuli compared to unweighted stimuli. The results show that test time can be reduced with up to 15 times for the circuits in the ISCAS’85 benchmark suite.</p><p>Based upon comprehensive experiments with various weighting schemes on ISCAS benchmarks, one can conclude that the following three-phase approach works well: First, generate test patterns to detect the K(20000) longest paths. Subsequently, compute weights for each input based upon the gennerated patterns. Finally, employ an accumulator based BIST scheme with the weights on non-robust path-delay faults.</p>
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Newalkar, Aditya. "Alternative techniques for Built-In Self-Test of Field Programmable Gate Arrays." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/master's/NEWALKAR_ADITYA_6.pdf.
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Gherman, Valentin. "Scalable deterministic logic built-in self-test." 2006. http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-27416.
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Zhang, Chaoming 1980. "Built-in self test of RF subsystems." Thesis, 2008. http://hdl.handle.net/2152/21908.
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With the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs.<br>text
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Wei, Chen-Jung, and 魏震榮. "Built-In-Self-Test for Embedded memories." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/31600621186037796464.
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碩士<br>國立中興大學<br>資訊科學研究所<br>87<br>Recently, integration of system into a chip becomes very popular. In testing of highly integrated chip, one difficult problem is embedded memory testing. It is hard to test embedded memory because direct controllability and observability are extremely low. To solve this problem, Built-In Self Test (BIST) technique is widely used in embedded memory testing.
Pseudo-random (PR) memory tests are tests which have the capability to detect any fault (defect) of any model, albeit with some probability less than 100%; the fault coverage is modular and depends on the test time, which makes them very attractive.
In this paper we describe a new method to improve the explicit memory test with word operations (DADWRD). By complement the written data, we could increase the probability of the detection. For the more, we modify the Markov chain of DADWRD to suitable our new algorithm. We prove that new method could reduce the test length coefficients, and the increase of area overhead is small.
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Zhao, Ann-Shen, and 趙安生. "Built-in Self Test for jitter measurement." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/30296290427134359925.
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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>93<br>Phase-locked loops (PLLs) are often served as clock generators and/or frequency synthesizers in a system on a chip (SoC). Since it is usually built inside the chip deeply, it is hard to test PLL directly by using automatic test equipments (ATEs). For a clock signal generated by a PLL, jitter is one of the specifications which are hardest to be test.
At the beginning of this thesis, we survey and investigate several built-in self-test (BIST) schemes used for jitter measurement in recent years. We also summarize pros, cons and challenges in practical implementation for these BIST schemes.
To accomplish the jitter measurement, it often needs a golden (jitter free) reference signal in many conventional BIST methods. However, it is hard to provide such ideal signal. Hence, we propose a BIST method which does not need an ideal reference clock. In this BIST method, we measure jitter and employ statistical analysis techniques to calibrate the measured data to achieve higher accuracy results.
Besides, we propose a BIST circuit based on the method developed previously. The BIST circuit mainly contains two building blocks: jitter amplifier and ring oscillator based jitter calculating circuit. Jitter amplifier is used to linearly amplify tiny time intervals to enhance the measuring resolution. Ring oscillator based jitter calculating circuit is used to collect the timing data and build the histogram of jitter to estimate the amount of jitter. In contrast to conventional BIST methods, the proposed BIST scheme can remove the extra jitter generated by the built-in ring oscillator itself to obtain more accurate measuring results by using linear jitter amplifier and simple statistical techniques. All main function blocks proposed in this thesis are all verified and simulated with TSMC 0.18 �慆 process.
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Lin, Yann-Horng, and 林燕宏. "Low Power Built In Self Test Design." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/24097221389448540102.
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碩士<br>國立中興大學<br>資訊科學研究所<br>89<br>BIST has emerged as a promising solution to the SOC testing problem. Most Test Pattern Generators (TPGs) used in BIST generate pseudorandom test patterns, which have low correlation between consecutive patterns and thus maximize power consumption in the circuit under test. This may damage the tested chips, as well as create reliability problem if the BIST is to be used frequently in system test.
This thesis proposes a new adjustable TPG structure that is targeted to reduce the switching activity during BIST test sessions.The proposed TPG structure consists of two parts, a LFSR and a Counter. The LFSR is driven by a slow clock whose speed is 1/2k of the normal clock, which is used to drive the Counter.
The proposed method is flexible, in that designers can select appropriate test structure for the given level of switching activity. The experimental results show that a 22%-84% reduction in switching activity can be achieved with no loss of fault coverage and the test length is about 10%-120% comparing with the original test sequence.
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Hsu, An-Chi, and 許安琪. "A Novel Test Pattern Generator for Built-In-Self-Test." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/94567365087518651005.
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碩士<br>義守大學<br>電子工程學系<br>91<br>ABSTRACT
The built-in-self-test (BIST) is a powerful test strategy for very large scale integrated circuit. The test pattern generator is a critical portion of an efficient BIST structure.
In this paper, we blend the weighted-random-pattern generator and controllable-linear-feedback-shift register to develop a novel test pattern generator for BIST. The whole testing is performed in two phases. The weighted-random-pattern generator generates the test patterns to drop some of the faults from the fault list during the first phase fault simulations. During the second-phase fault simulations, remain faults will be tested by the test patterns generated by the controllable-linear-feedback-shift register. We adopt controllable-linear-feedback-shift register to generate the deterministic patterns instead of modifying the configuration of the weighted-random-pattern generator such that a better fault coverage can be achieved with a lower hardware cost and shorter test length.
(Keywords: BIST; WRPG; CLFSR; Fault Coverage; Test Pattern Length)