Journal articles on the topic 'Built-in selft test'
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P, Nagma, Ramachandran S, and Sathishkumar E. "Fault Testing and Diagnosis of Sram based FBGA using Built-In-Self-Test-Architecture." International Journal of Trend in Scientific Research and Development Volume-2, Issue-2 (2018): 717–30. http://dx.doi.org/10.31142/ijtsrd9415.
Full textZorian, Yervant. "Built-in self-test." Microelectronic Engineering 49, no. 1-2 (1999): 135–38. http://dx.doi.org/10.1016/s0167-9317(99)00434-7.
Full textMcCluskey, Edward. "Built-In Self-Test Techniques." IEEE Design & Test of Computers 2, no. 2 (1985): 21–28. http://dx.doi.org/10.1109/mdt.1985.294856.
Full textMcCluskey, Edward. "Built-In Self-Test Structures." IEEE Design & Test of Computers 2, no. 2 (1985): 29–36. http://dx.doi.org/10.1109/mdt.1985.294857.
Full textSeuring, Markus. "Combining Scan Test and Built-in Self Test." Journal of Electronic Testing 22, no. 3 (2006): 297–99. http://dx.doi.org/10.1007/s10836-006-8950-7.
Full textUngar, L. Y., and T. Ambler. "Economics of built-in self-test." IEEE Design & Test of Computers 18, no. 5 (2001): 70–79. http://dx.doi.org/10.1109/54.953274.
Full textAdham, S., M. Kassab, J. Rajski, and J. Tyszer. "Built-in self test of digital decimators." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 42, no. 7 (1995): 486–92. http://dx.doi.org/10.1109/82.401174.
Full textMir, S., L. Rufer, and A. Dhayni. "Built-in-self-test techniques for MEMS." Microelectronics Journal 37, no. 12 (2006): 1591–97. http://dx.doi.org/10.1016/j.mejo.2006.04.016.
Full textDeb, N., and R. D. Blanton. "Built-In Self-Test of MEMS Accelerometers." Journal of Microelectromechanical Systems 15, no. 1 (2006): 52–68. http://dx.doi.org/10.1109/jmems.2006.864239.
Full textSavir, Jacob, and Paul H. Bardell. "Built-In Self-Test: Milestones and Challenges." VLSI Design 1, no. 1 (1993): 23–44. http://dx.doi.org/10.1155/1993/81360.
Full textKonemann, B., B. Bennetts, N. Jarwala, and B. Nadeau-Dostie. "Built-in self-test: assuring system integrity." Computer 29, no. 11 (1996): 39–45. http://dx.doi.org/10.1109/2.544236.
Full textGloster, C. S., and F. Brglez. "Boundary scan with built-in self-test." IEEE Design & Test of Computers 6, no. 1 (1989): 36–44. http://dx.doi.org/10.1109/54.20388.
Full textPulukuri, Mary D., and Charles E. Stroud. "On Built-In Self-Test for Adders." Journal of Electronic Testing 25, no. 6 (2009): 343–46. http://dx.doi.org/10.1007/s10836-009-5114-6.
Full textQi, Dandan, and Jon C. Muzio. "Non-linear test pattern generators for built-in self-test." International Journal of Communication Networks and Distributed Systems 1, no. 2 (2008): 179. http://dx.doi.org/10.1504/ijcnds.2008.020259.
Full textCraig, G. L., C. R. Kine, and K. K. Saluja. "Test scheduling and control for VLSI built-in self-test." IEEE Transactions on Computers 37, no. 9 (1988): 1099–109. http://dx.doi.org/10.1109/12.2260.
Full textDaniels, R. Gary, and William C. Bruce. "Built-In Self-Test Trends in Motorola Microprocessors." IEEE Design & Test of Computers 2, no. 2 (1985): 64–71. http://dx.doi.org/10.1109/mdt.1985.294865.
Full textKumar, Kota Satish, Sivasankari S.A, Gaddam Vinay, Bhaskar S, and Bala Venkateswarlu.P. "Digital Technique for Analog Built-in Self-Test." IOSR journal of VLSI and Signal Processing 4, no. 4 (2014): 38–45. http://dx.doi.org/10.9790/4200-04433845.
Full textSteininger, Andreas. "Testing and built-in self-test – A survey." Journal of Systems Architecture 46, no. 9 (2000): 721–47. http://dx.doi.org/10.1016/s1383-7621(99)00041-7.
Full textRadecka, K., J. Rajski, and J. Tyszer. "Arithmetic built-in self-test for DSP cores." Computer Standards & Interfaces 20, no. 6-7 (1999): 473. http://dx.doi.org/10.1016/s0920-5489(99)91044-9.
Full textGala, M., D. Ross, K. Watson, B. Vasudevan, and P. Utama. "Built-in self test for C-testable ILA's." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14, no. 11 (1995): 1388–98. http://dx.doi.org/10.1109/43.469664.
Full textTreuer, Robert, Hideo Fujiwara, and Vinod Agarwal. "Implementing a Built-In Self-Test PLA Design." IEEE Design & Test of Computers 2, no. 2 (1985): 37–48. http://dx.doi.org/10.1109/mdt.1985.294859.
Full textRadecka, K., J. Rajski, and J. Tyszser. "Arithmetic built-in self-test for DSP cores." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16, no. 11 (1997): 1358–69. http://dx.doi.org/10.1109/43.663825.
Full textStojev, M. "Arithmetic built-in self-test for embedded systems." Microelectronics Journal 29, no. 12 (1998): 1045–46. http://dx.doi.org/10.1016/s0026-2692(98)80001-3.
Full textHortensius, P. D., R. D. McLeod, and B. W. Podaima. "Cellular automata circuits for built-in self-test." IBM Journal of Research and Development 34, no. 2.3 (1990): 389–405. http://dx.doi.org/10.1147/rd.342.0389.
Full textAgrawal, Vishwani D., Chih-Jen Lin, Paul W. Rutkowski, Shianling Wu, and Yervant Zorian. "Built-in Self-Test for Digital Integrated Circuits." AT&T Technical Journal 73, no. 2 (1994): 30–39. http://dx.doi.org/10.1002/j.1538-7305.1994.tb00576.x.
Full textHsu, C. L., Y. Lai, and S. W. Wang. "Built-In Self-Test for Phase-Locked Loops." IEEE Transactions on Instrumentation and Measurement 54, no. 3 (2005): 996–1002. http://dx.doi.org/10.1109/tim.2005.847343.
Full textRAJASHEKHARA, T. N. "Built-in self-test design of semiconductor memory." International Journal of Electronics 70, no. 3 (1991): 645–49. http://dx.doi.org/10.1080/00207219108921316.
Full textChen, Chien-In Henry. "Partitioning Techniques for Built-In Self-Test Design." VLSI Design 2, no. 3 (1994): 185–98. http://dx.doi.org/10.1155/1994/25656.
Full textSantos, M. B., and J. Paulo Teixeira. "Functional-oriented mask-based built-in self-test." IET Computers & Digital Techniques 1, no. 5 (2007): 491. http://dx.doi.org/10.1049/iet-cdt:20060073.
Full textDekker, R., F. Beenker, and L. Thijssen. "Realistic built-in self-test for static RAMs." IEEE Design & Test of Computers 6, no. 1 (1989): 26–34. http://dx.doi.org/10.1109/54.20387.
Full textIllman, R., and S. Clarke. "Built-in self-test of the Macrolan chip." IEEE Design & Test of Computers 7, no. 2 (1990): 29–40. http://dx.doi.org/10.1109/54.53043.
Full textGizopoulos, D., A. Paschalis, and Y. Zorian. "Effective built-in self test for Booth multipliers." IEEE Design & Test of Computers 15, no. 3 (1998): 105–11. http://dx.doi.org/10.1109/54.706041.
Full textCerny, E., E. M. Aboulhamid, G. Bois, and J. Cloutier. "Built-in self-test of a CMOS ALU." IEEE Design & Test of Computers 5, no. 4 (1988): 38–48. http://dx.doi.org/10.1109/54.7968.
Full textShrivastava, Sakshi, Sunil Malviya, and Neelesh Gupta. "Built in Self Test Architecture Using Logic Module." International Journal of VLSI Design & Communication Systems 8, no. 4 (2017): 25–34. http://dx.doi.org/10.5121/vlsic.2017.8403.
Full textNicolaidis, M. "Self-exercising checkers for unified built-in self-test (UBIST)." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 8, no. 3 (1989): 203–18. http://dx.doi.org/10.1109/43.21840.
Full textGroza, Voicu, Rami Abielmona, Mansour H. Assaf, Mohammed Elbadri, Mohammad El-Kadri, and Arkan Khalaf. "A Self-Reconfigurable Platform for Built-In Self-Test Applications." IEEE Transactions on Instrumentation and Measurement 56, no. 4 (2007): 1307–15. http://dx.doi.org/10.1109/tim.2007.900134.
Full textPradhan, D. K., and M. Chatterjee. "GLFSR-a new test pattern generator for built-in-self-test." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18, no. 2 (1999): 238–47. http://dx.doi.org/10.1109/43.743744.
Full textMohamed. "Low Transition Test Pattern Generator Architecture for Built-in-Self-Test." American Journal of Applied Sciences 9, no. 9 (2012): 1396–406. http://dx.doi.org/10.3844/ajassp.2012.1396.1406.
Full textMukherjee, N., T. J. Chakraborty, and R. Karri. "Built in self test: a complete test solution for telecommunication systems." IEEE Communications Magazine 37, no. 6 (1999): 72–78. http://dx.doi.org/10.1109/35.769277.
Full textKim, Jin-Wan, and Hoon Chang. "TLC NAND-type Flash Memory Built-in Self Test." Journal of the Institute of Electronics and Information Engineers 51, no. 12 (2014): 72–82. http://dx.doi.org/10.5573/ieie.2014.51.12.072.
Full textDufaza, Christian. "Theoretical properties of LFSRs for built-in self test." Integration 25, no. 1 (1998): 17–35. http://dx.doi.org/10.1016/s0167-9260(98)00005-4.
Full textWurtz, L. T. "Built-in self-test structure for mixed-mode circuits." IEEE Transactions on Instrumentation and Measurement 42, no. 1 (1993): 25–29. http://dx.doi.org/10.1109/19.206674.
Full textHAN, J. "An Effective Built-In Self-Test for Chargepump PLL." IEICE Transactions on Electronics E88-C, no. 8 (2005): 1731–33. http://dx.doi.org/10.1093/ietele/e88-c.8.1731.
Full textStaszewski, Robert Bogdan, Imran Bashir, and Oren Eliezer. "RF Built-in Self Test of a Wireless Transmitter." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 2 (2007): 186–90. http://dx.doi.org/10.1109/tcsii.2006.886202.
Full textDreibelbis, J., J. Barth, H. Kalter, and R. Kho. "Processor-based built-in self-test for embedded DRAM." IEEE Journal of Solid-State Circuits 33, no. 11 (1998): 1731–40. http://dx.doi.org/10.1109/4.726568.
Full textYamada, Teruhiko, and Hiroshi Nakajima. "Pseudorandom pattern built-in self-test for embedded rams." Systems and Computers in Japan 21, no. 12 (1990): 1–8. http://dx.doi.org/10.1002/scj.4690211201.
Full textOrtega, J., A. Prieto, A. Lloris, and F. Pelayo. "Universal built-in self-test procedure for CMOS PLA's." IEEE Transactions on Circuits and Systems 38, no. 8 (1991): 941–45. http://dx.doi.org/10.1109/31.85635.
Full textMcAnney, W. H., and J. Savir. "Built-in checking of the correct self-test signature." IEEE Transactions on Computers 37, no. 9 (1988): 1142–45. http://dx.doi.org/10.1109/12.2268.
Full textReddy, S. M., K. K. Saluja, and M. G. Karpovsky. "A data compression technique for built-in self-test." IEEE Transactions on Computers 37, no. 9 (1988): 1151–56. http://dx.doi.org/10.1109/12.2271.
Full textAgrawal, V. D., C. R. Kime, and K. K. Saluja. "A tutorial on built-in self-test. I. Principles." IEEE Design & Test of Computers 10, no. 1 (1993): 73–82. http://dx.doi.org/10.1109/54.199807.
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