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Relevant bibliographies by topics / Cache Coherence Problem

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Academic literature on the topic 'Cache Coherence Problem'

Author: Grafiati

Published: 11 September 2023

Last updated: 31 July 2025

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Journal articles on the topic "Cache Coherence Problem"

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Somarouthu, Sruthi. "Demystifying Cache Coherency in Modern Multiprocessor Systems." European Journal of Computer Science and Information Technology 13, no. 37 (2025): 25–35. https://doi.org/10.37745/ejcsit.2013/vol13n372535.

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Cache coherency remains a fundamental architectural challenge in modern multi-core processors, balancing data consistency with performance. This article examines the intricate mechanics of cache coherence protocols, from the basic principles of memory hierarchy to advanced implementations like MESIF, MOESI and token coherence. The exploration begins with the core problem of maintaining consistent data views across distributed caches, continues through implementation mechanisms, including snooping and directory-based approaches, and addresses critical performance considerations such as coherenc

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Shmeylin, B. Z., and E. A. Alekseeva. "THE PROBLEM OF PROVIDING CACHE COHERENCE IN MULTIPROCESSOR SYSTEMS WITH MANY PROCESSORS." Issues of radio electronics, no. 5 (May 20, 2018): 47–53. http://dx.doi.org/10.21778/2218-5453-2018-5-47-53.

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In this paper the tasks of managing the directory in coherence maintenance systems in multiprocessor systems with a large number of processors are solved. In microprocessor systems with a large number of processors (MSLP) the problem of maintaining the coherence of processor caches is significantly complicated. This is due to increased traffic on the memory buses and increased complexity of interprocessor communications. This problem is solved in various ways. In this paper, we propose the use of Bloom filters used to accelerate the determination of an element’s belonging to a certain array. I

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Journal, Baghdad Science. "Cache Coherence Protocol Design and Simulation Using IES (Invalid Exclusive read/write Shared) State." Baghdad Science Journal 14, no. 1 (2017): 219–30. http://dx.doi.org/10.21123/bsj.14.1.219-230.

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To improve the efficiency of a processor in recent multiprocessor systems to deal with data, cache memories are used to access data instead of main memory which reduces the latency of delay time. In such systems, when installing different caches in different processors in shared memory architecture, the difficulties appear when there is a need to maintain consistency between the cache memories of different processors. So, cache coherency protocol is very important in such kinds of system. MSI, MESI, MOSI, MOESI, etc. are the famous protocols to solve cache coherency problem. We have proposed i

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أنيس القردوح, عبدالحميد الكواش, and عبدالمحسن البنداق. "Simulation Cache Coherence Protocols in Multicore Processors." Journal of Pure & Applied Sciences 21, no. 4 (2022): 285–89. http://dx.doi.org/10.51984/jopas.v21i4.2239.

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The cache coherence problem is the challenge of keeping multiple cache synchronized when one of the processors update its local copy of data which is shared among multiple cache. This paper discusses several different varieties of cache coherence protocols including with their pros and cons, and using simulation technique it will address this problem and compare between two protocols that use to solve it: Directory-based protocol and Snooping protocol. Simulation results have shown that snooping based systems are appropriate for high bandwidth systems while directory-based cache coherence prot

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Jalil, Luma Fayeq, Maha Abdul kareem H. Al-Rawi, and Abeer Diaa Al-Nakshabandi. "Cache coherence protocol design using VMSI (Valid Modified Shared Invalid) states." Journal of University of Human Development 3, no. 1 (2017): 274. http://dx.doi.org/10.21928/juhd.v3n1y2017.pp274-281.

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We have proposed in this research the design of a new protocol named VMSI coherence protocol in the cache in order to solve the problem of coherence which is the incompatibility of data between caches that appeared in recent multiprocessors system through the operations of reading and writing. The main purpose of this protocol is to increase processor efficiency by reducing traffic between processor and memory that have been achieved through the removal of the write back to the main memory in the case of reading or writing of shared caches because it depends on existing directory inside that c

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Guo, Yu Feng, Ming Zhang, and Rui Gong. "I/O Coherence Faulty Tolerance Method for Multi-Core Processor Based on Retry." Applied Mechanics and Materials 427-429 (September 2013): 2830–33. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.2830.

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I/O Consistency problem is one of the key issues which Multi-Cores Processor design must face. With increasing of core number and complicating of cache level, the probability of I/O coherence packets blocked would increase, which would decrease I/O system efficiency significantly. An I/O coherence maintaining method based on retransmission is proposed to improve reliability of the I/O coherence protocol. Experimental results demonstrate that this method can enhance the robustness of I/O coherence protocol effectively.

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Zhao, Jia, and Watanabe. "Router-integrated Cache Hierarchy Design for Highly Parallel Computing in Efficient CMP Systems." Electronics 8, no. 11 (2019): 1363. http://dx.doi.org/10.3390/electronics8111363.

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In current Chip Multi-Processor (CMP) systems, data sharing existing in cache hierarchy acts as a critical issue which costs plenty of clock cycles for maintaining data coherence. Along with the integrated core number increasing, the only shared cache serves too many processing threads to maintain sharing data efficiently. In this work, an enhanced router network is integrated within the private cache level for fast interconnecting sharing data accesses existing in different threads. All sharing data in private cache level can be classified into seven access types by experimental pattern analy

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Khushbu, Lalwani* &. Mayuri Chawla. "HIGH THROUGHPUT CACHE CONTROLLER USING VHDL & IT'S FPGA IMPLEMENTATION." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 10 (2017): 346–53. https://doi.org/10.5281/zenodo.1012539.

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The world is now using multicore processors for development, research or real-time device purposes as they provide a better processing leading to better performance. This has attracted a number of researchers as the processors are embedded on a single chip and the performance can be easily amplified by saving the space, reducing power consumption, reducing the delay of the system. In the past years, a lot of technique shave emerged which proposes the optimization. One such important scope of optimization is the cache handling which has a considerable effect on the power, performance, and area

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Walker, Marilyn A. "Vers un modèle de l’interaction du Centrage avec la structure globale du discours." Verbum 22, no. 1 (2000): 31–58. https://doi.org/10.3406/verbu.2000.1635.

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Centering was formulated as a model of the relationship between attentional state, the form of referring expressions, and the coherence of an utterance within a discourse segment. In this paper, I argue that the restriction of Centering to operating within a discourse segment should be abandoned in order to integrate it within a model of global discourse structure, using the cache model of attentional state in place of Grosz & Sidner’s stack model. The article adduces data from naturally-occurring texts which illustrate three major types of problem for the Grosz & Sidner model, but whi

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Zhu, Wei, and Xiaoyang Zeng. "Decision Tree-Based Adaptive Reconfigurable Cache Scheme." Algorithms 14, no. 6 (2021): 176. http://dx.doi.org/10.3390/a14060176.

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Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the pr

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Dissertations / Theses on the topic "Cache Coherence Problem"

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Archibald, James K. "The cache coherence problem in shared-memory multiprocessors /." Thesis, Connect to this title online; UW restricted, 1987. http://hdl.handle.net/1773/6955.

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ARORA, POOJA. "Cache Coherence in Multi Processors Architecture." Thesis, 2015. http://dspace.dtu.ac.in:8080/jspui/handle/repository/14290.

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Appropriate solution to illustrious Cache Coherence Problem in shared memory multiprocessors system is one of the crucial issue for improving system performance and scalability. In this paper we have surveyed various cache coherence mechanisms in shared memory multiprocessor. Various hardware based and software based protocol have been investigated in depth including recent protocols. We have concluded that hardware based cache coherence protocol are better than software based protocol according to presently available protocols, but hardware based protocol have added the cost to implemen

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HUANG, WEN-GIANG, and 黃文強. "Two new protocols for cache coherence problem." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/80242125272378726036.

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Books on the topic "Cache Coherence Problem"

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Milo, Tomašević, and Milutinović Veljko, eds. The Cache-coherence problem in shared-memory multiprocessors: Hardware solutions. IEEE Computer Society Press, 1993.

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Tartalja, Igor. The cache coherence problem in shared-memory multiprocessors: Software solutions. IEEE Computer Society Press, 1996.

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(Editor), Milo Tomasevic, and Veljko Milutinovic (Editor), eds. The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions. Ieee Computer Society, 1993.

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(Editor), Veljko Milutinovic, and Milo Tomasevic (Editor), eds. The Cache-Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions. Institute of Electrical & Electronics Enginee, 1999.

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Book chapters on the topic "Cache Coherence Problem"

1

Cortes, Toni, Sergi Girona, and Jesús Labarta. "Avoiding the cache-coherence problem in a parallel/distributed file system." In High-Performance Computing and Networking. Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/bfb0031657.

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Moorthi, M. Narayana, and R. Manjula. "Challenges Faced in Enhancing the Performance and Scalability in Parallel Computing Architecture." In Advances in Computer and Electrical Engineering. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-9479-8.ch010.

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Now a day the architecture of high performance systems are improving with more and more processor cores on the chip. This has both benefits as well as challenges. The benefit is running more task simultaneously which reduces the running time of the program or application. The challenges are what is the maximum limit of the number of cores in the given chip, how the existing and future software will make use of all the cores, what parallel programming language to choose, what are the memory and cache coherence issues involved when we increase the number of cores, how to solve the power and perf

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"Design Issues of a Cooperative Cache with no Coherence Problems." In High Performance Mass Storage and Parallel I/O. IEEE, 2009. http://dx.doi.org/10.1109/9780470544839.ch18.

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Conference papers on the topic "Cache Coherence Problem"

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Cheng, L., and A. A. Sawchuk. "Optical solutions for cache memories in parallel computers." In OSA Annual Meeting. Optica Publishing Group, 1993. http://dx.doi.org/10.1364/oam.1993.mzz.1.

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A cache is a high speed memory located between processors and main memory to fill the speed gap between them. In a loosely coupled parallel computer, each processor has its own cache memory. The processor accesses information from its cache memory, which stores information obtained from the main memory through an interconnection network. A major challenge in this system is to keep the data in all the caches consistent with that in main memory. This is referred to as the cache coherence problem. One solution is to have a bus between the caches, and supply each cache with a controller which list

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Mittal, Shaily, and Nitin. "A New Approach to Directory Based Solution for Cache Coherence Problem." In 2014 3rd International Conference on Eco-friendly Computing and Communication Systems (ICECCS). IEEE, 2014. http://dx.doi.org/10.1109/eco-friendly.2014.77.

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Li, Qiang. "SCI Lamp for Multimedia Applications." In ASME 1994 International Computers in Engineering Conference and Exhibition and the ASME 1994 8th Annual Database Symposium collocated with the ASME 1994 Design Technical Conferences. American Society of Mechanical Engineers, 1994. http://dx.doi.org/10.1115/cie1994-0474.

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Abstract Multimedia technology has become widely available and it has tremendous potential. As computers getting faster every day, multimedia applications are reaching new ground constantly. However, a fundamental problem of multimedia systems is the interprocessor/intermachine communication speed. In this paper, we introduce a platform based on the Scalable Coherent Interface (SCI, ANSI/IEEE std 1596). The system can be physically distributed but logically closely coupled. All processors/machines in an SCI system shared physical memory and cache coherence is maintained even among remote proce

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Cortes, Toni, Sergi Girona, and Jesús Labarta. "Design issues of a cooperative cache with no coherence problems." In the fifth workshop. ACM Press, 1997. http://dx.doi.org/10.1145/266220.266224.

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Hytopoulos, Evangelos, Mark D. Kremenetsky, Ramesh Andra, Richard Sun, and Stan Posey. "Scalability Studies on a cc-NUMA Computer Architecture for Large Automotive Simulations." In ASME 1998 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 1998. http://dx.doi.org/10.1115/imece1998-0994.

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Abstract The maturity of the Computational Fluid Dynamics methods and the increasing computational power of today’s computers have allowed the automotive industry to incorporate the CFD technology in several stages of the design process. As the application of the CFD technology is moving from the component level analysis to the system level, the complexity and the size of the models increase continuously. Successful simulation requires synergy between CAD, grid generation, and solvers. The requirement for shorter design cycle has put severe limitations on the turnaround time of the numerical s

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