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Journal articles on the topic 'Cache Coherence Problem'

Author: Grafiati

Published: 11 September 2023

Last updated: 31 July 2025

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1

Somarouthu, Sruthi. "Demystifying Cache Coherency in Modern Multiprocessor Systems." European Journal of Computer Science and Information Technology 13, no. 37 (2025): 25–35. https://doi.org/10.37745/ejcsit.2013/vol13n372535.

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Cache coherency remains a fundamental architectural challenge in modern multi-core processors, balancing data consistency with performance. This article examines the intricate mechanics of cache coherence protocols, from the basic principles of memory hierarchy to advanced implementations like MESIF, MOESI and token coherence. The exploration begins with the core problem of maintaining consistent data views across distributed caches, continues through implementation mechanisms, including snooping and directory-based approaches, and addresses critical performance considerations such as coherenc

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2

Shmeylin, B. Z., and E. A. Alekseeva. "THE PROBLEM OF PROVIDING CACHE COHERENCE IN MULTIPROCESSOR SYSTEMS WITH MANY PROCESSORS." Issues of radio electronics, no. 5 (May 20, 2018): 47–53. http://dx.doi.org/10.21778/2218-5453-2018-5-47-53.

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In this paper the tasks of managing the directory in coherence maintenance systems in multiprocessor systems with a large number of processors are solved. In microprocessor systems with a large number of processors (MSLP) the problem of maintaining the coherence of processor caches is significantly complicated. This is due to increased traffic on the memory buses and increased complexity of interprocessor communications. This problem is solved in various ways. In this paper, we propose the use of Bloom filters used to accelerate the determination of an element’s belonging to a certain array. I

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Journal, Baghdad Science. "Cache Coherence Protocol Design and Simulation Using IES (Invalid Exclusive read/write Shared) State." Baghdad Science Journal 14, no. 1 (2017): 219–30. http://dx.doi.org/10.21123/bsj.14.1.219-230.

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To improve the efficiency of a processor in recent multiprocessor systems to deal with data, cache memories are used to access data instead of main memory which reduces the latency of delay time. In such systems, when installing different caches in different processors in shared memory architecture, the difficulties appear when there is a need to maintain consistency between the cache memories of different processors. So, cache coherency protocol is very important in such kinds of system. MSI, MESI, MOSI, MOESI, etc. are the famous protocols to solve cache coherency problem. We have proposed i

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أنيس القردوح, عبدالحميد الكواش, and عبدالمحسن البنداق. "Simulation Cache Coherence Protocols in Multicore Processors." Journal of Pure & Applied Sciences 21, no. 4 (2022): 285–89. http://dx.doi.org/10.51984/jopas.v21i4.2239.

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The cache coherence problem is the challenge of keeping multiple cache synchronized when one of the processors update its local copy of data which is shared among multiple cache. This paper discusses several different varieties of cache coherence protocols including with their pros and cons, and using simulation technique it will address this problem and compare between two protocols that use to solve it: Directory-based protocol and Snooping protocol. Simulation results have shown that snooping based systems are appropriate for high bandwidth systems while directory-based cache coherence prot

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Jalil, Luma Fayeq, Maha Abdul kareem H. Al-Rawi, and Abeer Diaa Al-Nakshabandi. "Cache coherence protocol design using VMSI (Valid Modified Shared Invalid) states." Journal of University of Human Development 3, no. 1 (2017): 274. http://dx.doi.org/10.21928/juhd.v3n1y2017.pp274-281.

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We have proposed in this research the design of a new protocol named VMSI coherence protocol in the cache in order to solve the problem of coherence which is the incompatibility of data between caches that appeared in recent multiprocessors system through the operations of reading and writing. The main purpose of this protocol is to increase processor efficiency by reducing traffic between processor and memory that have been achieved through the removal of the write back to the main memory in the case of reading or writing of shared caches because it depends on existing directory inside that c

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6

Guo, Yu Feng, Ming Zhang, and Rui Gong. "I/O Coherence Faulty Tolerance Method for Multi-Core Processor Based on Retry." Applied Mechanics and Materials 427-429 (September 2013): 2830–33. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.2830.

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I/O Consistency problem is one of the key issues which Multi-Cores Processor design must face. With increasing of core number and complicating of cache level, the probability of I/O coherence packets blocked would increase, which would decrease I/O system efficiency significantly. An I/O coherence maintaining method based on retransmission is proposed to improve reliability of the I/O coherence protocol. Experimental results demonstrate that this method can enhance the robustness of I/O coherence protocol effectively.

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7

Zhao, Jia, and Watanabe. "Router-integrated Cache Hierarchy Design for Highly Parallel Computing in Efficient CMP Systems." Electronics 8, no. 11 (2019): 1363. http://dx.doi.org/10.3390/electronics8111363.

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In current Chip Multi-Processor (CMP) systems, data sharing existing in cache hierarchy acts as a critical issue which costs plenty of clock cycles for maintaining data coherence. Along with the integrated core number increasing, the only shared cache serves too many processing threads to maintain sharing data efficiently. In this work, an enhanced router network is integrated within the private cache level for fast interconnecting sharing data accesses existing in different threads. All sharing data in private cache level can be classified into seven access types by experimental pattern analy

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Khushbu, Lalwani* &. Mayuri Chawla. "HIGH THROUGHPUT CACHE CONTROLLER USING VHDL & IT'S FPGA IMPLEMENTATION." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 10 (2017): 346–53. https://doi.org/10.5281/zenodo.1012539.

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The world is now using multicore processors for development, research or real-time device purposes as they provide a better processing leading to better performance. This has attracted a number of researchers as the processors are embedded on a single chip and the performance can be easily amplified by saving the space, reducing power consumption, reducing the delay of the system. In the past years, a lot of technique shave emerged which proposes the optimization. One such important scope of optimization is the cache handling which has a considerable effect on the power, performance, and area

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Walker, Marilyn A. "Vers un modèle de l’interaction du Centrage avec la structure globale du discours." Verbum 22, no. 1 (2000): 31–58. https://doi.org/10.3406/verbu.2000.1635.

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Centering was formulated as a model of the relationship between attentional state, the form of referring expressions, and the coherence of an utterance within a discourse segment. In this paper, I argue that the restriction of Centering to operating within a discourse segment should be abandoned in order to integrate it within a model of global discourse structure, using the cache model of attentional state in place of Grosz & Sidner’s stack model. The article adduces data from naturally-occurring texts which illustrate three major types of problem for the Grosz & Sidner model, but whi

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10

Zhu, Wei, and Xiaoyang Zeng. "Decision Tree-Based Adaptive Reconfigurable Cache Scheme." Algorithms 14, no. 6 (2021): 176. http://dx.doi.org/10.3390/a14060176.

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Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the pr

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11

Li, Yongjian, Bohua Zhan, and Jun Pang. "Mechanizing the CMP Abstraction for Parameterized Verification." Proceedings of the ACM on Programming Languages 8, OOPSLA1 (2024): 1324–50. http://dx.doi.org/10.1145/3649858.

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Parameterized verification is a challenging problem that is known to be undecidable in the general case. ‍is a widely-used method for parameterized verification, originally proposed by Chou, Mannava and Park in 2004. It involves abstracting the protocol to a small fixed number of nodes, and strengthening by auxiliary invariants to refine the abstraction. In most of the existing applications of CMP, the abstraction and strengthening procedures are carried out manually, which can be tedious and error-prone. Existing theoretical justification of the ‍method is also done at a high level, without d

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Chekhmestruk, Roman Y., Pavlo I. Mykhaylov, and Sergey I. Vyatkin. "METHOD FOR CALCULATING THE REFLECTION FUNCTION OF GLOBAL ILLUMINATION WITH PERTURBATION FUNCTIONS." Herald of Advanced Information Technology 4, no. 1 (2021): 47–56. http://dx.doi.org/10.15276/hait.01.2021.4.

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The advent of new hardware and the ever-increasing demands on the complexity of scenes are forcing the development of new approaches for calculating lighting. Modern visualization requires not only photorealistic, but also physically correct calculation of lighting. The core of any algorithm for calculating global illumination is the calculation of the illumination integral over the hemisphere.The aim of the work is to develop an effective visualization method based on the radiance caching and reprojection.This paper presents a modified method that eliminates the shortcomings of the reprojecti

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13

Tian, Yong Hong, and Guang Jian Chen. "A Review of Researches on Cache Coherence Protocols for Multi-Core Processor." Advanced Materials Research 933 (May 2014): 740–43. http://dx.doi.org/10.4028/www.scientific.net/amr.933.740.

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Multi-core processor parallels two or more computing core in a single processor to enhance computational capability. Plenty of former researches are focused on CMP (Chip multi-processor), the most typical structure of multi-core processor. Thus deign of cache coherence, in particular, is one of the primary problems beyond other researches about CMP. In this paper, cache coherence protocol of CMP is fully presented, along with its advantages and disadvantages. Finally, some edging issues of cache coherence protocols are addressed in this paper.

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14

ALKOWAILEET, WAIL Y., DAVID CARRILLO-CISNEROS, ROBERT V. LIM, and ISAAC D. SCHERSON. "NUMA-Aware Multicore Matrix Multiplication." Parallel Processing Letters 24, no. 04 (2014): 1450006. http://dx.doi.org/10.1142/s0129626414500066.

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A user-level scheduling along with a specific data alignment for matrix multiplication in cache-coherent Non-Uniform Memory Access (ccNUMA) architectures is presented. Addressing the data locality problem that could occur in such systems potentially alleviates memory bottlenecks. We show experimentally that an agnostic thread scheduler (e.g., OpenMP 3.1) from the data placement on a ccNUMA machine produces a high number of cache-misses. To overcome this memory contention problem, we show how proper memory mapping and scheduling manage to tune an existing matrix multiplication implementation an

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15

Subrahmanya, Bhat, and K. R. Kamath Dr. "DIRECTORY BASED CACHE COHERENCY, ORGANIZATION, OPERATIONS AND CHALLENGES IN IMPLEMENTATION - STUDY." International Journal of Advanced Trends in Engineering and Technology 1, no. 1 (2016): 30–33. https://doi.org/10.5281/zenodo.225696.

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Todays systems are designed with Multi Core Architecture. The idea behind this is to achieve high system throuput. Once the Processor clock speed reached its saturation, designers opted for having multiple cores. Each Core or Processor equipped with their own private cache memory. But under Chip Multiprocessor, where all the processor have access to shared memory, having respective cache memory will result with Cache Coherency Problem. In Directory Protocol, for each block of data there is a directory entry that contains a number of pointers. The purpose of this number is to mention the locati

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16

CHONG, FREDERIC T., and ANANT AGARWAL. "SHARED MEMORY VERSUS MESSAGE PASSING FOR ITERATIVE SOLUTION OF SPARSE, IRREGULAR PROBLEMS." Parallel Processing Letters 09, no. 01 (1999): 159–70. http://dx.doi.org/10.1142/s0129626499000177.

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The benefits of hardware support for shared memory versus those for message passing are difficult to evaluate without an in-depth study of real applications on a common platform. We evaluate the communication mechanisms of the MIT Alewife machine, a multiprocessor which provides integrated cache-coherent shared memory, massage passing, and DMA. We perform this evaluation with "best-effort" implementations which solve several sparse, irregular benchmark problems with a preconditioned conjugate gradient sparse matrix solver (ICCG). We find that machines with fast global memory operations do not

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17

Jayanti, Prasad, and Siddhartha Jayanti. "Deterministic Constant-Amortized-RMR Abortable Mutex for CC and DSM." ACM Transactions on Parallel Computing 8, no. 4 (2021): 1–26. http://dx.doi.org/10.1145/3490559.

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The abortable mutual exclusion problem, proposed by Scott and Scherer in response to the needs in real-time systems and databases, is a variant of mutual exclusion that allows processes to abort from their attempt to acquire the lock. Worst-case constant remote memory reference algorithms for mutual exclusion using hardware instructions such as Fetch&Add or Fetch&Store have long existed for both cache coherent (CC) and distributed shared memory multiprocessors, but no such algorithms are known for abortable mutual exclusion. Even relaxing the worst-case requirement to amortized, algori

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18

Arribas Cacha, Antonio. "Valoración Clínica enfermera." Conocimiento Enfermero 2, no. 05 (2019): 3–4. http://dx.doi.org/10.60108/ce.82.

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Que la investigación supone la profundización sistematizada en el conocimiento de un determinado aspecto de una temática que permite obtener resultados y conclusiones seguras y fiables, es un hecho conocido y aceptado de manera general. Que este es el motivo por el que la investigación debe seguir los principios establecidos en el método científico, incorporando la necesaria seriedad y rigurosidad requerida en el desarrollo de todos los pasos, es también una realidad plasmada: “La investigación es una búsqueda de conocimiento ordenada, coherente, de reflexión analítica y confrontación continua

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19

Alkhamisi, Khalid. "Cache Coherence issues and Solution: A Review." International Journal of Information Systems and Computer Technologies 1, no. 2 (2022). http://dx.doi.org/10.58325/ijisct.001.02.0030.

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Computer systems are extensively being used in today’s era and the advancement in computer systems has led to the evolution of various technologies. As the efficiency of the computer systems is to be enhanced, the usage of cache memory becomes a must. The cache memory problems occur when multiprocessor systems are used. When multiple processors are processors share a common memory pool, the problem of cache coherence occurs. Cache coherence is a state in which the cache memories of the processors must stay in coherence with each other. The data should be updated in all the cache systems. Vario

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20

Gómez-Luna, Juan, Ezequiel Herruzo, and José Ignacio Benavides. "MESI Cache Coherence Simulator for Teaching Purposes." CLEI Electronic Journal 12, no. 1 (2009). http://dx.doi.org/10.19153/cleiej.12.1.5.

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Nowadays, the computational systems (multi and uniprocessors) need to avoid the cachecoherence problem. There are some techniques to solve this problem. The MESI cachecoherence protocol is one of them. This paper presents a simulator of the MESI protocolwhich is used for teaching the cache memory coherence on the computer systems withhierarchical memory system and for explaining the process of the cache memory location inmultilevel cache memory systems. The paper shows a description of the course in which thesimulator is used, a short explanation about the MESI protocol and how the simulatorwo

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21

Sandu, Roman, and Alexandr Shcherbakov. "GPU Cache Flush Minimization In Render Graph Systems." Journal of WSCG 32, no. 1-2 (2024). http://dx.doi.org/10.24132/jwscg.2024.8.

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Modern graphics APIs expose control over the infamously non-coherent GPU caches to application programmers through the mechanisms of pipeline barriers and render passes. A developer is then asked to group together their GPU computations based on memory access patterns such that cache flushes and invalidations are minimized, but render graph systems enable automation of this process. In this paper, we study the problem of finding an optimal execution order for a frame graph to minimize the amount of render pass breaks, which in turn minimizes cache control operations. We formulate and analyze a

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22

Han, Shaopu, and Yanfeng Jiang. "Advanced hybrid MRAM based novel GPU cache system for graphic processing with high efficiency." AIP Advances 14, no. 1 (2024). http://dx.doi.org/10.1063/9.0000721.

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With the rapid development of portable computing devices and users’ demand for high-quality graphics rendering, embedded Graphics Processing Units (GPU) systems for graphics processing are increasingly turning into a key component of computer architecture to enhance computability. The cache system based on traditional static random access memory (SRAM) plays a crucial role in GPUs. But high leakage, low lifetime and poor integration problems deeply plague the science and engineering field. In the paper, a novel magnetic random access memory (MRAM) based cache architecture of GPU systems is pro

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23

Francisco, Munoz Martinez, and Eugenio Acacio Sanchez Manuel. "Influencia de la Memoria en el Rendimiento de una Arquitectura GPGPU." Jornadas Sarteco 2017, September 19, 2017, 6. https://doi.org/10.5281/zenodo.896098.

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La GPU es un dispositivo con gran potencial de rendimiento para la ejecución de aplicaciones de física, medicina, biología, etc. Aun así, dista mucho de ser perfecta y uno de los puntos principales donde se produce esa imperfección es en la jerarquía de memoria. La gran cantidad de hilos ejecutándose sobre este dispositivo genera una exponencial cantidad de accesos a memoria, provocando que las cachés y la memoria principal se ahoguen, actuando como cuellos de botella y evitando que la GPU alcance su máximo potencial. La investigación presentada a continuación realiza un análisis de la jerarqu

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