Relevant bibliographies by topics / Cache (Computers) Architecture

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Cache (Computers) Architecture'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

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Journal articles on the topic "Cache (Computers) Architecture"

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Yang, Q. "Performance of Cache Memories for Vector Computers." Journal of Parallel and Distributed Computing 19, no. 3 (1993): 163–78. http://dx.doi.org/10.1006/jpdc.1993.1102.

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CHONG, FREDERIC T., and ANANT AGARWAL. "SHARED MEMORY VERSUS MESSAGE PASSING FOR ITERATIVE SOLUTION OF SPARSE, IRREGULAR PROBLEMS." Parallel Processing Letters 09, no. 01 (1999): 159–70. http://dx.doi.org/10.1142/s0129626499000177.

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The benefits of hardware support for shared memory versus those for message passing are difficult to evaluate without an in-depth study of real applications on a common platform. We evaluate the communication mechanisms of the MIT Alewife machine, a multiprocessor which provides integrated cache-coherent shared memory, massage passing, and DMA. We perform this evaluation with "best-effort" implementations which solve several sparse, irregular benchmark problems with a preconditioned conjugate gradient sparse matrix solver (ICCG). We find that machines with fast global memory operations do not
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Wang, Nenzi, Hsin-Yi Chen, and Yu-Wen Chen. "Fluid-film lubrication computing with many-core processors and graphics processing units." Advances in Mechanical Engineering 10, no. 10 (2018): 168781401880471. http://dx.doi.org/10.1177/1687814018804719.

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The advancement of modern processors with many-core and large-cache may have little computational advantages if only serial computing is employed. In this study, several parallel computing approaches, using devices with multiple or many processor cores, and graphics processing units are applied and compared to illustrate the potential applications in fluid-film lubrication study. Two Reynolds equations and an air bearing optimum design are solved using three parallel computing paradigms, OpenMP, Compute Unified Device Architecture, and OpenACC, on standalone shared-memory computers. The newly
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Giraud, L. "Combining Shared and Distributed Memory Programming Models on Clusters of Symmetric Multiprocessors: Some Basic Promising Experiments." International Journal of High Performance Computing Applications 16, no. 4 (2002): 425–30. http://dx.doi.org/10.1177/109434200201600405.

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This note presents some experiments on different clusters of SMPs, where both distributed and shared memory parallel programming paradigms can be naturally combined. Although the platforms exhibit the same macroscopic memory organization, it appears that their individual overall performance is closely dependent on the ability of their hardware to efficiently exploit the local shared memory within the nodes. In that context, cache blocking strategy appears to be very important not only to get good performance out of each individual processor but mainly good performance out of the overall comput
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Huang, Xiaohui, Junqing Fan, Ze Deng, Jining Yan, Jiabao Li, and Lizhe Wang. "Efficient IoT Data Management for Geological Disasters Based on Big Data-Turbocharged Data Lake Architecture." ISPRS International Journal of Geo-Information 10, no. 11 (2021): 743. http://dx.doi.org/10.3390/ijgi10110743.

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Multi-source Internet of Things (IoT) data, archived in institutions’ repositories, are becoming more and more widely open-sourced to make them publicly accessed by scientists, developers, and decision makers via web services to promote researches on geohazards prevention. In this paper, we design and implement a big data-turbocharged system for effective IoT data management following the data lake architecture. We first propose a multi-threading parallel data ingestion method to ingest IoT data from institutions’ data repositories in parallel. Next, we design storage strategies for both inges
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DRACH, N., A. GEFFLAUT, P. JOUBERT, and A. SEZNEC. "ABOUT CACHE ASSOCIATIVITY IN LOW-COST SHARED MEMORY MULTI-MICROPROCESSORS." Parallel Processing Letters 05, no. 03 (1995): 475–87. http://dx.doi.org/10.1142/s0129626495000436.

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Sizes of on-chip caches on current commercial microprocessors range from 16 Kbytes to 36 Kbytes. These microprocessors can be directly used in the design of a low cost single-bus shared memory multiprocessors without using any second-level cache. In this paper, we explore the viability of such a multi-microprocessor. Simulations results clearly establish that performance of such a system will be quite poor if on-chip caches are direct-mapped. On the other hand, when the on-chip caches are partially associative, the achieved level of performance is quite promising. In particular, two recently p
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Alghamdi, Fatimah, Saoucene Mahfoudh, and Ahmed Barnawi. "A Novel Fog Computing Based Architecture to Improve the Performance in Content Delivery Networks." Wireless Communications and Mobile Computing 2019 (January 23, 2019): 1–13. http://dx.doi.org/10.1155/2019/7864094.

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Along with the continuing evolution of the Internet and its applications, Content Delivery Networks (CDNs) have become a hot topic with both opportunities and challenges. CDNs were mainly proposed to solve content availability and download time issues by delivering content through edge cache servers deployed around the world. In our previous work, we presented a novel CDN architecture based on a Fog computing environment as a promising solution for real-time applications. In such architecture, we proposed to use a name-based routing protocol following the Information Centric Networking (ICN) a
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ALVES, MARCO A. Z., HENRIQUE C. FREITAS, and PHILIPPE O. A. NAVAUX. "HIGH LATENCY AND CONTENTION ON SHARED L2-CACHE FOR MANY-CORE ARCHITECTURES." Parallel Processing Letters 21, no. 01 (2011): 85–106. http://dx.doi.org/10.1142/s0129626411000096.

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Several studies point out the benefits of a shared L2 cache, but some other properties of shared caches must be considered to lead to a thorough understanding of all chip multiprocessor (CMP) bottlenecks. Our paper evaluates and explains shared cache bottlenecks, which are very important considering the rise of many-core processors. The results of our simulations with 32 cores show low performance when L2 cache memory is shared between 2 or 4 cores. In these two cases, the increase of L2 cache latency and contention are the main causes responsible for the increase of execution time.
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Zhu, Dexin, Jun Zheng, Hu Zhou, Jianan Wu, Nianfeng Li, and Lijun Song. "A Hybrid Encryption Scheme for Quantum Secure Video Conferencing Combined with Blockchain." Mathematics 10, no. 17 (2022): 3037. http://dx.doi.org/10.3390/math10173037.

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Traditional video conference systems depend largely on computational complexity to ensure system security, but with the development of high-performance computers, the existing encryption system will be seriously threatened. To solve this problem, a hybrid encryption scheme for quantum secure video conferencing combined with blockchain is proposed in this study. In the system solution architecture, first, the quantum key distribution network is embedded in the classic network; then, the “classical + quantum” hybrid encryption scheme is designed according to the secret level required for the vid
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Zha, Yuli, Pengshuai Cui, Yuxiang Hu, Lei Xue, Julong Lan, and Yu Wang. "An NDN Cache-Optimization Strategy Based on Dynamic Popularity and Replacement Value." Electronics 11, no. 19 (2022): 3014. http://dx.doi.org/10.3390/electronics11193014.

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Aiming at examining the problems of the low cache hit ratio and high-average routing hops in named data networking (NDN), this paper proposes a cache-optimization strategy based on dynamic popularity and replacement value. When the requested content arrives at the routing node, the latest popularity is calculated based on the number of requests in the current cycle and the popularity of the previous cycle. We adjust the node cache threshold according to the occupation of the node cache space and cache the content with a higher popularity than the threshold. When the cache is complete, the cach
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Dissertations / Theses on the topic "Cache (Computers) Architecture"

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Choudhary, Dhruv. "Micro-scheduling and its interaction with cache partitioning." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41167.

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The thesis explores the sources of energy inefficiency in asymmetric multi- core architectures where energy efficiency is measured by the energy-delay squared product. The insights gathered from this study drive the development of optimized thread scheduling and coordinated cache management strategies in an important class of asymmetric shared memory architectures. The proposed techniques are founded on well known mathematical optimization techniques yet are lightweight enough to be implemented in practical systems.
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Nayyar, Raman. "Performance Analysis of a Hierarchical, Cache-Coherent, Shared Memory Based, Multi-processor System." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4695.

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We have conducted a performance analysis of a large scale multiprocessor system based on shared buses organized in a hierarchical fashion and employing an easy to implement snoopy cache protocol. · This arrangement, named TREEBUS [ 5], presents a logical extension path for multiprocessor systems based on a single shared bus whose scalability is limited by the available system bus bandwidth [26]. The multiple, independent, hierarchical buses overcome the bus bandwidth limitation and the architecture can scale to relatively large sizes. We have developed an easy to use, reasonably accurate and c
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Zeng, Hui. "Managing datapath resources in an out-of-order processor for performance and energy efficiency." Diss., Online access via UMI:, 2009.

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Batistella, Rafael Fernandes. "PBIW : um esquema de codificação baseado em padrões de instrução." [s.n.], 2008. http://repositorio.unicamp.br/jspui/handle/REPOSIP/276093.

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Orientador: Rodolfo Jardim de Azevedo<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação<br>Made available in DSpace on 2018-08-11T00:49:37Z (GMT). No. of bitstreams: 1 Batistella_RafaelFernandes_M.pdf: 3411156 bytes, checksum: 7e6b46824189243405a180e949db65c6 (MD5) Previous issue date: 2008<br>Resumo: Trabalhos não muito recentes já mostravam que o aumento de velocidade nas memórias DRAM não acompanha o aumento de velocidade dos processadores. Mesmo assim, pesquisadores na área de arquitetura de computadores continuam buscando novas abordagens para aument
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Wu, Huaping. "An Express Network-on-Chip (ExNoC) Cache Architecture for Large Caches." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1307323725.

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Pattabiraman, Aishwariya. "Heterogeneous Cache Architecture in Network-on-Chips." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1321371508.

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Kong, Jingfei. "ARCHITECTURAL SUPPORT FOR IMPROVING COMPUTER SECURITY." Doctoral diss., University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2610.

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Computer security and privacy are becoming extremely important nowadays. The task of protecting computer systems from malicious attacks and potential subsequent catastrophic losses is, however, challenged by the ever increasing complexity and size of modern hardware and software design. We propose several methods to improve computer security and privacy from architectural point of view. They provide strong protection as well as performance efficiency. In our first approach, we propose a new dynamic information flow method to protect systems from popular software attacks such as buffer overflow
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Ramaswamy, Satish. "Optimizing directory-based cache coherence on the RAW architecture." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/33336.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.<br>Includes bibliographical references (p. 181-182).<br>Caches help reduce the effect of long-latency memory requests, by providing a high speed data-path to local memory. However, in multi-processor systems utilizing shared memory, cache coherence protocols are necessary to ensure sequential consistency. Of the multiple coherence protocols developed, the scalability of directory-based schemes makes them ideal for RAW's architecture [1]. Although one such system has been demonst
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Cashman, Neil. "SMART : an innovative multimedia computer architecture for processing ATM cells in real-time." Thesis, University of Sussex, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313965.

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Musalappa, Saibhushan. "An Energy efficient data cache implementing 2-way LRC architecture." MSSTATE, 2006. http://sun.library.msstate.edu/ETD-db/theses/available/etd-07212006-153949/.

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Conventional level one data caches are widely used in high-performance microprocessors. Shrinking process parameters in chip fabrication technology allow a much larger number of devices on a chip with every new generation. This reduction in device size has led to an increase in the magnitude of a type of energy dissipation hitherto ignored?leakage energy. Transistor level leakage energy research for sub-micron processes has shown that leakage can be as much as or greater than the dynamic energy for advanced circuit designs. Researchers have devised techniques to reduce leakage energy at the fa
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Books on the topic "Cache (Computers) Architecture"

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Analysis of cache performance for operating systems and multiprogramming. Kluwer Academic Publishers, 1989.

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Machinery, Association for Computing, and IEEE Computer Society, eds. ASPLOS-VII proceedings: Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, October 1-5, 1996. Association for Computing Machinery, 1996.

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1953-, Dubois Michel, and Thakkar S. S, eds. Cache and interconnect architectures in multiprocessors. Kluwer Academic Publishers, 1990.

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Balasubramonian, Rajeev. Multi-core cache hierarchies. Morgan & Claypool, 2011.

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A, Patterson David, ed. Computer Organization and Design: The Hardware/Software Interface. 2nd ed. Morgan Kaufmann Publishers, 1998.

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Hennessy, John L. Computer organization and design: The hardware/software interface. Morgan Kaufmann Publishers, 1994.

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Hennessy, John L. Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann, 1994.

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Hennessy, John L. Computer organization and design: The hardware/software interface. Morgan Kaufmann, 1994.

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William, Stallings. Computer organization and architecture: Designing for performance. 7th ed. Pearson Prentice Hall, 2006.

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William, Stallings. Computer organization and architecture: Designing for performance. 4th ed. Prentice-Hall International (UK), 1996.

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Book chapters on the topic "Cache (Computers) Architecture"

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Blanchet, Gérard, and Bertrand Dupouy. "Caches." In Computer Architecture. John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118577431.ch8.

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Blanchet, Gérard, and Bertrand Dupouy. "Caches in a Multiprocessor Environment." In Computer Architecture. John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118577431.ch12.

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Hung, Sheng-Kai, and Yarsun Hsu. "Striping Cache: A Global Cache for Striped Network File System." In Advances in Computer Systems Architecture. Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11859802_34.

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Tian, Xingyan, Kejia Zhao, Huowang Chen, and Hongyan Du. "Cache Behavior Analysis of a Compiler-Assisted Cache Replacement Policy." In Advances in Computer Systems Architecture. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30102-8_4.

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Li, Peng, Dongsheng Wang, Songliu Guo, Tao Tian, and Weimin Zheng. "Live Range Aware Cache Architecture." In Advances in Computer Systems Architecture. Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11859802_37.

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Kabadi, Mohan G., and Ranjani Parthasarathi. "Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem." In Advances in Computer Systems Architecture. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39864-6_27.

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Conte, Thomas M. "Stack-Based Single-Pass Cache Simulation." In Fast Simulation of Computer Architectures. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2361-1_4.

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Menezes, Kishore N. "Sampling for Cache and Processor Simulation." In Fast Simulation of Computer Architectures. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2361-1_7.

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Lai, Chunrong, and Shih-Lien Lu. "Efficient Victim Mechanism on Sector Cache Organization." In Advances in Computer Systems Architecture. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30102-8_3.

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Kim, Cheol Hong, Sung Woo Chung, and Chu Shik Jhon. "An Innovative Instruction Cache for Embedded Processors." In Advances in Computer Systems Architecture. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11572961_5.

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Conference papers on the topic "Cache (Computers) Architecture"

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Cheng, L., and A. A. Sawchuk. "Optical solutions for cache memories in parallel computers." In OSA Annual Meeting. Optica Publishing Group, 1993. http://dx.doi.org/10.1364/oam.1993.mzz.1.

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A cache is a high speed memory located between processors and main memory to fill the speed gap between them. In a loosely coupled parallel computer, each processor has its own cache memory. The processor accesses information from its cache memory, which stores information obtained from the main memory through an interconnection network. A major challenge in this system is to keep the data in all the caches consistent with that in main memory. This is referred to as the cache coherence problem. One solution is to have a bus between the caches, and supply each cache with a controller which list
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Xianfeng Li and Wencong Xie. "CRAFT: A Cache Reduction Architecture for Flow Tables in Software-Defined Networks." In 2017 IEEE Symposium on Computers and Communications (ISCC). IEEE, 2017. http://dx.doi.org/10.1109/iscc.2017.8024651.

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Murta, Cristina Duarte, and Virgílio A. F. Almeida. "Cache na WWW: Limitações e Potencial." In International Symposium on Computer Architecture and High Performance Computing. Sociedade Brasileira de Computação, 1999. http://dx.doi.org/10.5753/sbac-pad.1999.19806.

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WWW caching systems are essential for Web performance and scalability. Web cache workloads and goals show important differences when compared with traditional caching systems, such as memory caches. This article points out and discusses these differences. In order to illustrate our discussion, we present characterization of ten workloads from Web caches. The analysis focuses on the parameters response size and access patterns. We discuss the influence of the characterized parameters in cache performance according to relevant metrics for the WWW and we show directions for the design of Web cach
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Paixão, Goedson Teixeira, Wagner Meira Jr., and Fernando Caixeta Sanches. "Servidores Cache WWW em Arquiteturas Multiprocessadas." In International Symposium on Computer Architecture and High Performance Computing. Sociedade Brasileira de Computação, 1999. http://dx.doi.org/10.5753/sbac-pad.1999.19807.

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O grande crescimento em popularidade da World Wide Web tem motivado várias pesquisas com o objetivo de reduzir a latência observada pelos usuários. Os servidores cache têm se mostrado uma ferramenta muito importante na busca desse objetivo. Embora a utilização de servidores cache tenha contribuído para diminuir o tráfego na Internet, as estratégias de cooperação utilizadas na composição de grupos (clusters) de caches normalmente trazem uma degradação de desempenho aos servidores não sendo, por isso, escaláveis o suficiente para acompanhar o crescimento atual da WWW. Neste trabalho, propomos um
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Hexsel, Roberto A., and Nigel P. Topham. "The Performance of Cache Coherency in SCI-based Multiprocessors." In International Symposium on Computer Architecture and High Performance Computing. Sociedade Brasileira de Computação, 1996. http://dx.doi.org/10.5753/sbac-pad.1996.19813.

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The Scalable Coherent Interface (SCI) is an IEEE/ANSI standard that defines a hardware platform for scalable shared-memory multiprocessors. This paper contains a quantitative performance evaluation of SCI-connected multiprocessors that assesses both the communication and cache coherence subsystems. 1D, 2D and 3D tori with 16 and 64 nodes are investigated. For the architecture (100MHz Sparc, 2 levels of caches) and workload simulated, it was found that raw network bandwidth seen by a processing element is under 100Mbytes/s. The 3-D toros is 10-15% faster than the 2-D toros for programs that gen
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Hytopoulos, Evangelos, Mark D. Kremenetsky, Ramesh Andra, Richard Sun, and Stan Posey. "Scalability Studies on a cc-NUMA Computer Architecture for Large Automotive Simulations." In ASME 1998 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 1998. http://dx.doi.org/10.1115/imece1998-0994.

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Abstract The maturity of the Computational Fluid Dynamics methods and the increasing computational power of today’s computers have allowed the automotive industry to incorporate the CFD technology in several stages of the design process. As the application of the CFD technology is moving from the component level analysis to the system level, the complexity and the size of the models increase continuously. Successful simulation requires synergy between CAD, grid generation, and solvers. The requirement for shorter design cycle has put severe limitations on the turnaround time of the numerical s
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Musoll, Enric, and Mario Nemirovsky. "A study on the performance of two-level exclusive caching." In International Symposium on Computer Architecture and High Performance Computing. Sociedade Brasileira de Computação, 1999. http://dx.doi.org/10.5753/sbac-pad.1999.19771.

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This work presents a study on the performance of a level-two cache configured as a victim storage for the evicted lines of the level-one cache. This two-level cache configuration, known as exclusive caching, is evaluated for a wide range of level-one and level-two sizes and associalivily degrees, and the miss ratios of both levels are compared to those of the two-level inclusive caching. Although the two-level exclusive strategy has lower miss ratios than the inclusive one by increasing the effective associativity and capacity, the replacement policy of the exclusive caching organization force
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Agarwal, Neha, David Nellans, Eiman Ebrahimi, Thomas F. Wenisch, John Danskin, and Stephen W. Keckler. "Selective GPU caches to eliminate CPU-GPU HW cache coherence." In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2016. http://dx.doi.org/10.1109/hpca.2016.7446089.

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Arantes, Luciana, Bertil Folliot, Liria M. Sato, and Pierre Sens. "A Proposal for a Parallel Programming Support for Multi-LAN platforms." In International Symposium on Computer Architecture and High Performance Computing. Sociedade Brasileira de Computação, 1999. http://dx.doi.org/10.5753/sbac-pad.1999.19790.

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In the first part of this article, we present our proposal for a distributed shared memory system (DSM) for an interconnection of local-area networks (LANs). Our multi-LAN DSM will be composed of a set of per LAN lazy release consistency (LRC) memory model DSM systems. For controlling shared-memory updates, the LRC protocol of cach DSM will use the barrier-lock logical clocks, instead of the traditional per processor vector ones. This replacement provides modularity and scalability to some extent. The other enhancements to be added to the protocol aim the reduction of the number of messages an
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Hamkalo, José Luis, and Bruno Cernuschi-Frías. "A Taxonomy for Cache Memory Misses." In International Symposium on Computer Architecture and High Performance Computing. Sociedade Brasileira de Computação, 1999. http://dx.doi.org/10.5753/sbac-pad.1999.19773.

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One way to understand the causes of cache memory misses is to use a classification for them. Usually statistical models such as the 3C model are used to make the classification. In the present work a new definition for the 3C model: compulsory, capacity and conflict misses are given. The corresponding operational definitions are given, which are based on the use of the LRU stack distances. The proposed model is called a deterministic 3C model or D3C. The D3C model classifies the memory references in an individual way, conforming a taxonomy, and then it is possible to analyze when a memory refe
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