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Journal articles on the topic 'Cache (Computers) Architecture'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Yang, Q. "Performance of Cache Memories for Vector Computers." Journal of Parallel and Distributed Computing 19, no. 3 (1993): 163–78. http://dx.doi.org/10.1006/jpdc.1993.1102.

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CHONG, FREDERIC T., and ANANT AGARWAL. "SHARED MEMORY VERSUS MESSAGE PASSING FOR ITERATIVE SOLUTION OF SPARSE, IRREGULAR PROBLEMS." Parallel Processing Letters 09, no. 01 (1999): 159–70. http://dx.doi.org/10.1142/s0129626499000177.

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The benefits of hardware support for shared memory versus those for message passing are difficult to evaluate without an in-depth study of real applications on a common platform. We evaluate the communication mechanisms of the MIT Alewife machine, a multiprocessor which provides integrated cache-coherent shared memory, massage passing, and DMA. We perform this evaluation with "best-effort" implementations which solve several sparse, irregular benchmark problems with a preconditioned conjugate gradient sparse matrix solver (ICCG). We find that machines with fast global memory operations do not

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Wang, Nenzi, Hsin-Yi Chen, and Yu-Wen Chen. "Fluid-film lubrication computing with many-core processors and graphics processing units." Advances in Mechanical Engineering 10, no. 10 (2018): 168781401880471. http://dx.doi.org/10.1177/1687814018804719.

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The advancement of modern processors with many-core and large-cache may have little computational advantages if only serial computing is employed. In this study, several parallel computing approaches, using devices with multiple or many processor cores, and graphics processing units are applied and compared to illustrate the potential applications in fluid-film lubrication study. Two Reynolds equations and an air bearing optimum design are solved using three parallel computing paradigms, OpenMP, Compute Unified Device Architecture, and OpenACC, on standalone shared-memory computers. The newly

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Giraud, L. "Combining Shared and Distributed Memory Programming Models on Clusters of Symmetric Multiprocessors: Some Basic Promising Experiments." International Journal of High Performance Computing Applications 16, no. 4 (2002): 425–30. http://dx.doi.org/10.1177/109434200201600405.

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This note presents some experiments on different clusters of SMPs, where both distributed and shared memory parallel programming paradigms can be naturally combined. Although the platforms exhibit the same macroscopic memory organization, it appears that their individual overall performance is closely dependent on the ability of their hardware to efficiently exploit the local shared memory within the nodes. In that context, cache blocking strategy appears to be very important not only to get good performance out of each individual processor but mainly good performance out of the overall comput

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Huang, Xiaohui, Junqing Fan, Ze Deng, Jining Yan, Jiabao Li, and Lizhe Wang. "Efficient IoT Data Management for Geological Disasters Based on Big Data-Turbocharged Data Lake Architecture." ISPRS International Journal of Geo-Information 10, no. 11 (2021): 743. http://dx.doi.org/10.3390/ijgi10110743.

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Multi-source Internet of Things (IoT) data, archived in institutions’ repositories, are becoming more and more widely open-sourced to make them publicly accessed by scientists, developers, and decision makers via web services to promote researches on geohazards prevention. In this paper, we design and implement a big data-turbocharged system for effective IoT data management following the data lake architecture. We first propose a multi-threading parallel data ingestion method to ingest IoT data from institutions’ data repositories in parallel. Next, we design storage strategies for both inges

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DRACH, N., A. GEFFLAUT, P. JOUBERT, and A. SEZNEC. "ABOUT CACHE ASSOCIATIVITY IN LOW-COST SHARED MEMORY MULTI-MICROPROCESSORS." Parallel Processing Letters 05, no. 03 (1995): 475–87. http://dx.doi.org/10.1142/s0129626495000436.

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Sizes of on-chip caches on current commercial microprocessors range from 16 Kbytes to 36 Kbytes. These microprocessors can be directly used in the design of a low cost single-bus shared memory multiprocessors without using any second-level cache. In this paper, we explore the viability of such a multi-microprocessor. Simulations results clearly establish that performance of such a system will be quite poor if on-chip caches are direct-mapped. On the other hand, when the on-chip caches are partially associative, the achieved level of performance is quite promising. In particular, two recently p

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Alghamdi, Fatimah, Saoucene Mahfoudh, and Ahmed Barnawi. "A Novel Fog Computing Based Architecture to Improve the Performance in Content Delivery Networks." Wireless Communications and Mobile Computing 2019 (January 23, 2019): 1–13. http://dx.doi.org/10.1155/2019/7864094.

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Along with the continuing evolution of the Internet and its applications, Content Delivery Networks (CDNs) have become a hot topic with both opportunities and challenges. CDNs were mainly proposed to solve content availability and download time issues by delivering content through edge cache servers deployed around the world. In our previous work, we presented a novel CDN architecture based on a Fog computing environment as a promising solution for real-time applications. In such architecture, we proposed to use a name-based routing protocol following the Information Centric Networking (ICN) a

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ALVES, MARCO A. Z., HENRIQUE C. FREITAS, and PHILIPPE O. A. NAVAUX. "HIGH LATENCY AND CONTENTION ON SHARED L2-CACHE FOR MANY-CORE ARCHITECTURES." Parallel Processing Letters 21, no. 01 (2011): 85–106. http://dx.doi.org/10.1142/s0129626411000096.

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Several studies point out the benefits of a shared L2 cache, but some other properties of shared caches must be considered to lead to a thorough understanding of all chip multiprocessor (CMP) bottlenecks. Our paper evaluates and explains shared cache bottlenecks, which are very important considering the rise of many-core processors. The results of our simulations with 32 cores show low performance when L2 cache memory is shared between 2 or 4 cores. In these two cases, the increase of L2 cache latency and contention are the main causes responsible for the increase of execution time.

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Zhu, Dexin, Jun Zheng, Hu Zhou, Jianan Wu, Nianfeng Li, and Lijun Song. "A Hybrid Encryption Scheme for Quantum Secure Video Conferencing Combined with Blockchain." Mathematics 10, no. 17 (2022): 3037. http://dx.doi.org/10.3390/math10173037.

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Traditional video conference systems depend largely on computational complexity to ensure system security, but with the development of high-performance computers, the existing encryption system will be seriously threatened. To solve this problem, a hybrid encryption scheme for quantum secure video conferencing combined with blockchain is proposed in this study. In the system solution architecture, first, the quantum key distribution network is embedded in the classic network; then, the “classical + quantum” hybrid encryption scheme is designed according to the secret level required for the vid

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Zha, Yuli, Pengshuai Cui, Yuxiang Hu, Lei Xue, Julong Lan, and Yu Wang. "An NDN Cache-Optimization Strategy Based on Dynamic Popularity and Replacement Value." Electronics 11, no. 19 (2022): 3014. http://dx.doi.org/10.3390/electronics11193014.

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Aiming at examining the problems of the low cache hit ratio and high-average routing hops in named data networking (NDN), this paper proposes a cache-optimization strategy based on dynamic popularity and replacement value. When the requested content arrives at the routing node, the latest popularity is calculated based on the number of requests in the current cycle and the popularity of the previous cycle. We adjust the node cache threshold according to the occupation of the node cache space and cache the content with a higher popularity than the threshold. When the cache is complete, the cach

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Fethellah, Nour El Houda, Hafida Bouziane, and Abdallah Chouarfia. "NECS-based Cache Management in the Information Centric Networking." International Journal of Interactive Mobile Technologies (iJIM) 15, no. 21 (2021): 172. http://dx.doi.org/10.3991/ijim.v15i21.20011.

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The Information Centric Networking ICN architectures are proposed to overcome the problems of the actual internet architecture. One of the main straight points of the ICN architectures is the in-network caching. The ICN performance is influenced by efficiency of the adopted caching strategy which manages the contents in the network and decides where caching them. However, the major issue which faces the caching strategies in the ICN architectures is the strategic election of the cache routers to store the data through its delivery path. This will reduce congestion, optimize the distance betwee

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Fulcher, J. "Experience with Teaching Computer Architecture." International Journal of Electrical Engineering & Education 30, no. 4 (1993): 329–42. http://dx.doi.org/10.1177/002072099303000406.

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Experience with teaching computer architecture A middle-level undergraduate course in computer architecture is described, in terms of both formal coursework and laboratory exercises. These exercises are undertaken using a PDP8 simulator for the Apple Macintosh, an MC68000-based microcomputer, and RISC and Cache simulators for Unix.

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Weinrauch, Alexander, Wolfgang Tatzgern, Pascal Stadlbauer, et al. "Effect-based Multi-viewer Caching for Cloud-native Rendering." ACM Transactions on Graphics 42, no. 4 (2023): 1–16. http://dx.doi.org/10.1145/3592431.

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With cloud computing becoming ubiquitous, it appears as virtually everything can be offered as-a-service. However, real-time rendering in the cloud forms a notable exception, where the cloud adoption stops at running individual game instances in compute centers. In this paper, we explore whether a cloud-native rendering architecture is viable and scales to multi-client rendering scenarios. To this end, we propose world-space and on-surface caches to share rendering computations among viewers placed in the same virtual world. We discuss how caches can be utilized on an effect-basis and demonstr

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Stojcev, Mile, Teufik Tokic, and Ivan Milentijevic. "The limits of semiconductor technology and oncoming challenges in computer micro architectures and architectures." Facta universitatis - series: Electronics and Energetics 17, no. 3 (2004): 285–312. http://dx.doi.org/10.2298/fuee0403285s.

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In the last three decades the world of computers and especially that of microprocessors has been advanced at exponential rates in both productivity and performance. The integrated circuit industry has followed a steady path of constantly shrinking devices geometries and increased functionality that larger chips provide. The technology that enabled this exponential growth is a combination of advancements in process technology, micro architecture architecture and design and development tools. Together, these performances and functionality improvements have resulted in a history of new technology

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Fahringer, T., and A. Požgaj. "P3T+: A Performance Estimator for Distributed and Parallel Programs." Scientific Programming 8, no. 2 (2000): 73–93. http://dx.doi.org/10.1155/2000/217384.

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Developing distributed and parallel programs on today's multiprocessor architectures is still a challenging task. Particular distressing is the lack of effective performance tools that support the programmer in evaluating changes in code, problem and machine sizes, and target architectures. In this paper we introduceP3T+ which is a performance estimator for mostly regular HPF (High Performance Fortran) programs but partially covers also message passing programs (MPI).P3T+ is unique by modeling programs, compiler code transformations, and parallel and distributed architectures. It computes at c

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Gade, Sri Harsha, and Sujay Deb. "A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures." ACM Transactions on Design Automation of Electronic Systems 27, no. 1 (2022): 1–31. http://dx.doi.org/10.1145/3462775.

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Cache coherence ensures correctness of cached data in multi-core processors. Traditional implementations of existing protocols make them unscalable for many core architectures. While snoopy coherence requires unscalable ordered networks, directory coherence is weighed down by high area and energy overheads. In this work, we propose Wireless-enabled Share-aware Hybrid (WiSH) to provide scalable coherence in many core processors. WiSH implements a novel Snoopy over Directory protocol using on-chip wireless links and hierarchical, clustered Network-on-Chip to achieve low-overhead and highly effic

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Li, Yuanhang, Jinlin Wang, and Rui Han. "PB-NCC: A Popularity-Based Caching Strategy with Number-of-Copies Control in Information-Centric Networks." Applied Sciences 12, no. 2 (2022): 653. http://dx.doi.org/10.3390/app12020653.

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The Information-Centric Network (ICN), designed for efficient content acquisition and distribution, is a promising candidate architecture for the future Internet. In-network caching in ICN makes it possible to reuse contents and the Name Resolution System (NRS) makes cached contents better serve users. In this paper, we focused on the ICN caching scenario equipped with an NRS, which records the positions of contents cached in ICN. We propose a Popularity-based caching strategy with Number-of-Copies Control (PB-NCC) in this paper. PB-NCC is proposed to solve the problems of unreasonable content

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Zulfa, Mulki Indana, Rudy Hartanto, Adhistya Erna Permanasari, and Waleed Ali. "LRU-GENACO: A Hybrid Cached Data Optimization Based on the Least Used Method Improved Using Ant Colony and Genetic Algorithms." Electronics 11, no. 19 (2022): 2978. http://dx.doi.org/10.3390/electronics11192978.

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An optimization strategy for cached data offloading plays a crucial role in the edge network environment. This strategy can improve the performance of edge nodes with limited cache memory to serve data service requests from user terminals. The main challenge that must be solved in optimizing cached data offloading is assessing and selecting the cached data with the highest profit to be stored in the cache memory. Selecting the appropriate cached data can improve the utility of memory space to increase HR and reduce LSR. In this paper, we model the cached data offloading optimization strategy a

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Zhou, Tianchi, Peng Sun, and Rui Han. "An Active Path-Associated Cache Scheme for Mobile Scenes." Future Internet 14, no. 2 (2022): 33. http://dx.doi.org/10.3390/fi14020033.

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With the widespread growth of mass content, information-centric networks (ICN) have become one of the research hotspots of future network architecture. One of the important features of ICN is ubiquitous in-network caching. In recent years, the explosive growth of mobile devices has brought content dynamics, which poses a new challenge to the original ICN caching mechanism. This paper focuses on the WiFi mobile scenario of ICN. We design a new path-associated active caching scheme to shorten the time delay of users obtaining content to enhance the user experience. In this article, based on the

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Al-Ahmadi, Saad. "A New Efficient Cache Replacement Strategy for Named Data Networking." International journal of Computer Networks & Communications 13, no. 5 (2021): 19–35. http://dx.doi.org/10.5121/ijcnc.2021.13502.

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The Information-Centric Network (ICN) is a future internet architecture with efficient content retrieval and distribution. Named Data Networking (NDN) is one of the proposed architectures for ICN. NDN’s innetwork caching improves data availability, reduce retrieval delays, network load, alleviate producer load, and limit data traffic. Despite the existence of several caching decision algorithms, the fetching and distribution of contents with minimum resource utilization remains a great challenge. In this paper, we introduce a new cache replacement strategy called Enhanced Time and Frequency Ca

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Dalui, Mamata, and Biplab K. Sikdar. "A Cache System Design for CMPs with Built-In Coherence Verification." VLSI Design 2016 (October 30, 2016): 1–16. http://dx.doi.org/10.1155/2016/8093614.

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This work reports an effective design of cache system for Chip Multiprocessors (CMPs). It introduces built-in logic for verification of cache coherence in CMPs realizing directory based protocol. It is developed around the cellular automata (CA) machine, invented by John von Neumann in the 1950s. A special class of CA referred to as single length cycle 2-attractor cellular automata (TACA) has been planted to detect the inconsistencies in cache line states of processors’ private caches. The TACA module captures coherence status of the CMPs’ cache system and memorizes any inconsistent recording

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Chen, Yingwen, Hujie Yu, Bowen Hu, Zhimin Duan, and Guangtao Xue. "An Edge Caching Strategy Based on User Speed and Content Popularity for Mobile Video Streaming." Electronics 10, no. 18 (2021): 2217. http://dx.doi.org/10.3390/electronics10182217.

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Mobile users’ demands to delay-sensitive video streaming media put forward new requirements for mobile networks, such as architecture optimization. Edge caching as a new paradigm is proposed to enhance the quality of service (QoS) for mobile users at the network edge. Due to the limited coverage of edge cache nodes, the frequent handoffs between base stations would aggravate network traffic overhead, resulting in a bad experience of high latency and service interruption when mobile users browse videos. This paper first proposes a three-layer mobile edge network architecture and applied edge ca

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Kim, Beomjun, Yongtae Kim, Prashant Nair, and Seokin Hong. "Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches." Electronics 11, no. 2 (2022): 240. http://dx.doi.org/10.3390/electronics11020240.

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STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper pro

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Wang, Yao, Lijun Sun, Haibo Wang, Lavanya Gopalakrishnan, and Ronald Eaton. "Novel prioritized LRU circuits for shared cache in computer systems." Modern Physics Letters B 34, no. 23 (2020): 2050242. http://dx.doi.org/10.1142/s0217984920502425.

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Cache sharing technique is critical in multi-core and multi-threading systems. It potentially delays the execution of real-time applications and makes the prediction of the worst-case execution time (WCET) of real-time applications more challenging. Prioritized cache has been demonstrated as a promising approach to address this challenge. Instead of the conventional prioritized cache schemes realized at the architecture level by using cache controllers, this work presents two prioritized least recently used (LRU) cache replacement circuits that directly accomplish the prioritization inside the

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Gozlan, Itamar, Chen Avin, Gil Einziger, and Gabriel Scalosub. "Go-to-Controller is Better: Efficient and Optimal LPM Caching with Splicing." ACM SIGMETRICS Performance Evaluation Review 51, no. 1 (2023): 15–16. http://dx.doi.org/10.1145/3606376.3593546.

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Data center networks must support huge forwarding policies as they handle the traffic of the various tenants. Since such policies cannot be stored within the limited memory available at commodity switches, SDN controllers can manage the memory available at the switch as a cache, updating and changing the forwarding rules in the cache according to the policy and workloads dynamics. Most policies, such as Longest-prefix-match (LPM) policies, include dependencies between the forwarding rules, which introduce consistency constraints on the structure of the cached content, affecting the performance

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Quan, Guocong, Atilla Eryilmaz, Jian Tan, and Ness Shroff. "Prefetching and Caching for Minimizing Service Costs." ACM SIGMETRICS Performance Evaluation Review 48, no. 3 (2021): 77–78. http://dx.doi.org/10.1145/3453953.3453970.

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In practice, prefetching data strategically has been used to improve caching performance. The idea is that data items can either be cached upon request (traditional approach) or prefetched into the cache before the requests actually occur. The caching and prefetching operations compete for the limited cache space, whose size is typically much smaller than the number of data items. A key challenge is to design an optimal prefetching and caching policy, assuming that the future requests can be predicted to a certain extent. This is a non-trivial challenge even under the idealized assumption that

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Luo, Ya Li. "Research of Adaptive Control Algorithm Based on the Cached Playing of Streaming Media." Applied Mechanics and Materials 539 (July 2014): 502–6. http://dx.doi.org/10.4028/www.scientific.net/amm.539.502.

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Aimed at the quality issues of current network streaming media playing, it manages by introducing a streaming media caching mechanism to help improve the playing effect. But the cached playing also has its own deficiencies, so here combines the adaptive control algorithm with the caching mechanism to solve this problem. It firstly introduces the streaming media service, and analyzes the transmission process of streaming media and adaptive media playing in detail; secondly analyzes the adaptive control algorithm of streaming media caching from the principle and design of reserving cache algorit

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Kadayif, I., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and J. Ramanujam. "Morphable Cache Architectures." ACM SIGPLAN Notices 36, no. 8 (2001): 128–37. http://dx.doi.org/10.1145/384196.384215.

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Charrier, Dominic E., Benjamin Hazelwood, Ekaterina Tutlyaeva, et al. "Studies on the energy and deep memory behaviour of a cache-oblivious, task-based hyperbolic PDE solver." International Journal of High Performance Computing Applications 33, no. 5 (2019): 973–86. http://dx.doi.org/10.1177/1094342019842645.

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We study the performance behaviour of a seismic simulation using the ExaHyPE engine with a specific focus on memory characteristics and energy needs. ExaHyPE combines dynamically adaptive mesh refinement (AMR) with ADER-DG. It is parallelized using tasks, and it is cache efficient. AMR plus ADER-DG yields a task graph which is highly dynamic in nature and comprises both arithmetically expensive tasks and tasks which challenge the memory’s latency. The expensive tasks and thus the whole code benefit from AVX vectorization, although we suffer from memory access bursts. A frequency reduction of t

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Qazi, Faiza, Osman Khalid, Rao Naveed Bin Rais, Imran Ali Khan, and Atta ur Rehman Khan. "Optimal Content Caching in Content-Centric Networks." Wireless Communications and Mobile Computing 2019 (January 23, 2019): 1–15. http://dx.doi.org/10.1155/2019/6373960.

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Content-Centric Networking (CCN) is a novel architecture that is shifting host-centric communication to a content-centric infrastructure. In recent years, in-network caching in CCNs has received significant attention from research community. To improve the cache hit ratio, most of the existing schemes store the content at maximum number of routers along the downloading path of content from source. While this helps in increased cache hits and reduction in delay and server load, the unnecessary caching significantly increases the network cost, bandwidth utilization, and storage consumption. To a

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Osei-Mensah, Emmanuel, Saqr Khalil Saeed Thabet, Chunbo Luo, et al. "A Novel Distributed Media Caching Technique for Seamless Video Streaming in Multi-Access Edge Computing Networks." Applied Sciences 12, no. 9 (2022): 4205. http://dx.doi.org/10.3390/app12094205.

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Online video is anticipated to be the largest fraction of all mobile network traffic aside from the huge processing tasks imposed on networks by the billions of IoT devices, causing unprecedented challenges to the current network architecture. Edge caching has been proposed as a highly promising technology to overcome this challenge by placing computational and data storage resources at the network edge to reduce latency and backhaul traffic. However, the edge resources are heavily constrained in their storage and computational capacities as large-scale deployments mean fairly distributing res

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Qin, Tiancheng, and S. Rasoul Etesami. "Optimal Online Algorithms for File-Bundle Caching and Generalization to Distributed Caching." ACM Transactions on Modeling and Performance Evaluation of Computing Systems 6, no. 1 (2021): 1–23. http://dx.doi.org/10.1145/3445028.

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We consider a generalization of the standard cache problem called file-bundle caching, where different queries (tasks), each containing l ≥ 1 files, sequentially arrive. An online algorithm that does not know the sequence of queries ahead of time must adaptively decide on what files to keep in the cache to incur the minimum number of cache misses. Here a cache miss refers to the case where at least one file in a query is missing among the cache files. In the special case where l = 1, this problem reduces to the standard cache problem. We first analyze the performance of the classic least recen

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Fung, Larry S. K., Mohammad O. Sindi, and Ali H. Dogru. "Multiparadigm Parallel Acceleration for Reservoir Simulation." SPE Journal 19, no. 04 (2014): 716–25. http://dx.doi.org/10.2118/163591-pa.

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Summary With the advent of the multicore central-processing unit (CPU), today's commodity PC clusters are effectively a collection of interconnected parallel computers, each with multiple multicore CPUs and large shared random access memory (RAM), connected together by means of high-speed networks. Each computer, referred to as a compute node, is a powerful parallel computer on its own. Each compute node can be equipped further with acceleration devices such as the general-purpose graphical processing unit (GPGPU) to further speed up computational-intensive portions of the simulator. Reservoir

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PADMANABHAN, SANDEEP, and YANN-HANG LEE. "EFFICIENT STATE-SAVING ARCHITECTURES FOR POWER-MODE SWITCHING." International Journal of Software Engineering and Knowledge Engineering 15, no. 02 (2005): 379–88. http://dx.doi.org/10.1142/s0218194005001914.

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Time and energy is expended in switching between power modes (e.g., active, hibernate, sleep, etc.). Powering off cache is one major reason for this. When there is a switch in the power-mode involving cache power-off, the system spends time and energy in filling the cache with new data (inherent cache misses). In our technique, before powering off the cache, we save its state in Embedded DRAM and bring it back when the previous power mode is restored. Our experiments have showed that in a majority of cases the cache contents are too valuable to be erased. By saving the contents we can reduce s

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Qureshi, Adnan Mahmood, Nadeem Anjum, Rao Naveed Bin Rais, Masood Ur-Rehman, and Amir Qayyum. "Detection of malicious consumer interest packet with dynamic threshold values." PeerJ Computer Science 7 (March 17, 2021): e435. http://dx.doi.org/10.7717/peerj-cs.435.

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As a promising next-generation network architecture, named data networking (NDN) supports name-based routing and in-network caching to retrieve content in an efficient, fast, and reliable manner. Most of the studies on NDN have proposed innovative and efficient caching mechanisms and retrieval of content via efficient routing. However, very few studies have targeted addressing the vulnerabilities in NDN architecture, which a malicious node can exploit to perform a content poisoning attack (CPA). This potentially results in polluting the in-network caches, the routing of content, and consequent

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Su, Chao, and Qingkai Zeng. "Survey of CPU Cache-Based Side-Channel Attacks: Systematic Analysis, Security Models, and Countermeasures." Security and Communication Networks 2021 (June 10, 2021): 1–15. http://dx.doi.org/10.1155/2021/5559552.

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Privacy protection is an essential part of information security. The use of shared resources demands more privacy and security protection, especially in cloud computing environments. Side-channel attacks based on CPU cache utilize shared CPU caches within the same physical device to compromise the system’s privacy (encryption keys, program status, etc.). Information is leaked through channels that are not intended to transmit information, jeopardizing system security. These attacks have the characteristics of both high concealment and high risk. Despite the improvement in architecture, which m

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Chang, Yaxin, Jiafei Guo, Hanbo Wang, Dapeng Man, and Jiguang Lv. "An Information-Centric Network Caching Method Based on Popularity Rating and Topology Weighting." Wireless Communications and Mobile Computing 2022 (August 11, 2022): 1–12. http://dx.doi.org/10.1155/2022/4979057.

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Ubiquitous caching is a feature shared by all proposed information-centric network (ICN) architectures. Prioritising storage resources to popular content in the network is a proven way to guarantee hit rates, reduce the number of hops forwarded, and reduce user request latency. An ideal ICN caching mechanism should make the best use of relevant information such as content information, network state, and user requirements to achieve optimal selection and have the ability to adaptively adjust the decision cache content for dynamic scenarios. Since router nodes have limited cache space, it is the

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Qiu, Changpei, Xin’an Wang, Tianxia Zhao, Qiuping Li, Bo Wang, and Hu Wang. "An FPGA-Based Convolutional Neural Network Coprocessor." Wireless Communications and Mobile Computing 2021 (June 12, 2021): 1–12. http://dx.doi.org/10.1155/2021/3768724.

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In this paper, an FPGA-based convolutional neural network coprocessor is proposed. The coprocessor has a 1D convolutional computation unit PE in row stationary (RS) streaming mode and a 3D convolutional computation unit PE chain in pulsating array structure. The coprocessor can flexibly control the number of PE array openings according to the number of output channels of the convolutional layer. In this paper, we design a storage system with multilevel cache, and the global cache uses multiple broadcasts to distribute data to local caches and propose an image segmentation method that is compat

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Huh, Joonmoo, and Deokwoo Lee. "Effective On-Chip Communication for Message Passing Programs on Multi-Core Processors." Electronics 10, no. 21 (2021): 2681. http://dx.doi.org/10.3390/electronics10212681.

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Shared memory is the most popular parallel programming model for multi-core processors, while message passing is generally used for large distributed machines. However, as the number of cores on a chip increases, the relative merits of shared memory versus message passing change, and we argue that message passing becomes a viable, high performing, and parallel programming model. To demonstrate this hypothesis, we compare a shared memory architecture with a new message passing architecture on a suite of applications tuned for each system independently. Perhaps surprisingly, the fundamental beha

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Dogruluk, Ertugrul, Joaquim Macedo, and Antonio Costa. "A Countermeasure Approach for Brute-Force Timing Attacks on Cache Privacy in Named Data Networking Architectures." Electronics 11, no. 8 (2022): 1265. http://dx.doi.org/10.3390/electronics11081265.

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One key feature of named data networks (NDN) is supporting in-network caching to increase the content distribution for today’s Internet needs. However, previously cached contents may be threatened by side-channel timing measurements/attacks. For example, one adversary can identify previously cached contents by distinguishing between uncached and cached contents from the in-network caching node, namely the edge NDN router. The attacks can be mitigated by the previously proposed methods effectively. However, these countermeasures may be against the NDN paradigm, affecting the content distributio

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Cao, Wei, Jinyuan Gu, Xiaohui Gu, and Guoan Zhang. "Beamsteering-Aware Power Allocation for Cache-Assisted NOMA mmWave Vehicular Networks." Electronics 12, no. 12 (2023): 2653. http://dx.doi.org/10.3390/electronics12122653.

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Cache-enabled networks with multiple access (NOMA) integration have been shown to decrease wireless network traffic congestion and content delivery latency. This work investigates optimal power control in cache-assisted NOMA millimeter-wave (mmWave) vehicular networks, where mmWave channels experience double-Nakagami fading and the mmWave beamforming is subjected to beamsteering errors. We aim to optimize vehicular quality of service while maintaining fairness among vehicles, through the maximization of successful signal decoding probability for paired vehicles. A comprehensive analysis is car

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Struharik, Rastislav, and Vuk Vranjković. "Striping input feature map cache for reducing off-chip memory traffic in CNN accelerators." Telfor Journal 12, no. 2 (2020): 116–21. http://dx.doi.org/10.5937/telfor2002116s.

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Data movement between the Convolutional Neural Network (CNN) accelerators and off-chip memory is critical concerning the overall power consumption. Minimizing power consumption is particularly important for low power embedded applications. Specific CNN computes patterns offer a possibility of significant data reuse, leading to the idea of using specialized on-chip cache memories which enable a significant improvement in power consumption. However, due to the unique caching pattern present within CNNs, standard cache memories would not be efficient. In this paper, a novel on-chip cache memory a

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Giannoula, Christina, Kailong Huang, Jonathan Tang, et al. "Architectural Support for Efficient Data Movement in Fully Disaggregated Systems." ACM SIGMETRICS Performance Evaluation Review 51, no. 1 (2023): 5–6. http://dx.doi.org/10.1145/3606376.3593533.

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Traditional data centers include monolithic servers that tightly integrate CPU, memory and disk (Figure 1a). Instead, Disaggregated Systems (DSs) [8, 13, 18, 27] organize multiple compute (CC), memory (MC) and storage devices as independent, failure-isolated components interconnected over a high-bandwidth network (Figure 1b). DSs can greatly reduce data center costs by providing improved resource utilization, resource scaling, failure-handling and elasticity in modern data centers [5, 8-10, 10, 11, 13, 18, 27] The MCs provide large pools of main memory (remote memory), while the CCs include th

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Hu, Liang, Jiejun Hu, Tao Fu, Jiyang Bao, and Feng Wang. "Asymmetric network information cache based on mobile traffic in software-defined network." Advances in Mechanical Engineering 11, no. 1 (2019): 168781401881989. http://dx.doi.org/10.1177/1687814018819894.

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Software-defined network is an encouraging research area that realizes updates throughout an entire network, and a wireless network is ubiquitous in an up-to-date world. The combination of these techniques, which is referred to as a wireless software-defined network, has been a significant development in numerous testbeds. The extensive use of distributed controllers that achieved elastic extension and are fault tolerant in large-scale wireless networks is hopeful. Despite their profits, they generate significant overhead in synchronizing network information. Thus, power-hungry wireless softwa

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Park, Jungwoo, Soontae Kim, and Jong-Uk Hou. "An L2 Cache Architecture Supporting Bypassing for Low Energy and High Performance." Electronics 10, no. 11 (2021): 1328. http://dx.doi.org/10.3390/electronics10111328.

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Conventional 2-level cache architecture is not efficient in mobile systems when small programs that do not require the large L2 cache run. Bypassing the L2 cache for those small programs has two benefits. When only a single program runs, bypassing the L2 cache allows to power it down removing its leakage energy consumption. When multiple programs run simultaneously on multiple cores, small programs bypass the L2 cache while large programs use it. This decreases conflicts in the L2 cache among those programs increasing overall performance. From our experiments using cycle-accurate performance a

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Keyes, D. E., H. Ltaief, and G. Turkiyyah. "Hierarchical algorithms on hierarchical architectures." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 378, no. 2166 (2020): 20190055. http://dx.doi.org/10.1098/rsta.2019.0055.

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A traditional goal of algorithmic optimality, squeezing out flops, has been superseded by evolution in architecture. Flops no longer serve as a reasonable proxy for all aspects of complexity. Instead, algorithms must now squeeze memory, data transfers, and synchronizations, while extra flops on locally cached data represent only small costs in time and energy. Hierarchically low-rank matrices realize a rarely achieved combination of optimal storage complexity and high-computational intensity for a wide class of formally dense linear operators that arise in applications for which exascale compu

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Aggarwal, Amit, and Sanket Kansal. "The Architecture of Memory for Core Processors." Journal of Futuristic Sciences and Applications 4, no. 2 (2021): 31–38. http://dx.doi.org/10.51976/jfsa.422105.

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The effectiveness and storage capacity of single-bit cache memory have been investigated. Write driver circuit, random access memory cell, and current mode detector make up the single-bit cache. Using various strategies, such as power-saving components like current mode sensing amplifiers and static random access memory cells, memory systems with just one bit of cache can use less power. To save power, substitute a forced stack and a current mode detecting amplifier for a single-bit cache.

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Kim, Cheol Hong, Sung Woo Chung, and Chu Shik Jhon. "PP-cache: A partitioned power-aware instruction cache architecture." Microprocessors and Microsystems 30, no. 5 (2006): 268–79. http://dx.doi.org/10.1016/j.micpro.2005.12.004.

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Eckardt, H. "Disk cache architectures for transaction-like applications in parallel computers." Computing 53, no. 1 (1994): 13–31. http://dx.doi.org/10.1007/bf02262106.

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Kumar, Anurag, and Sheo Kumar. "Memory Architecture: Low-Power Single-Bit Cache." Journal of Futuristic Sciences and Applications 3, no. 2 (2020): 64–72. http://dx.doi.org/10.51976/jfsa.322007.

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Researchers investigated the functionality and efficiency of the single-bit cache memory architecture in terms of numbers. There are three different memory locations in a single-bit cache. A write driver, an SRAM cell, and a sensing amplifier are a few of these parts. SRAM blocks and sensing amplifiers are extensively used in constructing single-bit cache memory to reduce power usage. Both process corner simulation and circuit Monte Carlo simulation have researched their potential applications. It was subsequently determined that a forced stack design was more energy-efficient than a single-bi

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