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Relevant bibliographies by topics / Cache ; DRAM ; memory hierarchy

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Academic literature on the topic 'Cache ; DRAM ; memory hierarchy'

Author: Grafiati

Published: 4 June 2021

Last updated: 2 February 2022

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Journal articles on the topic "Cache ; DRAM ; memory hierarchy"

1

Li, Xiaochang, and Zhengjun Zhai. "UHNVM: A Universal Heterogeneous Cache Design with Non-Volatile Memory." Electronics 10, no. 15 (2021): 1760. http://dx.doi.org/10.3390/electronics10151760.

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During the recent decades, non-volatile memory (NVM) has been anticipated to scale up the main memory size, improve the performance of applications, and reduce the speed gap between main memory and storage devices, while supporting persistent storage to cope with power outages. However, to fit NVM, all existing DRAM-based applications have to be rewritten by developers. Therefore, the developer must have a good understanding of targeted application codes, so as to manually distinguish and store data fit for NVM. In order to intelligently facilitate NVM deployment for existing legacy applicatio

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Hidaka, H., Y. Matsuda, M. Asakura, and K. Fujishima. "The cache DRAM architecture: a DRAM with an on-chip cache memory." IEEE Micro 10, no. 2 (1990): 14–25. http://dx.doi.org/10.1109/40.52944.

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Xu, Thomas Can Hao, Pasi Liljeberg, and Hannu Tenhunen. "Exploring DRAM Last Level Cache for 3D Network-on-Chip Architecture." Advanced Materials Research 403-408 (November 2011): 4009–18. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.4009.

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In this paper, we implement and analyze different Network-on-Chip (NoC) designs with Static Random Access Memory (SRAM) Last Level Cache (LLC) and Dynamic Random Access Memory (DRAM) LLC. Different 2D/3D NoCs with SRAM/DRAM are modeled based on state-of-the-art chips. The impact of integrating DRAM cache into a NoC platform is discussed. We explore the advantages and disadvantages of DRAM cache for NoC in terms of access latency, cache size, area and power consumption. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that

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Shin, Ho, and Eui-Young Chung. "In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs." Micromachines 10, no. 2 (2019): 124. http://dx.doi.org/10.3390/mi10020124.

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Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed,

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Tabak, Daniel. "Cache and Memory Hierarchy Design." ACM SIGARCH Computer Architecture News 23, no. 3 (1995): 28. http://dx.doi.org/10.1145/203618.564957.

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Cha, Sanghoon, Bokyeong Kim, Chang Hyun Park, and Jaehyuk Huh. "Morphable DRAM Cache Design for Hybrid Memory Systems." ACM Transactions on Architecture and Code Optimization 16, no. 3 (2019): 1–24. http://dx.doi.org/10.1145/3338505.

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Kawata, Hirotaka, Gaku Nakagawa, and Shuichi Oikawa. "Using DRAM as Cache for Non-Volatile Main Memory Swapping." International Journal of Software Innovation 4, no. 1 (2016): 61–71. http://dx.doi.org/10.4018/ijsi.2016010105.

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The performance of mobile devices such as smartphones and tablets has been rapidly improving in recent years. However, these improvements have been seriously affecting power consumption. One of the greatest challenges is to achieve efficient power management for battery-equipped mobile devices. To solve this problem, the authors focus on the emerging non-volatile memory (NVM), which has been receiving increasing attention in recent years. Since its performance is comparable with that of DRAM, it is possible to replace the main memory with NVM, thereby reducing power consumption. However, the p

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Moon, Yaebin, Deok-Jae Oh, and Jung Ho Ahn. "Performance Analysis of DRAM Cache by Comparing Performance Analysis of DRAM Cache by Comparing." Journal of KIISE 47, no. 10 (2020): 893–99. http://dx.doi.org/10.5626/jok.2020.47.10.893.

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Lim, Seung-Ho, Hyunchul Seok, and Ki-Woong Park. "Polymorphic Memory: A Hybrid Approach for Utilizing On-Chip Memory in Manycore Systems." Electronics 9, no. 12 (2020): 2061. http://dx.doi.org/10.3390/electronics9122061.

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The key challenges of manycore systems are the large amount of memory and high bandwidth required to run many applications. Three-dimesnional integrated on-chip memory is a promising candidate for addressing these challenges. The advent of on-chip memory has provided new opportunities to rethink traditional memory hierarchies and their management. In this study, we propose a polymorphic memory as a hybrid approach when using on-chip memory. In contrast to previous studies, we use the on-chip memory as both a main memory (called M1 memory) and a Dynamic Random Access Memory (DRAM) cache (called

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Ro, Yuhwan, Minchul Sung, Yongjun Park, and Jung Ho Ahn. "Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems." IEICE Electronics Express 14, no. 11 (2017): 20170437. http://dx.doi.org/10.1587/elex.14.20170437.

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Dissertations / Theses on the topic "Cache ; DRAM ; memory hierarchy"

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Huang, Cheng-Chieh. "Optimizing cache utilization in modern cache hierarchies." Thesis, University of Edinburgh, 2016. http://hdl.handle.net/1842/19571.

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Memory wall is one of the major performance bottlenecks in modern computer systems. SRAM caches have been used to successfully bridge the performance gap between the processor and the memory. However, SRAM cache’s latency is inversely proportional to its size. Therefore, simply increasing the size of caches could result in negative impact on performance. To solve this problem, modern processors employ multiple levels of caches, each of a different size, forming the so called memory hierarchy. Upon a miss, the processor will start to lookup the data from the highest level (L1 cache) to the lowe

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Ghosh, Mrinmoy. "Microarchitectural techniques to reduce energy consumption in the memory hierarchy." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28265.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Lee, Hsien-Hsin S.; Committee Member: Cahtterjee,Abhijit; Committee Member: Mukhopadhyay, Saibal; Committee Member: Pande, Santosh; Committee Member: Yalamanchili, Sudhakar.

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Dublish, Saumay Kumar. "Managing the memory hierarchy in GPUs." Thesis, University of Edinburgh, 2018. http://hdl.handle.net/1842/31205.

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Pervasive use of GPUs across multiple disciplines is a result of continuous adaptation of the GPU architectures to address the needs of upcoming application domains. One such vital improvement is the introduction of the on-chip cache hierarchy, used primarily to filter the high bandwidth demand to the off-chip memory. However, in contrast to traditional CPUs, the cache hierarchy in GPUs is presented with significantly different challenges such as cache thrashing and bandwidth bottlenecks, arising due to small caches and high levels of memory traffic. These challenges lead to severe congestion

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Xiang, Ping. "ANALYZING INSTRUCTTION BASED CACHE REPLACEMENT POLICIES." Master's thesis, University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2589.

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The increasing speed gap between microprocessors and off-chip DRAM makes last-level caches (LLCs) a critical component for computer performance. Multi core processors aggravate the problem since multiple processor cores compete for the LLC. As a result, LLCs typically consume a significant amount of the die area and effective utilization of LLCs is mandatory for both performance and power efficiency. We present a novel replacement policy for last-level caches (LLCs). The fundamental observation is to view LLCs as a shared resource among multiple address streams with each stream being generated

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SOHONI, SOHUM. "IMPROVING L2 CACHE PERFORMANCE THROUGH STREAM-DIRECTED OPTIMIZATIONS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1092932892.

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Baek, Seungcheol. "High-performance memory system architectures using data compression." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51863.

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The Chip Multi-Processor (CMP) paradigm has cemented itself as the archetypal philosophy of future microprocessor design. Rapidly diminishing technology feature sizes have enabled the integration of ever-increasing numbers of processing cores on a single chip die. This abundance of processing power has magnified the venerable processor-memory performance gap, which is known as the ”memory wall”. To bridge this performance gap, a high-performing memory structure is needed. An attractive solution to overcoming this processor-memory performance gap is using compression in the memory hierarchy. In

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Davari, Mahdad. "Advances Towards Data-Race-Free Cache Coherence Through Data Classification." Doctoral thesis, Uppsala universitet, Avdelningen för datorteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-320595.

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Providing a consistent view of the shared memory based on precise and well-defined semantics—memory consistency model—has been an enabling factor in the widespread acceptance and commercial success of shared-memory architectures. Moreover, cache coherence protocols have been employed by the hardware to remove from the programmers the burden of dealing with the memory inconsistency that emerges in the presence of the private caches. The principle behind all such cache coherence protocols is to guarantee that consistent values are read from the private caches at all times. In its most stringent

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Lodde, Mario. "Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors." Doctoral thesis, Universitat Politècnica de València, 2014. http://hdl.handle.net/10251/35325.

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La jerarquía de caches y la red en el chip (NoC) son dos componentes clave de los chip multiprocesadores (CMPs). La mayoría del trafico en la NoC se debe a mensajes que las caches envían según lo que establece el protocolo de coherencia. La cantidad de trafico, el porcentaje de mensajes cortos y largos y el patrón de trafico en general varían dependiendo de la geometría de las caches y del protocolo de coherencia. La arquitectura de la NoC y la jerarquía de caches están de hecho firmemente acopladas, y estos dos componentes deben ser diseñados y evaluados conjuntamente para estudiar como el va

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Candel, Margaix Francisco. "Efficient L2 Cache Management to Boost GPGPU Performance." Doctoral thesis, Universitat Politècnica de València, 2019. http://hdl.handle.net/10251/125477.

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[ES] En los últimos años, la creciente necesidad de la capacidad de cómputo ha supuesto un reto que ha llevado a la industria a buscar arquitecturas alternativas a los procesadores superescalares con ejecución fuera de orden convencionales, con el objetivo de incrementar la potencia de cómputo con una mayor eficiencia energética. Las GPU, que hasta hace apenas una década se dedicaban exclusivamente a la aceleración de los gráficos en los computadores, han sido una de las arquitecturas alternativas más utilizadas durante varios años para alcanzar el mencionado objetivo. Una de las característi

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Molka, Daniel. "Performance Analysis of Complex Shared Memory Systems." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-221729.

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Systems for high performance computing are getting increasingly complex. On the one hand, the number of processors is increasing. On the other hand, the individual processors are getting more and more powerful. In recent years, the latter is to a large extent achieved by increasing the number of cores per processor. Unfortunately, scientific applications often fail to fully utilize the available computational performance. Therefore, performance analysis tools that help to localize and fix performance problems are indispensable. Large scale systems for high performance computing typically consi

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Books on the topic "Cache ; DRAM ; memory hierarchy"

1

Jacob, Bruce. Memory systems: Cache, DRAM, disk. Morgan Kaufmann Publishers, 2008.

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Przybylski, Steven A. Cache and memory hierarchy design: A performance-directed approach. Morgan Kaufmann Publishers, 1990.

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Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann, 2007.

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Cache and Memory Hierarchy Design. Elsevier, 1990. http://dx.doi.org/10.1016/c2009-0-27582-9.

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Book chapters on the topic "Cache ; DRAM ; memory hierarchy"

1

Kavi, Krishna, Stefano Pianelli, Giandomenico Pisano, Giuseppe Regina, and Mike Ignatowski. "3D DRAM and PCMs in Processor Memory Hierarchy." In Architecture of Computing Systems – ARCS 2014. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-04891-8_16.

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Li, Hai, Zhenyu Sun, Xiuyuan Bi, Weng-Fai Wong, Xiaochun Zhu, and Wenqing Wu. "STT-RAM Cache Hierarchy Design and Exploration with Emerging Magnetic Devices." In Emerging Memory Technologies. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4419-9551-3_7.

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Machanick, Philip, and Zunaid Patel. "L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy." In Advances in Computer Systems Architecture. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39864-6_25.

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Chen, Naikuo, Zhilou Yu, and Ruidong Zhao. "A Hybrid Memory Hierarchy to Improve Cache Reliability with Non-volatile STT-RAM." In Lecture Notes in Computer Science. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-52015-5_47.

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Novac, O., St Vari-Kakas, Mihaela Novac, Ecaterina Vladu, and Liliana Indrie. "Dependability Aspects Regarding the Cache Level of a Memory Hierarchy using Hamming Codes." In Innovations in Computing Sciences and Software Engineering. Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9112-3_98.

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Novac, O., St Vari-Kakas, F. I. Hathazi, M. Curila, and S. Curila. "Aspects Regarding the Implementation of Hsiao Code to the Cache Level of a Memory Hierarchy with Fpga Xilinx Circuits." In Advanced Techniques in Computing Sciences and Software Engineering. Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3660-5_92.

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Davis, Al, Michael Schuette, Diana Franklin, et al. "In Praise of Memory Systems: Cache, DRAM, Disk." In Memory Systems. Elsevier, 2008. http://dx.doi.org/10.1016/b978-0-12-379751-3.50036-9.

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Przybylski, Steven A. "Performance-Directed Cache Design." In Cache and Memory Hierarchy Design. Elsevier, 1990. http://dx.doi.org/10.1016/b978-0-08-050059-1.50009-8.

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Przybylski, Steven A. "Multi-Level Cache Hierarchies." In Cache and Memory Hierarchy Design. Elsevier, 1990. http://dx.doi.org/10.1016/b978-0-08-050059-1.50010-4.

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"Front Matter." In Cache and Memory Hierarchy Design. Elsevier, 1990. http://dx.doi.org/10.1016/b978-0-08-050059-1.50001-3.

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Conference papers on the topic "Cache ; DRAM ; memory hierarchy"

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Van Laer, Anouk, William Wang, and Chris Emmons. "Inefficiencies in the Cache Hierarchy." In MEMSYS '15: International Symposium on Memory Systems. ACM, 2015. http://dx.doi.org/10.1145/2818950.2818980.

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Hameed, Fazal, Christian Menard, and Jeronimo Castrillon. "Efficient STT-RAM last-level-cache architecture to replace DRAM cache." In MEMSYS 2017: The International Symposium on Memory Systems, 2017. ACM, 2017. http://dx.doi.org/10.1145/3132402.3132414.

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Hameed, Fazal, Lars Bauer, and Jörg Henkel. "Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture." In the The 51st Annual Design Automation Conference. ACM Press, 2014. http://dx.doi.org/10.1145/2593069.2593197.

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Hameed, Fazal, Lars Bauer, and Jorg Henkel. "Adaptive Cache Management for a Combined SRAM and DRAM Cache Hierarchy for Multi-cores." In Design Automation and Test in Europe. IEEE Conference Publications, 2013. http://dx.doi.org/10.7873/date.2013.030.

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Hallnor, Erik G., and Steven K. Reinhardt. "A compressed memory hierarchy using an indirect index cache." In the 3rd workshop. ACM Press, 2004. http://dx.doi.org/10.1145/1054943.1054945.

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Vivekanandarajah, K., T. Srikanthan, and S. Bhattacharyya. "Dynamic filter cache for low power instruction memory hierarchy." In Euromicro Symposium on Digital System Design, 2004. DSD 2004. IEEE, 2004. http://dx.doi.org/10.1109/dsd.2004.1333333.

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Li, Pengcheng, Hao Luo, and Chen Ding. "Rethinking a heap hierarchy as a cache hierarchy: a higher-order theory of memory demand (HOTM)." In ISMM '16: International Symposium on Memory Management. ACM, 2016. http://dx.doi.org/10.1145/2926697.2926708.

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de Souza, Garrenlus, Sergio Bampi, Arthur Cerveira, Bruno Zatt, and Felipe Sampaio. "Evaluation of Cache-Based Memory Hierarchy for HEVC Video Decoding." In 2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI). IEEE, 2020. http://dx.doi.org/10.1109/sbcci50935.2020.9189909.

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Lee, Hyung Gyu, Seungcheol Baek, Chrysostomos Nicopoulos, and Jongman Kim. "An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems." In 2011 IEEE 29th International Conference on Computer Design (ICCD 2011). IEEE, 2011. http://dx.doi.org/10.1109/iccd.2011.6081427.

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Lin, Ye-Jyun, Chia-Lin Yang, Hsiang-Pang Li, and Cheng-Yuan Michael Wang. "A buffer cache architecture for smartphones with hybrid DRAM/PCM memory." In 2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA). IEEE, 2015. http://dx.doi.org/10.1109/nvmsa.2015.7304363.

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