Relevant bibliographies by topics / Cache memory. Computer algorithms

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Cache memory. Computer algorithms'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 February 2022

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Journal articles on the topic "Cache memory. Computer algorithms"

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Zhu, Wei, and Xiaoyang Zeng. "Decision Tree-Based Adaptive Reconfigurable Cache Scheme." Algorithms 14, no. 6 (2021): 176. http://dx.doi.org/10.3390/a14060176.

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Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the pr
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P, Pratheeksha, and Revathi S. A. "Machine Learning-Based Cache Replacement Policies: A Survey." International Journal of Engineering and Advanced Technology 10, no. 6 (2021): 19–22. http://dx.doi.org/10.35940/ijeat.f2907.0810621.

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Despite extensive developments in improving cache hit rates, designing an optimal cache replacement policy that mimics Belady’s algorithm still remains a challenging task. Existing standard static replacement policies does not adapt to the dynamic nature of memory access patterns, and the diversity of computer programs only exacerbates the problem. Several factors affect the design of a replacement policy such as hardware upgrades, memory overheads, memory access patterns, model latency, etc. The amalgamation of a fundamental concept like cache replacement with advanced machine learning algori
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Vishnekov, A. V., and E. M. Ivanova. "DYNAMIC CONTROL METHODS OF CACHE LINES REPLACEMENT POLICY." Vestnik komp'iuternykh i informatsionnykh tekhnologii, no. 191 (May 2020): 49–56. http://dx.doi.org/10.14489/vkit.2020.05.pp.049-056.

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The paper investigates the issues of increasing the performance of computing systems by improving the efficiency of cache memory, analyzes the efficiency indicators of replacement algorithms. We show the necessity of creation of automated or automatic means for cache memory tuning in the current conditions of program code execution, namely a dynamic cache replacement algorithms control by replacement of the current replacement algorithm by more effective one in current computation conditions. Methods development for caching policy control based on the program type definition: cyclic, sequentia
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Vishnekov, A. V., and E. M. Ivanova. "DYNAMIC CONTROL METHODS OF CACHE LINES REPLACEMENT POLICY." Vestnik komp'iuternykh i informatsionnykh tekhnologii, no. 191 (May 2020): 49–56. http://dx.doi.org/10.14489/vkit.2020.05.pp.049-056.

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The paper investigates the issues of increasing the performance of computing systems by improving the efficiency of cache memory, analyzes the efficiency indicators of replacement algorithms. We show the necessity of creation of automated or automatic means for cache memory tuning in the current conditions of program code execution, namely a dynamic cache replacement algorithms control by replacement of the current replacement algorithm by more effective one in current computation conditions. Methods development for caching policy control based on the program type definition: cyclic, sequentia
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Brodal, Gerth Stølting, and Konstantinos Mampentzidis. "Cache Oblivious Algorithms for Computing the Triplet Distance between Trees." ACM Journal of Experimental Algorithmics 26 (July 8, 2021): 1–44. http://dx.doi.org/10.1145/3433651.

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We consider the problem of computing the triplet distance between two rooted unordered trees with n labeled leaves. Introduced by Dobson in 1975, the triplet distance is the number of leaf triples that induce different topologies in the two trees. The current theoretically fastest algorithm is an O( n log n ) algorithm by Brodal et al. (SODA 2013). Recently, Jansson and Rajaby proposed a new algorithm that, while slower in theory, requiring O( n log 3 n ) time, in practice it outperforms the theoretically faster O( n log n ) algorithm. Both algorithms do not scale to external memory. We presen
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Zhao, Yao, Jian Dong, Hongwei Liu, Jin Wu, and Yanxin Liu. "Performance Improvement of DAG-Aware Task Scheduling Algorithms with Efficient Cache Management in Spark." Electronics 10, no. 16 (2021): 1874. http://dx.doi.org/10.3390/electronics10161874.

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Directed acyclic graph (DAG)-aware task scheduling algorithms have been studied extensively in recent years, and these algorithms have achieved significant performance improvements in data-parallel analytic platforms. However, current DAG-aware task scheduling algorithms, among which HEFT and GRAPHENE are notable, pay little attention to the cache management policy, which plays a vital role in in-memory data-parallel systems such as Spark. Cache management policies that are designed for Spark exhibit poor performance in DAG-aware task-scheduling algorithms, which leads to cache misses and perf
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Zavadskyi, I. O. "Pattern matching by the terms of cache memory limitations." Bulletin of Taras Shevchenko National University of Kyiv. Series: Physics and Mathematics, no. 3 (2019): 56–59. http://dx.doi.org/10.17721/1812-5409.2019/3.8.

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A few known techniques of exact pattern matching, such as 2-byte read, skip loop, and sliding search windows, are improved and applied to pattern matching algorithms, performing over 256-ary alphabets. Instead of 2-byte read, we offer “1.5-byte read”, i.e. reading more than 8 but less than 16 bits of two sequential bytes of a text at each iteration of a search loop. This allows us to fit the search table into L1 cache memory, which significantly improves the algorithm performance. Also, we introduce the so-called double skip loop instead of single one, resolve problems caused by endianness of
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Hać, Anna. "Design algorithms for asynchronous operations in cache memory." ACM SIGMETRICS Performance Evaluation Review 16, no. 2-4 (1989): 21. http://dx.doi.org/10.1145/1041911.1041914.

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BEIN, WOLFGANG, LAWRENCE L. LARMORE, and RÜDIGER REISCHUK. "KNOWLEDGE STATES FOR THE CACHING PROBLEM IN SHARED MEMORY MULTIPROCESSOR SYSTEMS." International Journal of Foundations of Computer Science 20, no. 01 (2009): 167–83. http://dx.doi.org/10.1142/s0129054109006504.

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Multiprocessor systems with a global shared memory provide logically uniform data access. To hide latencies when accessing global memory each processor makes use of a private cache. Several copies of a data item may exist concurrently in the system. To guarantee consistency when updating an item a processor must invalidate copies of the item in other private caches. To exclude the effect of classical paging faults, one assumes that each processor knows its own data access sequence, but does not know the sequence of future invalidations requested by other processors. Performance of a processor
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Al-Marakeby, A. "CACHE MEMORY LOACLITY OPTIMIZATION FOR IMPLEMENTATION OF COMPUTER VISION AND IMAGE PROCESSING ALGORITHMS." Journal of Al-Azhar University Engineering Sector 15, no. 55 (2020): 604–13. http://dx.doi.org/10.21608/auej.2020.87899.

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Dissertations / Theses on the topic "Cache memory. Computer algorithms"

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Furis, Mihai Alexandru Johnson Jeremy. "Cache miss analysis of Walsh-Hadamard Transform algorithms /." Philadelphia : Drexel University, 2003. http://dspace.library.drexel.edu/handle/1721.1/109.

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Slocum, Joshua Foster. "Performance analysis of cache oblivious Algorithms in the Fresh Breeze memory model." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/76998.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 31-32).<br>The Fresh Breeze program execution model was designed for easy, reliable and massively scalable parallel performance. The model achieves these goals by combining a radical memory model with efficient fine-grain parallelsim and managing both in hardware. This presents a unique opportunity for studying program execution in a system whose memory behavior is not well understood. In this th
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Korupolu, Madhukar. "Placement algorithms for hierarchical cooperative caching and other location problems /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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Thesis (Ph. D.)--University of Texas at Austin, 1999.<br>Vita. Includes bibliographical references (leaves 143-150), Copy 2 (p. 135-142). Available also in a digital version from Dissertation Abstracts.
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Liang, Shuang. "Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1268420517.

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Lindqvist, Maria. "Dynamic Eviction Set Algorithms and Their Applicability to Cache Characterisation." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-420317.

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Eviction sets are groups of memory addresses that map to the same cache set. They can be used to perform efficient information-leaking attacks against the cache memory, so-called cache side channel attacks. In this project, two different algorithms that find such sets are implemented and compared. The second of the algorithms improves on the first by using a concept called group testing. It is also evaluated if these algorithms can be used to analyse or reverse engineer the cache characteristics, which is a new area of application for this type of algorithms. The results show that the optimise
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Kamath, Akash S. "An efficient algorithm for caching online analytical processing objects in a distributed environment." Ohio : Ohio University, 2002. http://www.ohiolink.edu/etd/view.cgi?ohiou1174678903.

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Lim, Nien Yi. "Separating instruction fetches from memory accesses ILAR (Instruction Line Associative Registers) /." Lexington, Ky. : [University of Kentucky Libraries], 2009. http://hdl.handle.net/10225/1121.

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Thesis (M.S.)--University of Kentucky, 2009.<br>Title from document title page (viewed on May 6, 2010). Document formatted into pages; contains: viii, 59 p. : ill. (some col.). Includes abstract and vita. Includes bibliographical references (p. 56-58).
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Fix, James D. "Cache performance analysis of algorithms /." Thesis, Connect to this title online; UW restricted, 2002. http://hdl.handle.net/1773/6880.

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Prokop, Harald 1975. "Cache-oblivious algorithms." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80568.

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Brewer, Jeffery Ramon. "Reconfigurable Cache Memory." OpenSIUC, 2009. https://opensiuc.lib.siu.edu/theses/48.

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AN ABSTRACT OF THE THESIS OF Jeffery R. Brewer, for the Master degree in Electrical Computer Engineer, presented on May 22, 2009 at Southern Illinois University Carbondale. TITLE: Reconfigurable Cache Memory MAJOR PROFESSOR: Dr. Nazeih Botros As chip designers continue to push the performance of microprocessors to higher levels the energy demand grows. The increase need for integrated chips that provide energy savings without degrading performance is paramount. The cache memory is typically over fifty percent of the size of today's microprocessor chip, and consumes a significant percentage of
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Books on the topic "Cache memory. Computer algorithms"

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Nicol, David. Massively parallel algorithms for trace-driven cache simulations. National Aeronautics and Space Administration, Langley Research Center, 1991.

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Handy, Jim. The cache memory book. Academic Press, 1993.

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The cache memory book. 2nd ed. Academic Press, 1998.

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Jacob, Bruce. Memory systems: Cache, DRAM, disk. Morgan Kaufmann Publishers, 2008.

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Balasubramonian, Rajeev. Multi-core cache hierarchies. Morgan & Claypool, 2011.

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Sorin, Daniel J. A primer on memory consistency and cache coherence. Morgan & Claypool, 2011.

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Algorithms and data structures for external memory. Published, sold, and distributed by now Publishers, 2008.

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Przybylski, Steven A. Cache and memory hierarchy design: A performance-directed approach. Morgan Kaufmann Publishers, 1990.

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Rafael, Lins, ed. Garbage collection: Algorithms for automatic dynamic memory management. Wiley, 1996.

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M, Abello James, and Vitter Jeffrey Scott 1955-, eds. External memory algorithms: DIMACS Workshop External Memory and Visualization, May 20-22, 1998. American Mathematical Society, 1999.

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Book chapters on the topic "Cache memory. Computer algorithms"

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Oh, Chansoo, Dong Hyun Kang, Minho Lee, and Young Ik Eom. "A Buffer Cache Algorithm for Hybrid Memory Architecture in Mobile Devices." In Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-38904-2_30.

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Kumar, Piyush. "Cache Oblivious Algorithms." In Algorithms for Memory Hierarchies. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-36574-5_9.

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Kowarschik, Markus, and Christian Weiß. "An Overview of Cache Optimization Techniques and Cache-Aware Numerical Algorithms." In Algorithms for Memory Hierarchies. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-36574-5_10.

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Leiserson, Charles E. "Cache-Oblivious Algorithms." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-44849-7_5.

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Getov, Vladimir. "Benchmarking the cache memory effect." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-60902-4_27.

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Franklin, Michael J. "Performance of Cache Consistency Algorithms." In The Kluwer International Series in Engineering and Computer Science. Springer US, 1996. http://dx.doi.org/10.1007/978-1-4613-1363-2_5.

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Wu, Weiwei, Minming Li, He Huang, and Enhong Chen. "Speed Scaling Problems with Memory/Cache Consideration." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-29952-0_40.

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Kossmann, Jan, Markus Dreseler, Timo Gasda, Matthias Uflacker, and Hasso Plattner. "Visual Evaluation of SQL Plan Cache Algorithms." In Lecture Notes in Computer Science. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-92013-9_31.

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Michael, Maged M. "Memory Management in Concurrent Algorithms." In Computer Aided Verification. Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-14295-6_4.

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Rui, Hou, Fuxin Zhang, and Weiwu Hu. "A Memory Bandwidth Effective Cache Store Miss Policy." In Advances in Computer Systems Architecture. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11572961_61.

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Conference papers on the topic "Cache memory. Computer algorithms"

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Nimako, Gideon, E. J. Otoo, and Daniel Ohene-Kwofie. "Cache-sensitive MapReduce DGEMM algorithms for shared memory architectures." In the South African Institute for Computer Scientists and Information Technologists Conference. ACM Press, 2012. http://dx.doi.org/10.1145/2389836.2389849.

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Kumar, Akhilesh, and Laxmi N. Bhuyan. "Parallel FFT Algorithms for Cache Based Shared Memory Multiprocessors." In 1993 International Conference on Parallel Processing - ICPP'93 Vol3. IEEE, 1993. http://dx.doi.org/10.1109/icpp.1993.136.

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Kapoor, Bhanu, and Patrick W. Bosshart. "Cache parameters and memory power consumption of video algorithms." In Photonics West '98 Electronic Imaging, edited by Sethuraman Panchanathan, Frans Sijstermans, and Subramania I. Sudharsanan. SPIE, 1998. http://dx.doi.org/10.1117/12.304671.

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Hac, A. "Sensitivity study of asynchronous algorithms in disk buffer cache memory." In Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences. IEEE, 1992. http://dx.doi.org/10.1109/hicss.1992.183149.

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Amory, Ibrahim, and Safaa Omran. "Comparative Study of Reconfigurable Cache Memory." In 2nd International Conference of Cihan University-Erbil on Communication Engineering and Computer Science. Cihan University-Erbil, 2017. http://dx.doi.org/10.24086/cocos17.01.

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Ozturk, O., G. Chen, M. Kandemir, and M. Karakoy. "Cache Miss Clustering for Banked Memory Systems." In 2006 IEEE/ACM International Conference on Computer Aided Design. IEEE, 2006. http://dx.doi.org/10.1109/iccad.2006.320143.

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Kuszmaul, William, and Alek Westover. "Cache-Efficient Parallel-Partition Algorithms using Exclusive-Read-and-Write Memory." In SPAA '20: 32nd ACM Symposium on Parallelism in Algorithms and Architectures. ACM, 2020. http://dx.doi.org/10.1145/3350755.3400234.

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Gu, Yongbin, and Lizhong Chen. "CART: Cache Access Reordering Tree for Efficient Cache and Memory Accesses in GPUs." In 2018 IEEE 36th International Conference on Computer Design (ICCD). IEEE, 2018. http://dx.doi.org/10.1109/iccd.2018.00046.

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Koh, Cheng-Kok, Weng-Fai Wong, Yiran Chen, and Hai Li. "The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies." In 2009 IEEE International Conference on Computer Design (ICCD 2009). IEEE, 2009. http://dx.doi.org/10.1109/iccd.2009.5413145.

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Rani, Manira S., Muhammad F. Mridha, and Abu S. Asaduzzaman. "Investigating the impact of multimedia applications on multicore cache memory subsystems." In Computer Engineering (ICECE). IEEE, 2010. http://dx.doi.org/10.1109/icelce.2010.5700787.

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