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Relevant bibliographies by topics / Cadence Design Systems

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Academic literature on the topic 'Cadence Design Systems'

Author: Grafiati

Published: 4 June 2021

Last updated: 17 February 2022

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Journal articles on the topic "Cadence Design Systems"

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SORIANO REYES, CARLOS, ASIER ARIZAGA GURRUTXAGA, ROBERTO OCAÑA PEREZ, MADDI SANCHEZ ARGOITIA, ANDREAS STEPHEN, RAFAEL SANCHEZ MARTINEZ, and LUIS URIARTE IBARROLA. "DESIGN OF A HIGH PERFORMANCE LASER MICRO-DRILLING MACHINE FOR THE AERONAUTICAL SECTOR." DYNA 96, no. 2 (March 1, 2021): 130–33. http://dx.doi.org/10.6036/9391.

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This article describes the design of a high cadence laser micro-drilling machine for the manufacture of large micro-drilled panels, which will form part of the leading edge of tail stabilisers on future commercial aircraft. This type of microperforated surface will be of great interest mainly in the aeronautical field, since it will improve the aerodynamic performance of the aircrafts supposing a fuel saving of up to 10 %. Manufacturing requirements demand through-holes of around 0.1 mm at a cadence equal to or greater than 300 holes per second. The quality of each of the holes, as well as the precision of the distance between them has been decisive in the design phase. The machine will be equipped with on-site measurement and defect detection systems to ensure the quality of the holes. Keywords: microdrilling, laser, titanium, machine, HLFC

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CVS, Chaitanya, Sundaresan C, P. R Venkateswaran, and Keerthana Prasad. "Design of modified booth based multiplier with carry pre-computation." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 3 (March 1, 2019): 1048. http://dx.doi.org/10.11591/ijeecs.v13.i3.pp1048-1055.

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Arithmetic unit is the most important component of modern embedded computer systems. Arithmetic unit generally includes floating point and fixed-point arithmetic operations and trigonometric functions. Multipliers units are the most important hardware structures in a complex arithmetic unit. With increase in chip frequency, the designer must be able to find the best set of trade-offs. The ability for faster computation is essential to achieve high performance in many DSP and Graphic processing algorithms and is why there is at least one dedicated Multiplier unit in all of the modern commercial DSP processors. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. A novel modified booth multiplier design for high speed VLSI applications using pre-computation logic has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

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Ma, Kezheng, Rene Van Leuken, Maja Vidojkovic, Jac Romme, Simonetta Rampu, Hans Pflug, Li Huang, and Guido Dolmans. "A Precise and High Speed Charge-Pump PLL Model Based on SystemC/SystemC-AMS." International Journal of Electronics and Telecommunications 58, no. 3 (September 2012): 225–32. http://dx.doi.org/10.2478/v10177-012-0031-5.

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Abstract The Phase Locked Loop (PLL) has become an important part of electrical systems. When designing a PLL, an efficient and reliable simulation platform for system evaluation is needed. However, the closed loop simulation of a PLL is time consuming. To address this problem, in this paper, a new PLL model containing both digital and analog parts based on SystemC/SystemC-AMS (BETA version) is presented. Many imperfections such as Voltage Control Oscillator (VCO) noise or reference jitter are included in this model. By comparing with the Matlab model, the SystemC/SystemC-AMS model can dramatically reduce simulation time. Also, by comparing with Analog Devices ADI SimPLL simulation results, Cadence simulation results and real measurement results, the accuracy of the SystemC/SystemC-AMS model is demonstrated. The paper shows the feasibility of a unified design environment for mixed-signal modelling based on SystemC/SystemC-AMS in order to reduce the cost and design time of electrical systems.

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Memlikai, Evisa, Stavroula Kapoulea, Costas Psychalinos, Jerzy Baranowski, Waldemar Bauer, Andrzej Tutaj, and Paweł Piątek. "Design of Fractional-Order Lead Compensator for a Car Suspension System Based on Curve-Fitting Approximation." Fractal and Fractional 5, no. 2 (May 15, 2021): 46. http://dx.doi.org/10.3390/fractalfract5020046.

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An alternative procedure for the implementation of fractional-order compensators is presented in this work. The employment of a curve-fitting-based approximation technique for the approximation of the compensator transfer function offers improved accuracy compared to the Oustaloup and Padé methods. As a design example, a lead compensator intended for usage in car suspension systems is realized. The open-loop and closed-loop behavior of the system is evaluated by post-layout simulation results obtained using the Cadence IC design suite and the Metal Oxide Semiconductor (MOS) transistor models provided by the Austria Mikro Systeme 0.35 m Complementary Metal Oxide Semiconductor (CMOS) process. The derived results verify the efficient performance of the introduced implementation.

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Wang, Kai Yu, Zhe Nan Tang, and Tao Ge. "The Design and Simulation of a CMOS Digital PLL." Applied Mechanics and Materials 48-49 (February 2011): 1227–30. http://dx.doi.org/10.4028/www.scientific.net/amm.48-49.1227.

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In this paper, the charge-pump PLL structure is well analyzed. By using top-down method, the digital PLL is designed from frequency phase detector, charge pump, loop filter, VCO to frequency divider. Based on 0.5μm CMOS mixed signal process, the schematic and layout design is finished on Cadence IC 5.1.4.1, and Hspice is used for the simulation. The layout verification and parasitic extraction is completed on industry mainstream Calibre software. Simulation results show that the digital PLL is with a 100MHz center frequency, the locking range is between 20MHz~60MHz, the locking time is less than 1.5μs, and phase noise is -105dBc/Hz. The design has implemented the digital signal lock function and it can be used as an IP hard core in the clock recovery of communication systems and frequency synthesis of digital systems.

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Williams, Duncan, Bruno Fazenda, Victoria Williamson, and György Fazekas. "On Performance and Perceived Effort in Trail Runners Using Sensor Control to Generate Biosynchronous Music." Sensors 20, no. 16 (August 13, 2020): 4528. http://dx.doi.org/10.3390/s20164528.

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Music has been shown to be capable of improving runners’ performance in treadmill and laboratory-based experiments. This paper evaluates a generative music system, namely HEARTBEATS, designed to create biosignal synchronous music in real-time according to an individual athlete’s heartrate or cadence (steps per minute). The tempo, melody, and timbral features of the generated music are modulated according to biosensor input from each runner using a combination of PPG (Photoplethysmography) and GPS (Global Positioning System) from a wearable sensor, synchronized via Bluetooth. We compare the relative performance of athletes listening to music with heartrate and cadence synchronous tempos, across a randomized trial (N = 54) on a trail course with 76 ft of elevation. Participants were instructed to continue until their self-reported perceived effort went beyond an 18 using the Borg rating of perceived exertion. We found that cadence-synchronous music improved performance and decreased perceived effort in male runners. For female runners, cadence synchronous music improved performance but it was heartrate synchronous music which significantly reduced perceived effort and allowed them to run the longest of all groups tested. This work has implications for the future design and implementation of novel portable music systems and in music-assisted coaching.

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Kladovščikov, Leonid, and Romualdas Navickas. "DESIGN AND INVESTIGATION OF RESISTOR MATRIX FOR ACTIVE ANALOG RC FILTERS." Mokslas - Lietuvos ateitis 12 (January 28, 2020): 1–7. http://dx.doi.org/10.3846/mla.2020.11419.

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Resistor matrixes are widely used in active RC filters as well as in self-tuning systems. Using self-tuning systems for active RC filters, it is possible to automatically tune various parameters of filter – cut-off frequency, gain and quality of filter. Most recent multiband transceivers employ higher order filters for fine bandpass filtering, thus number of passive components increases. In this work, a novel resistor matrix structure and design method is proposed. Proposed resistor matrix structure compensates both integrated circuit process variations and temperature change. Proposed resistor matrix is designed using 0.18 μm TSMC CMOS technology node and investigated using Cadence Virtuoso software. For most accurate comparison of different resistor matrices, all of them were designed in same technology node using design techniques described in other authors’ works.

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Et.al, Yarlagadda Archana. "Design of 16-Bit SAR ADC Using DTMOS Technique." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (April 10, 2021): 3046–54. http://dx.doi.org/10.17762/turcomat.v12i3.1339.

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This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

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Kakarla Hari Kishore, Yarlagadda Archana,. "Design of 16-Bit SAR ADC Using DTMOS Technique." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (April 11, 2021): 144–52. http://dx.doi.org/10.17762/turcomat.v12i5.806.

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This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

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Alraho, Senan, and Andreas König. "Wide input range, fully-differential indirect current feedback instrumentation amplifier for self-x sensory systems / Symmetrischer Instrumentierungsverstärker mit indirekter Stromgegenkopplung und hoher Eingangsignalspanne für integrierte Sensorsysteme mit Self-x-Eigenschaften." tm - Technisches Messen 86, s1 (September 1, 2019): 62–66. http://dx.doi.org/10.1515/teme-2019-0054.

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AbstractThis paper research presents the design of wide input range indirect current feedback-instrumentation amplifier (CFIA). In order to extend the input range without sacrificing the amplifier performance, the negative feedback is applied to the source coupled differential pairs inputs. The feedback network and the biasing current can be programmed to work at different values to meet different signal conditions or to self-correct the drift in the amplifier properties. The simulated input range Vin; P-P=1.6 V with total harmonic distortion of 0.93 % at 5 MHz frequency. Thus the proposed CFIA is very suitable to read the high speed and high common mode range TMR differential voltage sensor signal. The circuit is implemented using the CMOS 0.35 μm technology from Austriamicrosystems (AMS) and by using Cadence Virtuoso design tools.

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Dissertations / Theses on the topic "Cadence Design Systems"

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Bartholomew, David Ray. "Design of a High Speed Mixed Signal CMOS Mutliplying Circuit." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd362.pdf.

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Park, Cheolmin S. M. Massachusetts Institute of Technology. "Global product development in semiconductor industry : Intel -- Tick-Tock product development cadence." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/43113.

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Thesis (S.M.)--Massachusetts Institute of Technology, System Design and Management Program, 2008.
Includes bibliographical references (p. 124-142).
This thesis investigates on changes in semiconductor industry's product development methodology by following Intel's product development from year 2000. Intel was challenged by customer's preference change, competitors new enhanced product, internet bubble burst economy, and miss steps in the business strategy. Dynamics of these challenges drove Intel to develop a new product strategy: Tick-Tock product cadence. The paper discusses reasons why Intel landed at the Tick-tock strategy and results how strong product portfolio Intel ended up constructing. The thesis further discusses how the new "Global Product Development" strategy evolves, which can take advantage of TickTock cadence and deliver it to the next level helped from the effective GPD and systems engineering deployment.
by Cheolmin Park.
S.M.

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Delgado, Segura Sergi. "Towards a better understanding of Bitcoin: from system analyses to new protocol designs." Doctoral thesis, Universitat Autònoma de Barcelona, 2018. http://hdl.handle.net/10803/664349.

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Bitcoin ha donat peu a un dels majors canvis de paradigma de l’últim segle respecte a com entenem i utilitzem els diners. El naixement de les criptomonedes ha obert la porta a un sistema econòmic distribuït on la necessitat de terceres parts de confiança, o d’entitats centrals, ha estat substituïda per la criptografia i el flux obert d’informació entre tots els actors del sistema, construint d’aquesta forma un registre de transaccions comú conegut com a blockchain. Aquest canvi de paradigma, però, comporta certes implicacions que, de no ser tractades adientment, poden comprometre la seguretat del sistema. En aquesta tesis ens hem centrat en analitzar dos dels grans components de Bitcoin: la seva xarxa P2P i el conjunt de monedes en circulació. Amb aquest anàlisis es pretén identificar els punts forts i les febleses de Bitcoin, amb l’objectiu de proposar solucions i/o millores per aquestes. Aquests anàlisis ens han permès, per una banda, caracteritzar les xarxes P2P de criptomonedes, i, per altra banda, identificar un dels actuals problemes d’escalabilitat de Bitcoin: les monedes no rentables. D’altra banda, i un cop assolit un coneixement suficient del sistema, la tesis s’ha centrat en el disseny de protocols per estendre la funcionalitat de Bitcoin en diferents escenaris de pagament. A més a més, s’ha proposat una solució per reduir la probabilitat de ser estafat a l’utilitzar transaccions sense confirmar. I finalment, s’ha dissenyat un protocol de compra-venta de dades utilitzant Bitcoin, eliminant la necessitat inherent de confiança per part del comprador.
Bitcoin has kicked off one of the biggest paradigm shifts of the last century regarding how we understand and use money. The birth of criptocurrencies lays the foundations of a new financial system, where the need of trusted third parties, or central authorities, has been replaced by cryptography and an open flow of information between all the actors of the system. By sharing all the information regarding the operations of the system, all users can eventually agree in a distributed ledger, known as blockchain. Such a paradigm shift, however, poses some threads that, if not properly handled, may compromise the security of the system. In this thesis we have studied two of the core components of Bitcoin: its P2P network, and the set of unspent Bitcoins. Such analysis aimed to spot the strengths and weaknesses of the system in order to design solutions for them. The outcomes of our analyses have been, on the one side, characterizing the cryptocurrency P2P networks and, on the other side, spotting one of the current Bitcoin scalability problems: the unprofitable coins. Moreover, after analysing the system and obtaining a deep understanding of it, the thesis has focused on designing protocols to extend Bitcoin’s functionality in different payment scenarios. First, we have designed a solution to reduce the likelihood of a merchant of being deceived when accepting zero-confirmation transactions. Finally, we have designed a fair protocol for data trading using Bitcoin, where the exchange between data and coins is performed atomically.

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"A feasibility study on what can be outsourced to Cadence Design Systems by Motorola Semiconductor Products Sector, Consumer Systems Group in Hong Kong." 1998. http://library.cuhk.edu.hk/record=b5889381.

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by Yu, Lawrence Kwok Cheung.
Thesis (M.B.A.)--Chinese University of Hong Kong, 1998.
Includes bibliographical references (leaves 46-47).
ABSTRACT --- p.iii
TABLE OF CONTENTS --- p.iv
LIST OF TABLES --- p.vi
ACKNOWLEDGMENT --- p.vii
Chapter
Chapter I. --- INTRODUCTION --- p.1
Benefits of Outsourcing --- p.1
Strategic Benefits --- p.1
Financial Benefits --- p.2
Operational Benefits --- p.3
Human Resources Benefits --- p.3
Risks of Outsourcing --- p.4
Strategic Risks --- p.4
Financial Risks --- p.4
Operational Risks --- p.5
Human Resources Risks --- p.6
Outsourcing Issues --- p.7
Feasibility and Planning --- p.7
Outsourcing Candidate Identification --- p.8
Outsourcing Engagement --- p.10
Managing the Outsourcing Contract --- p.12
Human Resources Development --- p.14
Outsourcing Post-mortem Analysis --- p.14
Other Important Findings --- p.15
Outsourcing Trends --- p.16
Chapter II. --- MOTOROLA SPS CONSUMER SYSTEMS GROUP --- p.19
Background --- p.19
CSG Needs --- p.20
Analyzing Outsourcing to Cadence --- p.21
Chapter III. --- REVIEW OF CADENCE DESIGN SYSTEMS --- p.22
Company Background --- p.22
Cadence Design Services --- p.23
Multimedia Design Services --- p.26
Recent Cadence Design Services News --- p.27
Chapter IV. --- MOTOROLA SPS AND CADENCE --- p.28
Past Cadence Outsourcing Projects --- p.28
Views of Colleagues on Past Cadence Outsourcing Projects --- p.30
Views of Colleagues on Outsourcing Design Work to Cadence --- p.32
Chapter V. --- ANALYSIS --- p.35
Technical Issues --- p.35
Economic Issues --- p.36
Legal Issues --- p.37
Operational Issues --- p.37
Sensitivity Issues --- p.38
Other Analyses --- p.39
Chapter VI. --- RECOMMENDATIONS AND CONCLUSIONS --- p.41
Other Recommendations --- p.42
Conclusions --- p.43
APPENDIX --- p.44
BIBLIOGRAPHY --- p.46

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Books on the topic "Cadence Design Systems"

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Disabato, Nick. Cadence & Slang. Ann Arbor: Sheridan Books, 2010.

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Ltd, ICON Group. CADENCE DESIGN SYSTEMS, INC.: Labor Productivity Benchmarks and International Gap Analysis (Labor Productivity Series). 2nd ed. Icon Group International, 2000.

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Ltd, ICON Group. CADENCE DESIGN SYSTEMS, INC.: International Competitive Benchmarks and Financial Gap Analysis (Financial Performance Series). 2nd ed. Icon Group International, 2000.

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Book chapters on the topic "Cadence Design Systems"

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Balan, Nikhitha C., and Abinkant A. Jose. "Accumulator Design in Cadence 90 nm Technology." In Advances in Intelligent Systems and Computing, 273–84. New Delhi: Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2656-7_24.

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Savarese, Giancarlo, and Salvatore Geraci. "Realization of a Place and Route Flow Using PKS, a New Cadence Design System Tool." In Microelectronics and Microsystems, 75–83. London: Springer London, 2000. http://dx.doi.org/10.1007/978-1-4471-0671-5_4.

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"Fullchip, three-dimensional, shapesbased RLC extractionThis work was supported in part by the National Science Foundation under Grant CCR9734216 and by a gift from Cadence Design Systems." In Signal Integrity Effects in Custom IC and ASIC Designs. IEEE, 2009. http://dx.doi.org/10.1109/9780470546413.ch21.

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Conference papers on the topic "Cadence Design Systems"

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"Cadence academic network." In 2016 MIXDES - 23rd International Conference "Mixed Design of Integrated Circuits and Systems". IEEE, 2016. http://dx.doi.org/10.1109/mixdes.2016.7529802.

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Liu, He, Yifu Zhang, Xue Jiang, and Shuang Zhang. "Design of switching power supply based on Cadence." In 2017 First International Conference on Electronics Instrumentation & Information Systems (EIIS). IEEE, 2017. http://dx.doi.org/10.1109/eiis.2017.8298639.

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Higuchi, Gai, Kengo Ohnishi, Kohei Tsuda, Hiroyuki Matsubara, and Isamu Kajitani. "Hand design priority based on cadence of grasping direction in deskwork." In 2019 IEEE International Conference on Systems, Man and Cybernetics (SMC). IEEE, 2019. http://dx.doi.org/10.1109/smc.2019.8914023.

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Lukose, Sanjana Anna, and Anu Assis. "Full custom design flow for a transimpedance amplifier using Cadence Virtuoso." In PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON MICROELECTRONICS, SIGNALS AND SYSTEMS 2019. AIP Publishing, 2020. http://dx.doi.org/10.1063/5.0003971.

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Venkatesan, Chandran, M. Thabsera Sulthana, M. G. Sumithra, and M. Suriya. "Design of a 16-Bit Harvard Structure RISC Processor in Cadence 45nm Technology." In 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS). IEEE, 2019. http://dx.doi.org/10.1109/icaccs.2019.8728479.

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Sitaram, Kalambe Ankita, Y. V. Joshi, and Neelima R. Kolhare. "Design of an op-amp as a Comparator of 10 bit Split SAR ADC using Cadence tool." In 2015 International Conference on Smart Sensors and Systems (IC-SSS). IEEE, 2015. http://dx.doi.org/10.1109/smartsens.2015.7873607.

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Kuzmin, Pavel. "DESIGNING A MICROPROCESSOR TOPOLOGY WITH THE MIPS ARCHITECTURE." In International Forum “Microelectronics – 2020”. Joung Scientists Scholarship “Microelectronics – 2020”. XIII International conference «Silicon – 2020». XII young scientists scholarship for silicon nanostructures and devices physics, material science, process and analysis. LLC MAKS Press, 2020. http://dx.doi.org/10.29003/m1663.silicon-2020/400-402.

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based on specialized cadence Design Systems CAD packages, the architecture of an open-source MIPS microprocessor project is considered as a training example, and a route for designing the topology of its main components is developed.

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LaPrè, Andrew, and Frank Sup. "A Control Strategy for an Active Alignment Transtibial Prosthesis." In ASME 2015 Dynamic Systems and Control Conference. American Society of Mechanical Engineers, 2015. http://dx.doi.org/10.1115/dscc2015-9948.

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This paper presents a control approach for an experimental transtibial prosthesis that can actively realign the residual limb in relation to prosthetic foot during the stance phase of gait. The realignment objective is to inject positive power into the gait cycle while actively reducing the magnitude of the sagittal moment transferred to the residual limb. The altered gait dynamics of this new type of prosthesis require a control approach that coordinates its function with a user’s gait cycle. This paper overviews the mechanical design of the prosthesis development, the proposed finite-state adaptive controller, and presents experimental results for constant cadence walking and adaptation while changing walking speeds.

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Casas, Jonathan, Chen-Hao Chang, and Victor H. Duenas. "Motorized and Functional Electrical Stimulation Induced Cycling via Switched Adaptive Concurrent Learning Control." In ASME 2020 Dynamic Systems and Control Conference. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/dscc2020-3311.

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Abstract Cycling induced by functional electrical stimulation (FES) with motorized assistance is a rehabilitative approach for individuals with movement impairments. In this paper, an adaptive controller is designed for cadence tracking by switching across multiple muscle groups and an electric motor. The control design and analysis are based on a recently developed adaptive method called integral concurrent learning and an invariance-like tool to ensure stability of switched adaptive systems. A Lyapunov-based stability analysis for the overall switched rider-cycle system is segregated into two phases. During the first phase when sufficient learning has not been attained, which is quantified by a finite excitation condition, global asymptotic tracking and bounded parameter estimation are guaranteed. In the second phase, global exponential tracking and parameter convergence is ensured after the finite excitation condition is satisfied for all the subsystems within a finite time.

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Riesener, Michael, Christian Doelle, Sebastian Schloesser, and Guenther Schuh. "Prototype Design in Agile Product Development Processes for Technical Systems." In ASME 2019 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/detc2019-97008.

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Abstract Agile development processes such as Scrum have been successfully applied in the software industry for many years. Based on experience, industrial practitioners indicate three predominant benefits of agile development processes compared to traditional software development processes. First of all, development results better fit customers’ and other stakeholders’ needs. That is because they are intensively involved in the development process by receiving, applying and assessing functional software increments in a defined cadence throughout the development process. Secondly, agile development processes better cope with unexpected changes in the development process due to the built-in process flexibility. Lastly, development speed has significantly increased in most of the agile software development projects, resulting in a shorter time-to-market. Especially in the context of radical innovations for technical systems, manufacturing companies are striving for approaches to optimize their development processes in a similar direction. Traditional plan-oriented development approaches such as VDI 2221 or Cooper’s Stage-Gate Process turn out to be insufficiently customer oriented, too inflexible and project duration is usually too long to reach an adequate time-to-market. For that reason, a large community in academia and industrial practice is developing and implementing approaches to adapt agile software development practices for the development of technical systems. However, a current study in industrial practice reveals that out of 23 objectives, that are expected when introducing agile development processes to technical systems, the three objectives mentioned above, show the largest negative deviations from expected benefit to realized benefit. Therefore, the overall goal of this research is to address these gaps by developing an explicit methodological approach for an agile development of technical systems. It turns out, that mainly the role of prototyping and the way product specifications are handled during the development process change significantly in the course of introducing agility to development of technical systems. Agile practitioners strive to not necessarily define product specifications comprehensively upfront, as it is postulated in plan-oriented development processes. In contrast, product specifications, which are of major importance to the overall development project, are specified and validated with customers and other stakeholders in early prototypes. Therefore, prototypes are realized in a defined cadence throughout the development process to gradually specify and validate the product. However, the way product specifications are prioritized and selected in the development of technical systems has to differ substantially from the general way Scrum or other existing agile development processes propose. That is because technical systems are characterized by multiple technical interrelations, resulting in informational dependencies for the development process. For that reason, a prioritization along criteria such as customer value, development effort and risk seems too narrow in the context of technical systems. In fact, the prioritization of product specifications has to consider both, the value being generated by their realization as well as the informational dependencies towards other specifications. Furthermore, when designing a prototype, time constraints need to be particularly considered due to lead times in parts delivery and prototype production. Therefore, this paper introduces a methodology to prioritize and select technical design parameters in agile development processes. The methodology can be applied in the cyclical sprint planning that aims at defining the scope of the next prototype to be developed. As outlined above, the major paradigms of value generation, informational dependencies as well as lead-time and effort are crucial when adapting agile for technical systems and are consequently implemented in the methodology. These paradigms are operationalized to explicitly address the mentioned major objectives of agile development processes, which are currently showing are large gap between expected benefit and realized benefit in industrial practice. The methodology is applied to the real development process of an RGB laser light source for digital cinema projectors, which is summarized as a case study in the paper. Insights from this application are equally discussed as the resulting next steps in further developing and aligning the methodology to the needs of industrial practice.

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