Journal articles: 'Cadence Design Systems'

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SORIANO REYES, CARLOS, ASIER ARIZAGA GURRUTXAGA, ROBERTO OCAÑA PEREZ, MADDI SANCHEZ ARGOITIA, ANDREAS STEPHEN, RAFAEL SANCHEZ MARTINEZ, and LUIS URIARTE IBARROLA. "DESIGN OF A HIGH PERFORMANCE LASER MICRO-DRILLING MACHINE FOR THE AERONAUTICAL SECTOR." DYNA 96, no. 2 (March 1, 2021): 130–33. http://dx.doi.org/10.6036/9391.

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This article describes the design of a high cadence laser micro-drilling machine for the manufacture of large micro-drilled panels, which will form part of the leading edge of tail stabilisers on future commercial aircraft. This type of microperforated surface will be of great interest mainly in the aeronautical field, since it will improve the aerodynamic performance of the aircrafts supposing a fuel saving of up to 10 %. Manufacturing requirements demand through-holes of around 0.1 mm at a cadence equal to or greater than 300 holes per second. The quality of each of the holes, as well as the precision of the distance between them has been decisive in the design phase. The machine will be equipped with on-site measurement and defect detection systems to ensure the quality of the holes. Keywords: microdrilling, laser, titanium, machine, HLFC

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CVS, Chaitanya, Sundaresan C, P. R Venkateswaran, and Keerthana Prasad. "Design of modified booth based multiplier with carry pre-computation." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 3 (March 1, 2019): 1048. http://dx.doi.org/10.11591/ijeecs.v13.i3.pp1048-1055.

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Arithmetic unit is the most important component of modern embedded computer systems. Arithmetic unit generally includes floating point and fixed-point arithmetic operations and trigonometric functions. Multipliers units are the most important hardware structures in a complex arithmetic unit. With increase in chip frequency, the designer must be able to find the best set of trade-offs. The ability for faster computation is essential to achieve high performance in many DSP and Graphic processing algorithms and is why there is at least one dedicated Multiplier unit in all of the modern commercial DSP processors. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. A novel modified booth multiplier design for high speed VLSI applications using pre-computation logic has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

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Ma, Kezheng, Rene Van Leuken, Maja Vidojkovic, Jac Romme, Simonetta Rampu, Hans Pflug, Li Huang, and Guido Dolmans. "A Precise and High Speed Charge-Pump PLL Model Based on SystemC/SystemC-AMS." International Journal of Electronics and Telecommunications 58, no. 3 (September 2012): 225–32. http://dx.doi.org/10.2478/v10177-012-0031-5.

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Abstract The Phase Locked Loop (PLL) has become an important part of electrical systems. When designing a PLL, an efficient and reliable simulation platform for system evaluation is needed. However, the closed loop simulation of a PLL is time consuming. To address this problem, in this paper, a new PLL model containing both digital and analog parts based on SystemC/SystemC-AMS (BETA version) is presented. Many imperfections such as Voltage Control Oscillator (VCO) noise or reference jitter are included in this model. By comparing with the Matlab model, the SystemC/SystemC-AMS model can dramatically reduce simulation time. Also, by comparing with Analog Devices ADI SimPLL simulation results, Cadence simulation results and real measurement results, the accuracy of the SystemC/SystemC-AMS model is demonstrated. The paper shows the feasibility of a unified design environment for mixed-signal modelling based on SystemC/SystemC-AMS in order to reduce the cost and design time of electrical systems.

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Memlikai, Evisa, Stavroula Kapoulea, Costas Psychalinos, Jerzy Baranowski, Waldemar Bauer, Andrzej Tutaj, and Paweł Piątek. "Design of Fractional-Order Lead Compensator for a Car Suspension System Based on Curve-Fitting Approximation." Fractal and Fractional 5, no. 2 (May 15, 2021): 46. http://dx.doi.org/10.3390/fractalfract5020046.

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An alternative procedure for the implementation of fractional-order compensators is presented in this work. The employment of a curve-fitting-based approximation technique for the approximation of the compensator transfer function offers improved accuracy compared to the Oustaloup and Padé methods. As a design example, a lead compensator intended for usage in car suspension systems is realized. The open-loop and closed-loop behavior of the system is evaluated by post-layout simulation results obtained using the Cadence IC design suite and the Metal Oxide Semiconductor (MOS) transistor models provided by the Austria Mikro Systeme 0.35 m Complementary Metal Oxide Semiconductor (CMOS) process. The derived results verify the efficient performance of the introduced implementation.

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Wang, Kai Yu, Zhe Nan Tang, and Tao Ge. "The Design and Simulation of a CMOS Digital PLL." Applied Mechanics and Materials 48-49 (February 2011): 1227–30. http://dx.doi.org/10.4028/www.scientific.net/amm.48-49.1227.

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In this paper, the charge-pump PLL structure is well analyzed. By using top-down method, the digital PLL is designed from frequency phase detector, charge pump, loop filter, VCO to frequency divider. Based on 0.5μm CMOS mixed signal process, the schematic and layout design is finished on Cadence IC 5.1.4.1, and Hspice is used for the simulation. The layout verification and parasitic extraction is completed on industry mainstream Calibre software. Simulation results show that the digital PLL is with a 100MHz center frequency, the locking range is between 20MHz~60MHz, the locking time is less than 1.5μs, and phase noise is -105dBc/Hz. The design has implemented the digital signal lock function and it can be used as an IP hard core in the clock recovery of communication systems and frequency synthesis of digital systems.

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Williams, Duncan, Bruno Fazenda, Victoria Williamson, and György Fazekas. "On Performance and Perceived Effort in Trail Runners Using Sensor Control to Generate Biosynchronous Music." Sensors 20, no. 16 (August 13, 2020): 4528. http://dx.doi.org/10.3390/s20164528.

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Music has been shown to be capable of improving runners’ performance in treadmill and laboratory-based experiments. This paper evaluates a generative music system, namely HEARTBEATS, designed to create biosignal synchronous music in real-time according to an individual athlete’s heartrate or cadence (steps per minute). The tempo, melody, and timbral features of the generated music are modulated according to biosensor input from each runner using a combination of PPG (Photoplethysmography) and GPS (Global Positioning System) from a wearable sensor, synchronized via Bluetooth. We compare the relative performance of athletes listening to music with heartrate and cadence synchronous tempos, across a randomized trial (N = 54) on a trail course with 76 ft of elevation. Participants were instructed to continue until their self-reported perceived effort went beyond an 18 using the Borg rating of perceived exertion. We found that cadence-synchronous music improved performance and decreased perceived effort in male runners. For female runners, cadence synchronous music improved performance but it was heartrate synchronous music which significantly reduced perceived effort and allowed them to run the longest of all groups tested. This work has implications for the future design and implementation of novel portable music systems and in music-assisted coaching.

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Kladovščikov, Leonid, and Romualdas Navickas. "DESIGN AND INVESTIGATION OF RESISTOR MATRIX FOR ACTIVE ANALOG RC FILTERS." Mokslas - Lietuvos ateitis 12 (January 28, 2020): 1–7. http://dx.doi.org/10.3846/mla.2020.11419.

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Resistor matrixes are widely used in active RC filters as well as in self-tuning systems. Using self-tuning systems for active RC filters, it is possible to automatically tune various parameters of filter – cut-off frequency, gain and quality of filter. Most recent multiband transceivers employ higher order filters for fine bandpass filtering, thus number of passive components increases. In this work, a novel resistor matrix structure and design method is proposed. Proposed resistor matrix structure compensates both integrated circuit process variations and temperature change. Proposed resistor matrix is designed using 0.18 μm TSMC CMOS technology node and investigated using Cadence Virtuoso software. For most accurate comparison of different resistor matrices, all of them were designed in same technology node using design techniques described in other authors’ works.

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Et.al, Yarlagadda Archana. "Design of 16-Bit SAR ADC Using DTMOS Technique." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (April 10, 2021): 3046–54. http://dx.doi.org/10.17762/turcomat.v12i3.1339.

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This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

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Kakarla Hari Kishore, Yarlagadda Archana,. "Design of 16-Bit SAR ADC Using DTMOS Technique." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (April 11, 2021): 144–52. http://dx.doi.org/10.17762/turcomat.v12i5.806.

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This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

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Alraho, Senan, and Andreas König. "Wide input range, fully-differential indirect current feedback instrumentation amplifier for self-x sensory systems / Symmetrischer Instrumentierungsverstärker mit indirekter Stromgegenkopplung und hoher Eingangsignalspanne für integrierte Sensorsysteme mit Self-x-Eigenschaften." tm - Technisches Messen 86, s1 (September 1, 2019): 62–66. http://dx.doi.org/10.1515/teme-2019-0054.

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AbstractThis paper research presents the design of wide input range indirect current feedback-instrumentation amplifier (CFIA). In order to extend the input range without sacrificing the amplifier performance, the negative feedback is applied to the source coupled differential pairs inputs. The feedback network and the biasing current can be programmed to work at different values to meet different signal conditions or to self-correct the drift in the amplifier properties. The simulated input range Vin; P-P=1.6 V with total harmonic distortion of 0.93 % at 5 MHz frequency. Thus the proposed CFIA is very suitable to read the high speed and high common mode range TMR differential voltage sensor signal. The circuit is implemented using the CMOS 0.35 μm technology from Austriamicrosystems (AMS) and by using Cadence Virtuoso design tools.

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NagaSaiLakshmi, B., and RajaSekhar T. "Design of low- area, power fault tolerant parallel FFTs using trellis codes." International Journal of Engineering & Technology 7, no. 4 (September 17, 2018): 2338. http://dx.doi.org/10.14419/ijet.v7i4.14106.

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Present day electronic circuits are generally affected by the delicate mistakes. To maintain the reliability of the complex systems few techniques have been proposed. For few applications, an algorithmic - based fault tolerance (ABFT) system has attempt to abuse the algorithmic properties to identify and adjust mistakes. One example FFT used. There are various protection schemes to identify and adjust errors in FFTs. It is normal to discover various blocks are working in parallel. Recently; a new method is exploiting to implement a blame tolerance in parallel. In this work, same method is first applicable to parallel FFT and then secured methods are merged that the use of error correction codes (ECCs) and parseval checks are used to detect and correct a single bit fault. Trellis code is applied to parallel FFTs to protect the errors which are used to detect and correct a multibit faults are proposed and evaluated. The 4-point FFT is protected with the input32-bit length .Simulation and Synthesis report for FFT using ECC,SOS,ECC-SOS,Trellis codes are obtained in Xilinx software14.2v.Area,power,delay is analyzed in cadence using 90nm & 180nmTechnology.

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Yasukawa, Koki, Yuta Koike, Taisei Konno, Mizuki Sudo, Kazunori Ohkawara, and Soichi Ando. "Effects of Visual Flow Alterations on Psychophysiological Responses to Virtual Reality Exercise." Perceptual and Motor Skills 128, no. 3 (March 4, 2021): 1169–82. http://dx.doi.org/10.1177/00315125211000861.

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Virtual reality (VR) technology combined with exercise, called VR exercise, is believed to have beneficial effects on mood; but VR factors contributing to improved mood remain ambiguous. The purpose of this study was to examine the effect of visual flow speed on psychophysiological responses (i.e., physiological responses, ratings of perceived exertion or RPE, and mood) to immersive VR exercise in a simulated natural environment. Eighteen male participants ( Mage =23.1, SD = 1.9 years) cycled an ergometer at 80 watts for 5 minutes on three separate occasions while watching a first-person VR movie through VR goggles at three different speeds of visual flow, corresponding to 7.5 km.h−1, 15 km.h−1, and 22.5 km.h−1. The order of the three speeds was randomized in a counterbalanced design. We measured heart rate, oxygen uptake, minute ventilation, respiratory rate, and cadence during the exercise, and we recorded ratings of perceived exertion (RPE) and mood immediately after the exercise. We evaluated mood states with the Two-Dimensional Mood Scale. One-way repeated measures analysis of variance or the Friedman test revealed no significant effects on any physiological variables, RPE or cadence as a result of altered visual flow speed during VR exercise ( p > .05). However, speed of visual flow significantly influenced participant ratings of Vitality ( p = 0.01) and Pleasure ( p = 0.02), with the faster speed resulting in a more positive mood state. As these findings showed that VR exercise with faster visual flow induced positive mood states, we recommend faster visual flow to induce better mood states in VR exercise.

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Kushwah, Preeti, Saurabh Khandelwal, and Shyam Akashe. "Multi-Threshold Voltage CMOS Design for Low-Power Half Adder Circuit." International Journal of Nanoscience 14, no. 05n06 (October 2015): 1550022. http://dx.doi.org/10.1142/s0219581x15500222.

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The new era of portable electronic devices demands lesser power dissipation for longer battery life and design compactability. Leakage current and leakage power are dominating factors which greatly affect the power consumption in low voltage and low power applications. For many numerical representations of binary numbers, combinational circuits like adder, encoder, multiplexer, etc. are useful circuits for arithmetic operation. A novel high speed and low power half adder cell is introduced here which consists of AND gate and OR gate. This cell shows high speed, lower power consumption than conventional half adder. In CMOS technology, transistors used have small area and low power consumption. It is used in various applications like adder, subtract or, multiplexer, ALU and microprocessors digital VLSI systems. As the scaling technology reduces, the leakage power increases. In this paper, multi threshold complementary metal oxide semiconductor (MTCMOS) technique is proposed to reduce the leakage current and leakage power. MTCMOS is an effective circuit level technique that increases the performance of a cell by using both low- and high-threshold voltage transistors. Leakage current is reduced by 85.37% and leakage power is reduced by 87.45% using MTCMOS technique as compared to standard CMOS technique. The half adder design simulation work was performed by cadence simulation tool at 45-nm technology.

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Ali, Khaled Alhaj, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, and Jalal Jomaah. "Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL." Electronics 10, no. 9 (April 24, 2021): 1018. http://dx.doi.org/10.3390/electronics10091018.

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A great deal of effort has recently been devoted to extending the usage of memristor technology from memory to computing. Memristor-based logic design is an emerging concept that targets efficient computing systems. Several logic families have evolved, each with different attributes. Memristor Ratioed Logic (MRL) has been recently introduced as a hybrid memristor–CMOS logic family. MRL requires an efficient design strategy that takes into consideration the implementation phase. This paper presents a novel MRL-based crossbar design: X-MRL. The proposed structure combines the density and scalability attributes of memristive crossbar arrays and the opportunity of their implementation at the top of CMOS layer. The evaluation of the proposed approach is performed through the design of an X-MRL-based full adder. The design is presented with its layout and corresponding simulation results using the Cadence Virtuoso toolset and CMOS 65nm process. The comparison with a pure CMOS implementation is promising in terms of the area, as our approach exhibits a 44.79% area reduction. Moreover, the combined Energy.Delay metric demonstrates a significant improvement (between ×5.7 and ×31) with respect to the available literature.

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Amitrano, Federica, Armando Coccia, Carlo Ricciardi, Leandro Donisi, Giuseppe Cesarelli, Edda Maria Capodaglio, and Giovanni D’Addio. "Design and Validation of an E-Textile-Based Wearable Sock for Remote Gait and Postural Assessment." Sensors 20, no. 22 (November 23, 2020): 6691. http://dx.doi.org/10.3390/s20226691.

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This paper presents a new wearable e-textile based system, named SWEET Sock, for biomedical signals remote monitoring. The system includes a textile sensing sock, an electronic unit for data transmission, a custom-made Android application for real-time signal visualization, and a software desktop for advanced digital signal processing. The device allows the acquisition of angular velocities of the lower limbs and plantar pressure signals, which are postprocessed to have a complete and schematic overview of patient’s clinical status, regarding gait and postural assessment. In this work, device performances are validated by evaluating the agreement between the prototype and an optoelectronic system for gait analysis on a set of free walk acquisitions. Results show good agreement between the systems in the assessment of gait cycle time and cadence, while the presence of systematic and proportional errors are pointed out for swing and stance time parameters. Worse results were obtained in the comparison of spatial metrics. The “wearability” of the system and its comfortable use make it suitable to be used in domestic environment for the continuous remote health monitoring of de-hospitalized patients but also in the ergonomic assessment of health workers, thanks to its low invasiveness.

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Dendouga, Abdelghani, Slimane Oussalah, Damien Thienpont, and Abdenour Lounis. "Multiobjective Genetic Algorithms Program for the Optimization of an OTA for Front-End Electronics." Advances in Electrical Engineering 2014 (August 13, 2014): 1–5. http://dx.doi.org/10.1155/2014/374741.

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The design of an interface to a specific sensor induces costs and design time mainly related to the analog part. So to reduce these costs, it should have been standardized like digital electronics. The aim of the present work is the elaboration of a method based on multiobjectives genetic algorithms (MOGAs) to allow automated synthesis of analog and mixed systems. This proposed methodology is used to find the optimal dimensional transistor parameters (length and width) in order to obtain operational amplifier performances for analog and mixed CMOS-(complementary metal oxide semiconductor-) based circuit applications. Six performances are considered in this study, direct current (DC) gain, unity-gain bandwidth (GBW), phase margin (PM), power consumption (P), area (A), and slew rate (SR). We used the Matlab optimization toolbox to implement the program. Also, by using variables obtained from genetic algorithms, the operational transconductance amplifier (OTA) is simulated by using Cadence Virtuoso Spectre circuit simulator in standard TSMC (Taiwan Semiconductor Manufacturing Company) RF 0.18 μm CMOS technology. A good agreement is observed between the program optimization and electric simulation.

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Alimisis, Vassilis, Christos Dimas, Georgios Pappas, and Paul P. Sotiriadis. "Analog Realization of Fractional-Order Skin-Electrode Model for Tetrapolar Bio-Impedance Measurements." Technologies 8, no. 4 (November 2, 2020): 61. http://dx.doi.org/10.3390/technologies8040061.

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This work compares two design methodologies, emulating both AgCl electrode and skin tissue Cole models for testing and verification of electrical bio-impedance circuits and systems. The models are based on fractional-order elements, are implemented with active components, and capture bio-impedance behaviors up to 10 kHz. Contrary to passive-elements realizations, both architectures using analog filters coupled with adjustable transconductors offer tunability of the fractional capacitors’ parameters. The main objective is to build a tunable active integrated circuitry block that is able to approximate the models’ behavior and can be utilized as a Subject Under Test (SUT) and electrode equivalent in bio-impedance measurement applications. A tetrapolar impedance setup, typical in bio-impedance measurements, is used to demonstrate the performance and accuracy of the presented architectures via Spectre Monte-Carlo simulation. Circuit and post-layout simulations are carried out in 90-nm CMOS process, using the Cadence IC suite.

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Raj, Niranjan, Sagar, Rajeev Kumar Ranjan, Bindu Priyadarshini, and Nicu Bizon. "Electronically Tunable Full Wave Precision Rectifier Using DVCCTAs." Electronics 10, no. 11 (May 25, 2021): 1262. http://dx.doi.org/10.3390/electronics10111262.

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This work presents a voltage mode scheme of a full-wave precision rectifier circuit using an analog building block differential voltage current conveyor transconductance amplifier (DVCCTA) including five NMOS transistors. The proposed design is essentially suited for low voltage and high-frequency input signals. The operation of the proposed rectifier design depends upon the region of operation of NMOS transistors. The output waveform of the presented rectifier design can be made electronically tunable by controlling the bias voltage. The functional correctness and verification of the presented design are performed using 0.25-µm TSMC technology under the supply voltage of ±1.5 V. The absence of a resistor leads to a minimal parasitic effect. To obtain further insight on the robustness of the circuit, a Monte Carlo simulation and corner analysis are also presented. The circuit is verified experimentally by incorporating a breadboard model with the help of commercially available ICs CA3080 (operational transconductance amplifier) and AD844AN (current feedback operational amplifier) and offers remarkable compliance with both theoretical and simulation outcomes. The presented design has been laid out on Cadence virtuoso, which consumes a chip area of 9044 µm2.

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Jmai, Bassem, Vitor Silva, and Paulo M. Mendes. "2D Electronics Based on Graphene Field Effect Transistors: Tutorial for Modelling and Simulation." Micromachines 12, no. 8 (August 18, 2021): 979. http://dx.doi.org/10.3390/mi12080979.

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This paper provides modeling and simulation insights into field-effect transistors based on graphene (GFET), focusing on the devices’ architecture with regards to the position of the gate (top-gated graphene transistors, back-gated graphene transistors, and top-/back-gated graphene transistors), substrate (silicon, silicon carbide, and quartz/glass), and the graphene growth (CVD, CVD on SiC, and mechanical exfoliation). These aspects are explored and discussed in order to facilitate the selection of the appropriate topology for system-level design, based on the most common topologies. Since most of the GFET models reported in the literature are complex and hard to understand, a model of a GFET was implemented and made available in MATLAB, Verilog in Cadence, and VHDL-AMS in Simplorer—useful tools for circuit designers with different backgrounds. A tutorial is presented, enabling the researchers to easily implement the model to predict the performance of their devices. In short, this paper aims to provide the initial knowledge and tools for researchers willing to use GFETs in their designs at the system level, who are looking to implement an initial setup that allows the inclusion of the performance of GFETs.

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Fusca, Marcello, Francesco Negrini, Paolo Perego, Luciana Magoni, Franco Molteni, and Giuseppe Andreoni. "Validation of a Wearable IMU System for Gait Analysis: Protocol and Application to a New System." Applied Sciences 8, no. 7 (July 18, 2018): 1167. http://dx.doi.org/10.3390/app8071167.

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Miniaturized wearable Inertial Measurement Units (IMU) offer new opportunities for the functional assessment of motor functions for medicine, sport, and ergonomics. Sparse reliability validation studies have been conducted without a common specific approach and protocol. A set of guidelines to design validation protocol for these systems is proposed hereafter. They are based on the comparison between video analysis and the gold standard optoelectronic motion capture system for Gait Analysis (GA). A setup of the protocol has been applied to a wearable device implementing an inertial measurement unit and a dedicated harmonic oscillator kinematic model of the center of mass. In total, 10 healthy volunteers took part in the study, and four trials of walking at a self-selected speed and step length have been simultaneously recorded by the two systems, analyzed, and compared blindly (40 datasets). The model detects the steps and the foot which supports body weight. The stride time and the cadence have a mean absolute percentage error of 5.7% and 4.9%, respectively. The mean absolute percentage error in the measurement of step’s length and step’s speed is 5.6% and 13.5%, respectively. Results confirm that the proposed methodology is complete and effective. It is demonstrated that the developed wearable system allows for a reliable assessment of human gait spatio-temporal parameters. Therefore, the goal of this paper is threefold. The first goal is to present and define structured Protocol Design Guidelines, where the related setup is implemented for the validation of wearable IMU systems particularly dedicated to GA and gait monitoring. The second goal is to apply these Protocol Design Guidelines to a case study in order to verify their feasibility, user-friendliness, and efficacy. The third goal is the validation of our biomechanical kinematic model with the gold standard reference.

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Pevtsov, E. Ph, T. A. Demenkova, and A. A. Shnyakin. "Design for Testability of Integrated Circuits and Project Protection Difficulties." Russian Technological Journal 7, no. 4 (August 11, 2019): 60–70. http://dx.doi.org/10.32362/2500-316x-2019-7-4-60-70.

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Design solutions of domestic VLSI were obtained as a result of the application of computeraided design tools of a foreign supplier (CAD Synopsys, Cadence Design Systems and Mentor Graphics), based on standard libraries of PDK elements (Project Design KIT) of factories and IC-modules also supplied mainly by foreign companies. As a rule, the developer does not have its own production facilities, using the services provided by foreign factories (fablesscompanies). Due to this fact, relevant are the studies aimed at the development of a complex of measures, excluding the possibility of unauthorized changes into IC, i.e. protection of projects against intentional hardware and technology violations made during the formation of the control information for handing it over to the production facility and/or in case of IC manufacture at the factory. This paper considers this task from the standpoint of the analysis of the methodology of design for testability (DFT), i.e., a complex of measures that provide obtaining solutions at the design stage. The solutions include the verification of the correct performance of the manufactured chip by means of external tests and/or self-testing procedures. It was proposed, inter alia: 1) to analyze the libraries of standard elements used in the project with full disclosure of their specifications; 2) to create nodes with the physical non-cloning function in the projects on the basis of the libraries of standard elements in models and analysis programs; 3) to analyze IP modules used in the project with the maximum disclosure of structure, methods and algorithms for providing test coverings; 4) to provide for the development in projects of special test kits and methods of their generation at the design stage of functions in order to detect malicious nodes and programs both within SoC cores and at the level of system buses; 5) to develop at the design stage and to apply during tests a technique of special hardware measurements of parameters of the manufactured circuits and analysis of their results, inter alia, according to measurements of delays in distribution of signals and/or buses current consumption.

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Gudlavalleti, R. H., B. Saman, R. Mays, H. Salama, Evan Heller, J. Chandy, and F. Jain. "A Novel Addressing Circuit for SWS-FET Based Multivalued Dynamic Random-Access Memory Array." International Journal of High Speed Electronics and Systems 29, no. 01n04 (March 2020): 2040009. http://dx.doi.org/10.1142/s0129156420400091.

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Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels.

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Freitas, Luis Miguel Carvalho, and Fernando Morgado-Dias. "Design Improvements on Fast, High-Order, Incremental Sigma-Delta ADCs for Low-Noise Stacked CMOS Image Sensors." Electronics 10, no. 16 (August 11, 2021): 1936. http://dx.doi.org/10.3390/electronics10161936.

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Modern CMOS imaging devices are present everywhere, in the form of line, area and depth scanners. These image devices can be used in the automotive field, in industrial applications, in the consumer’s market, and in various medical and scientific areas. Particularly in industrial and scientific applications, the low-light noise performance or the high dynamic-range features are often the cases of interest, combined with low power dissipation and high frame rates. In this sense, the noise floor performance and the power consumption are the focus of this work, given that both are interlinked and play a direct role in the remaining sensor features. It is known that thermal and flicker noise sources are the main contributors to the degradation of the sensor performance, concerning the sensor output image noise. This paper presents an indirect way to reduce both the thermal and the flicker noise contributions by using thin-oxide low voltage supply column readout circuits and fast 3rd order incremental sigma-delta converters with noise shaping capabilities (to provide low noise output digital samples—74 μVrms; 0.7 e−rms; at 105 μV/e−), and thus performing correlated double sampling in a short time (19 μs), while dissipating significant low power (346 μW). Throughout the extensive parametric transistor-level simulations, the readout path produced 1.2% non-linearity, with a competitive saturation capacity (6.5 ke−) pixel. In addition, this paper addresses the readout parallelism as the main point of interest, decoupling resolution from the image noise and the frame rate, at virtually any array resolution. The design and simulations were performed with Virtuoso 6.17 tools (Cadence Design Systems, San Jose, CA, USA) using Spectre models from TS18IS Image Sensor 0.18 µm Process Development Kit (Tower Jazz Semiconductor, Migdal Haemek, Israel).

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Bait-Suwailam, M. M. "Electromagnetic Field Detector Circuit for Low- Frequency Energy Applications." Journal of Engineering Research [TJER] 12, no. 1 (June 1, 2015): 69. http://dx.doi.org/10.24200/tjer.vol12iss1pp69-80.

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This study details an electromagnetic (EM) field radiation detector system that was developed for near-field low-frequency energy applications. The prototype constitutes the use of a dual-band monopole antenna system as a probe along with a detecting circuit. Furthermore, the prototype was equipped with a qualitative EM radiation strength display unit at its output stage. For proof of concept, the detecting probe was implemented on a printed-circuit board. Both numerical simulations were based on PSpice software (Cadence Design Systems, Inc., San Jose, California, USA) and measurements are presented and discussed. The EM field detector aimed to sense any potential sources of EM radiation from mobile phone units as well as WiFi access points, simultaneously, which is accomplished with the use of the dual-band antenna system. Such a sensitive detector has useful application as a stand-alone monitoring probe for troubleshooting as well as to identify sources of EM radiation interference threats for industrial high-speed electronic devices. Additionally, such a sensor is a potentially useful tool for site testing and scanning for optimal locations of base station masks for telecommunication service providers. Other prototypes are also presented to illustrate the usefulness of such detectors in some of the aforementioned applications.

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SINGH, RAGHVENDRA, and SHYAM AKASHE. "MODELING AND ANALYSIS OF LOW POWER 10 T FULL ADDER WITH REDUCED GROUND BOUNCE NOISE." Journal of Circuits, Systems and Computers 23, no. 01 (January 2014): 1450005. http://dx.doi.org/10.1142/s0218126614500054.

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In the design of high performance complex arithmetic logic circuits, ground bounce noise, leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, the low power and reduced ground bounce noise using 10 transistor full adder has been proposed. Full adder is the most important basic building of digital circuits employing arithmetic operation. Adder circuit is widely used in many digital circuits not only for arithmetic operation but also for address generation in processors and microcontrollers. It is therefore necessary to make these systems more efficient so that they consume less power. Here, we use stacking power gating technique to evaluate leakage current, power and ground bounce noise. This paper describes reduction of leakage power and ground bounce noise from the 10 T full adder circuits to make it more reliable to be used to have low power and stable and errorless output. All the simulation in this paper has been carried out using cadence virtuoso at 45 nm technology at various voltages and various temperatures. By using this technique the leakage current reduction can be improved by 80% and leakage power to 70% as compared to conventional 10 T full adder. Ground bounce noise can be reduced to 60% as compared to the base full adder.

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Найденов and E. Naydenov. "Development micromachined cyber platforms to cultive endothelial сapillary networks in vitro in the space organized microflows nutrient medium." Journal of New Medical Technologies. eJournal 9, no. 2 (July 6, 2015): 0. http://dx.doi.org/10.12737/10746.

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This work is devoted to the development of technology and special equipment for the cultivation of spontaneously developing functioning endothelial capillary networks in vitro as the basis of artificial cloth-like structures with desired biological properties. It is the scientific and engineering projects RFBR №94-04-13544 «Structural analysis of microvascular bifurcations" and №96-04-50991 «Cell and Tissue Engineering endothelium (formation in endothelial culture in vitro the functioning self-developing capillary networks)." The proposed technology allows the author to form three-dimensional capillary endothelial network around micro-fluidic arrays, immersed in a specially designed dynamic gel. In 2013, the Korean research team under the lea-dership Noo Li Jeon has reproduced, using a similar approach, the phenomenon of self-developing functioning endothelial capillary networks with mass transfer in vitro. It has fully confirmed the validity of the concept pro-posed in the listed projects. Using system of the mathematical modeling Matlab & Simulink and system engi-neering design Cadence Orcad it was developed simulation mathematical model and circuit diagrams experimental reactor modules, it allows to saving considerable financial resources allocated to research and de-velopment of this kind. The resulting model contains 5.4 million basic Simulink blocks and performs more than 7,000 different mathematical functions, reflecting the behavior of devices in stationary and non-stationary conditions. Device control is based on neural network technology. Portable stand-alone microcomputers cyber platform includes microfluidic matrix, generators of microflows liquid phase nutrient medium, life-support systems of endothelial culture system of automatic digital imaging process of angiogenesis, the transmission system of encrypted data over a secure radio, digital control systems. All systems are backed up multiple times, allowing the product to operate in stand-alone mode for a long time (up to a year or more).

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Zaman, Qummar, Senan Alraho, and Andreas König. "Efficient transient testing procedure using a novel experience replay particle swarm optimizer for THD-based robust design and optimization of self-X sensory electronics in industry 4.0." Journal of Sensors and Sensor Systems 10, no. 2 (August 10, 2021): 193–206. http://dx.doi.org/10.5194/jsss-10-193-2021.

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Abstract. This paper aims to improve the traditional calibration method for reconfigurable self-X (self-calibration, self-healing, self-optimize, etc.) sensor interface readout circuit for industry 4.0. A cost-effective test stimulus is applied to the device under test, and the transient response of the system is analyzed to correlate the circuit's characteristics parameters. Due to complexity in the search and objective space of the smart sensory electronics, a novel experience replay particle swarm optimization (ERPSO) algorithm is being proposed and proved a better-searching capability than some currently well-known PSO algorithms. The newly proposed ERPSO expanded the selection producer of the classical PSO by introducing an experience replay buffer (ERB) intending to reduce the probability of trapping into the local minima. The ERB reflects the archive of previously visited global best particles, while its selection is based upon an adaptive epsilon greedy method in the velocity updating model. The performance of the proposed ERPSO algorithm is verified by using eight different popular benchmarking functions. Furthermore, an extrinsic evaluation of the ERPSO algorithm is also examined on a reconfigurable wide swing indirect current-feedback instrumentation amplifier (CFIA). For the later test, we proposed an efficient optimization procedure by using total harmonic distortion analyses of CFIA output to reduce the total number of measurements and save considerable optimization time and cost. The proposed optimization methodology is roughly 3 times faster than the classical optimization process. The circuit is implemented by using Cadence design tools and CMOS 0.35 µm technology from Austria Microsystems (AMS). The efficiency and robustness are the key features of the proposed methodology toward implementing reliable sensory electronic systems for industry 4.0 applications.

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Scataglini, Sofia, Stijn Verwulgen, Eddy Roosens, Robby Haelterman, and Damien Van Tiggelen. "Measuring Spatiotemporal Parameters on Treadmill Walking Using Wearable Inertial System." Sensors 21, no. 13 (June 29, 2021): 4441. http://dx.doi.org/10.3390/s21134441.

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This study aims to measure and compare spatiotemporal gait parameters in nineteen subjects using a full wearable inertial mocap system Xsens (MVN Awinda, Netherlands) and a photoelectronic system one-meter OptoGaitTM (Microgait, Italy) on a treadmill imposing a walking speed of 5 km/h. A total of eleven steps were considered for each subject constituting a dataset of 209 samples from which spatiotemporal parameters (SPT) were calculated. The step length measurement was determined using two methods. The first one considers the calculation of step length based on the inverted pendulum model, while the second considers an anthropometric approach that correlates the stature with an anthropometric coefficient. Although the absolute agreement and consistency were found for the calculation of the stance phase, cadence and gait cycle, from our study, differences in SPT were found between the two systems. Mean square error (MSE) calculation of their speed (m/s) with respect to the imposed speed on a treadmill reveals a smaller error (MSE = 0.0008) using the OptoGaitTM. Overall, our results indicate that the accurate detection of heel strike and toe-off have an influence on phases and sub-phases for the entire acquisition. Future study in this domain should investigate how to design and integrate better products and algorithms aiming to solve the problematic issues already identified in this study without limiting the user’s need and performance in a different environment.

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John, Vimukth, Shylu Sam, S. Radha, P. Sam Paul, and Joel Samuel. "Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process." Circuit World 46, no. 4 (March 23, 2020): 257–69. http://dx.doi.org/10.1108/cw-12-2018-0104.

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Purpose The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V. Design/methodology/approach In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates. Findings The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. Originality/value In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.

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Jaikla, Winai, Sirigul Bunrueangsak, Fabian Khateb, Tomasz Kulej, Peerawut Suwanjan, and Piya Supavarasuwat. "Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs." Electronics 10, no. 6 (March 15, 2021): 684. http://dx.doi.org/10.3390/electronics10060684.

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This paper presents inductance simulators using the voltage differencing differential input buffered amplifier (VD-DIBA) as an active building block. Three types of inductance simulators, including floating lossless inductance, series inductance-resistance, and parallel inductance-resistance simulators, are proposed, in addition to their application to the 4th order elliptic lowpass ladder filter. The simple design procedures of these inductance simulators using a circuit block diagram are also given. The proposed inductance simulators employ two VD-DIBAs and two passive elements. The complementary metal oxide semiconductor (CMOS) VD-DIBA used in this design utilizes the multiple-input metal oxide semiconductor (MOS) transistor technique in order to achieve a compact and simple structure with a minimum count of transistors. Thanks to this technique, the VD-DIBA offers high performances compared to the other CMOS structures presented in the literature. The CMOS VD-DIBAs and their applications are designed and simulated in the Cadence environment using a 0.18 µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). Using a supply voltage of ±0.9 V, the linear operation of VD-DIBA is obtained over a differential input range of −0.5 V to 0.5 V. The lowpass (LP) ladder filter realized with the proposed inductance simulators shows a dynamic range (DR) of 80 dB for a total harmonic distortion (THD) of 2% at 1 kHz and a 1.8 V peak-to-peak output. In addition, the experimental results of the floating inductance simulators and their applications are obtained by using VD-DIBA constructed from the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental ones, confirming the advantages of the inductance simulators and their application.

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Hnin, Htet Htet, Sunee Bovonsunthonchai, Theerapol Witthiwej, Roongtiwa Vachalathiti, and Rattapha Ariyaudomkit. "Feasibility of action observation effect on gait and mobility in idiopathic normal pressure hydrocephalus patients." Dementia & Neuropsychologia 15, no. 1 (March 2021): 79–87. http://dx.doi.org/10.1590/1980-57642021dn15-010008.

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ABSTRACT. Action observation (AO) has been proved to be of benefit in several neurological conditions, but no study has previously been conducted in idiopathic normal pressure hydrocephalus (iNPH). Objective: This study aimed to investigate the feasibility of AO in iNPH patients. Methods: A single-group pretest-posttest design was conducted in twenty-seven iNPH patients. Gait and mobility parameters were assessed using the 2D gait measurement in the timed up and go (TUG) test for two trials before and after immediate AO training. The outcomes included step length and time, stride length and time, cadence, gait speed, sit-to-stand time, 3-m walking time, turning time and step, and TUG. In addition, early step length and time were measured. AO consisted of 7.5 min of watching gait videos demonstrated by a healthy older person. Parameters were measured twice for the baseline to determine reproducibility using the intraclass correlation coefficient (ICC3,1). Data between before and after immediately applying AO were compared using the paired t-test. Results: All outcomes showed moderate to excellent test-retest reliability (ICC3,1=0.51 0.99, p<0.05), except for the step time (ICC3,1=0.19, p=0.302), which showed poor reliability. There were significant improvements (p<0.05) in step time, early step time, gait speed, sit-to-stand time, and turning time after applying AO. Yet, the rest of the outcomes showed no significant change. Conclusions: A single session of AO is feasible to provide benefits for gait and mobility parameters. Therapists may modify this method in the training program to improve gait and mobility performances for iNPH patients.

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Templeman, James N., Patricia S. Denbrook, and Linda E. Sibert. "Virtual Locomotion: Walking in Place through Virtual Environments." Presence: Teleoperators and Virtual Environments 8, no. 6 (December 1999): 598–617. http://dx.doi.org/10.1162/105474699566512.

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This paper presents both an analysis of requirements for user control over simulated locomotion and a new control technique designed to meet these requirements. The goal is to allow the user to move through virtual environments in as similar a manner as possible to walking through the real world. We approach this problem by examining the interrelationships between motion control and the other actions people use to act, sense, and react to their environment. If the interactions between control actions and sensory feedback can be made comparable to those of actions in the real world, then there is hope for constructing an effective new technique. Candidate solutions are reviewed once the analysis is developed. This analysis leads to a promising new design for a sensor-based virtual locomotion called Gaiter. The new control allows users to direct their movement through virtual environments by stepping in place. The movement of a person's legs is sensed, and in-place walking is treated as a gesture indicating the user intends to take a virtual step. More specifically, the movement of the user's legs determines the direction, extent, and timing of their movement through virtual environments. Tying virtual locomotion to leg motion allows a person to step in any direction and control the stride length and cadence of his virtual steps. The user can walk straight, turn in place, and turn while advancing. Motion is expressed in a body-centric coordinate system similar to that of actual stepping. The system can discriminate between gestural and actual steps, so both types of steps can be intermixed.

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Huang, Fu Xiang, Zhi Qiang Gao, and Xiao Wei Liu. "Design of 16 bit 200kHz Feedforward Sigma-Delta ADC Applied in Silicon Gyroscope." Key Engineering Materials 645-646 (May 2015): 548–54. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.548.

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Due to the huge potential applications in military and civil fields, silicon micro mechanical gyro has become the most popular research direction in MEMS field today. Therefore, the corresponding interface circuit of silicon gyroscope has also become a hot topic at home and abroad. Now, integration, digitalization and intelligence has become the focus of future research directions of silicon gyroscope, so the research of analog to digital conversion circuit for gyroscope has become a research priority. Therefore, the conduct of Sigma Delta ADCs research for silicon gyro interface circuit has a very important significance and application prospects.This topic briefly introduces the working principle of Sigma Delta ADC. Based on the requirements of the modulator design, Sigma Delta modulator structures are carefully analyzed and also carried on the comparison and optimization. Hereby, a three order three bits quantization in single-loop with partial feedback of feed-forward summation system structure for modulator is designed in this paper, and then the ideal model of modulator system in Matlab is simulated. In addition, the focus of this topic is mainly on the nonlinear factors analysis and modeling, and the Data Weighted Average (DWA) technique used in multi-bit quantization is introduced as well as modeling in system level. Then, the non-ideal modeling of system is simulated in Matlab.In system level design, this paper adopts feed-forward summation and multi-bit quantization structure to reduce the output of the integrator, increase the noise performance of the modulator, and make it easier for the system stability. Furthermore, the use of partial feedback in the structure for zero-point optimization improves the noise shaping ability in signal bandwidth of modulator. This topic employs the single-loop third-order three-bit quantization structure, with the sampling rate 64, signal bandwidth 200 K Hz and the sampling clock frequency 25.6 MHz. For the ideal modeling, the Signal-to-Noise Ratio (SNR) is 125dB, and the Effective Number of Bits (ENOB) is 20.48. When in consideration of modulator’s nonlinear factors, the nonlinear systems Simulink simulation results obtained SNR of 104dB, and the ENOB is 16.98.In order to reduce the harmonic distortion of the modulator, transistor level is implemented by fully-differential switch capacitor circuit. The structure at all levels of the integrator was optimized. To reduce the influence of flicker noise, the integrator adopts Correlated Double Sampling (CDS) technology, and is improved by the partial feedback circuit. The fully-differential operational amplifier with high slew-rate and high bandwidth is designed, and uses switch capacitor circuit as common-mode feedback. Dynamic comparator and multi-bit quantizer are designed to improve the speed of the quantizer and reduce power consumption. The design the nonlinear compensation feedback DAC module--DWA module circuit--realizes noise shaping of capacitance matching error. The overall circuit was simulated in Cadence by 0.6um process. Transistor-level simulation result shows that the SNR is 101.3dB, and the effective number of bits is 16.54bits. The simulation results are consistent with the established non-ideal model of modulator, which verifies the correction of system level design method.

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Carry, B. "Solar system science with ESA Euclid." Astronomy & Astrophysics 609 (January 2018): A113. http://dx.doi.org/10.1051/0004-6361/201730386.

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Context. The ESA Euclid mission has been designed to map the geometry of the dark Universe. Scheduled for launch in 2020, it will conduct a six-year visible and near-infrared imaging and spectroscopic survey over 15 000 deg2 down to VAB ~ 24.5. Although the survey will avoid ecliptic latitudes below 15°, the survey pattern in repeated sequences of four broadband filters seems well-adapted to detect and characterize solar system objects (SSOs). Aims. We aim at evaluating the capability of Euclid of discovering SSOs and of measuring their position, apparent magnitude, and spectral energy distribution. We also investigate how the SSO orbits, morphology (activity and multiplicity), physical properties (rotation period, spin orientation, and 3D shape), and surface composition can be determined based on these measurements. Methods. We used the current census of SSOs to extrapolate the total amount of SSOs that will be detectable by Euclid, that is, objects within the survey area and brighter than the limiting magnitude. For each different population of SSO, from neighboring near-Earth asteroids to distant Kuiper-belt objects (KBOs) and including comets, we compared the expected Euclid astrometry, photometry, and spectroscopy with the SSO properties to estimate how Euclid will constrain the SSOs dynamical, physical, and compositional properties. Results. With the current survey design, about 150 000 SSOs, mainly from the asteroid main-belt, should be observable by Euclid. These objects will all have high inclination, which is a difference to many SSO surveys that focus on the ecliptic plane. Euclid may be able to discover several 104 SSOs, in particular, distant KBOs at high declination. The Euclid observations will consist of a suite of four sequences of four measurements and will refine the spectral classification of SSOs by extending the spectral coverage provided by Gaia and the LSST, for instance, to 2 microns. Combined with sparse photometry such as measured by Gaia and the LSST, the time-resolved photometry will contribute to determining the SSO rotation period, spin orientation, and 3D shape model. The sharp and stable point-spread function of Euclid will also allow us to resolve binary systems in the Kuiper belt and detect activity around Centaurs. Conclusions. The depth of the Euclid survey (VAB ~ 24.5), its spectral coverage (0.5 to 2.0 μm), and its observation cadence has great potential for solar system research. A dedicated processing for SSOs is being set up within the Euclid consortium to produce astrometry catalogs, multicolor and time-resolved photometry, and spectral classification of some 105 SSOs, which will be delivered as Legacy Science.

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Bertsias, Panagiotis, Costas Psychalinos, Ahmed S. Elwakil, and Brent Maundy. "Minimum MOS Transistor Count Fractional-Order Voltage-Mode and Current-Mode Filters." Technologies 7, no. 4 (December 6, 2019): 85. http://dx.doi.org/10.3390/technologies7040085.

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Voltage-mode and current-mode fractional-order filter topologies, which are capable of realizing various types of transfer functions, are introduced in this paper. Thanks to the employment of the transconductance parameter of the MOS transistors, the derived filter structures offer the benefit of the electronic adjustment of their frequency characteristics. With regards to the literature, the number of MOS transisitors is minimized leading to significant reduction of the circuit complexity and power dissipation. Simulation results, derived using the Design Kit of the 0.35 μm Austria Mikro Systeme CMOS process and the Cadence IC design suite, confirm the correct operation of the presented filter structures.

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Kaskouta, Elpida, Stavroula Kapoulea, Costas Psychalinos, and Ahmed S. Elwakil. "Implementation of a Fractional-Order Electronically Reconfigurable Lung Impedance Emulator of the Human Respiratory Tree." Journal of Low Power Electronics and Applications 10, no. 2 (May 16, 2020): 18. http://dx.doi.org/10.3390/jlpea10020018.

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The fractional-order lung impedance model of the human respiratory tree is implemented in this paper, using Operational Transconductance Amplifiers. The employment of such active element offers electronic adjustment of the impedance characteristics in terms of both elements values and orders. As the MOS transistors in OTAs are biased in the weak inversion region, the power dissipation and the dc bias voltage of operation are also minimized. In addition, the partial fraction expansion tool has been utilized, in order to achieve reduction of the spread of the required time-constants and scaling factors. The performance of the proposed scheme has been evaluated, at post-layout level, using MOS transistors models provided by the 0.35 μ m Austria Mikro Systeme technology CMOS process, and the Cadence IC design suite.

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Irby, Steven E., Kathie A. Bernhardt, and Kenton R. Kaufman. "Gait of stance control orthosis users: The Dynamic Knee Brace System." Prosthetics and Orthotics International 29, no. 3 (December 2005): 269–82. http://dx.doi.org/10.1080/03093640500238915.

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Individuals with weak or absent quadriceps who wish to walk independently are prescribed knee-ankle-foot orthoses (KAFOs). New stance control orthosis (SCO) designs automatically release the knee to allow swing phase flexion and extension while still locking the joint during stance. Twenty-one participants were fitted unilaterally with the Dynamic Knee Brace System (DKBS), a non-commercial SCO. Thirteen subjects were experienced KAFO users (average 28 ± 18 years of experience) while eight were novice users. Novice users demonstrated increased velocity (55 vs. 71cm/sec, p = 0.048) and cadence (77 vs. 85 steps/min, p < 0.05) when using the DKBS over the traditional locked KAFO. Experienced KAFO users tended to have reduced velocity and cadence measures when using the SCO ( p < 0.10). Knee range of motion was significantly greater for the novice group than for the experienced group (55.2 ± 4.8 vs. 42.6 ± 3.8°, p = 0.05). Peak knee extension moments tended to be greater for the experienced group (0.29 ± 0.21 vs. 0.087 ± 0.047 Nm/kg, p = 0.09). This report describes gait changes during the introductory phase of DKBS adoption. Experienced KAFO users undoubtedly had ingrained gait patterns designed to compensate for walking with a standard locked KAFO. These patterns may have limited the ability of those users from taking full and immediate advantage of the SCO capabilities. Also, alternate SCO systems may engender different results. Comparison studies and longer term field studies are needed to clarify benefits of the various bracing options.

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Fei, B., A. H. Darrat, and W. Mathis. "Charakterisierung von CMOS RF Blöcken mittels Volterra-Reihen zur Optimierung des Designprozesses." Advances in Radio Science 7 (May 18, 2009): 155–61. http://dx.doi.org/10.5194/ars-7-155-2009.

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Abstract. Im Rahmen dieser Arbeit werden die Volterra-Reihen zur Analyse der Nichtlinearität in RF Schaltungen verwendet, um den Designprozess für RF Systeme zu optimieren. Die auf Volterra-Reihen basierende Nichtlinearitätsanalyse wurde in eine Matlab-Toolbox implementiert. Diese Toolbox kann mittels Volterra-Reihen die symbolische Berechnung der Nichtlinearitätsparameter (harmonische Verzerrungen und Intermodulationsverzerrungen) eines RF Blocks für eine gegebene Architektur und Technologie durchführen. Danach können die symbolische Ausdrücke der Nichtlinearitätsparameter in Abhängigkeit von den Architekturparametern und Technologieparametern erhalten werden. Dies ermöglicht die Beschränkung der Wertebereiche der Architekturparameter und die Überprüfung auf die Erfüllung der Nichtlinearitätsspezifikationen für unterschiedliche Kombinationen von Architekturen und Technologien. Somit ist eine Beschränkung der Klassen der Architekturen und Technologien möglich. Die Toolbox wurde zur Verdeutlichung auf einen Low Noise Amplifier (LNA) der Inductive Source Degeneration (ISD) Architektur angewandt. Zur Verifikation wurde diese LNA-Schaltung auch in Cadence SpectreRF Design Tool simuliert.

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LI, FANYANG, TAO YIN, and XIAOYU WANG. "A 1 V INTEGRATION AND ACCURACY AND POWER IMPROVED HEARING AID SYSTEM WITH THE TRIPLE OSCILLATION-BASED LOOPS TECHNIQUE." Journal of Circuits, Systems and Computers 23, no. 04 (April 2014): 1450056. http://dx.doi.org/10.1142/s021812661450056x.

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We present the integration and accuracy and power improved hearing aid system that proposes the triple oscillation-based loops (TOL) technique. Compared with the conventional techniques, the technique replaces the interface capacitors, A/D and D/A convertors with the oscillation-based closed loop and the calibration/operation feedback paths, which are able to enhance the integration of the system and improve the system's accuracy and power performance. Specifically, the technique achieves the only once of the second-order delta-sigma modulation with an integrator and an oscillator. To realize the architecture, the current mode blocks with calibration and successive subtraction are presented on the circuit design. Simulated with a 0.13 μm standard CMOS process in Cadence, with the 16 ohm loudspeaker impedance under the 1 V supply voltage, the input referred DC offset voltage with interface capacitor free is achieved below 2.5 mV; and the signal-to-noise and distortion rate (SNDR) achieves 50 dB@400 mVp-p output voltage. Moreover, the power consumption with no load is maintained within 350 μW.

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Huang, Yuxuan, Jian Zhao, Wenyu Sun, Huazhong Yang, and Yongpan Liu. "Investigation and Modeling of Multi-Node Body Channel Wireless Power Transfer." Sensors 20, no. 1 (December 25, 2019): 156. http://dx.doi.org/10.3390/s20010156.

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Insufficient power supply is a huge challenge for wireless body area network (WBAN). Body channel wireless power transfer (BC-WPT) is promising to realize multi-node high-efficiency power transmission for miniaturized WBAN nodes. However, the behavior of BC-WPT, especially in the multi-node scenario, is still lacking in research. In this paper, the inter-degeneration mechanism of a multi-node BC-WPT is investigated based on the intuitive analysis of the existing circuit model. Co-simulation in the Computer Simulation Technology (CST) and Cadence platform and experiments in a general indoor environment verify this mechanism. Three key factors, including the distance between the source and the harvester, frequency of the source, and area of the ground electrodes, are taken into consideration, resulting in 15 representative cases for simulation and experiments studies. Based on the simulation parameters, an empirical circuit model to accurately predict the received power of multiple harvesters is established, which fits well with the measurement results, and can further provide guidelines for designs and research on multi-node BC-WPT systems.

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Rincón Ballesteros, Dora Lucia, Johan Esteban Fonseca Ramírez, and Javier Arturo Orjuela-Castro. "Hacia un Marco Conceptual Común sobre Trazabilidad en la Cadena de Suministro de Alimentos." Ingeniería 22, no. 2 (May 5, 2017): 161. http://dx.doi.org/10.14483/udistrital.jour.reving.2017.2.a01.

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AbstractBackground: The absence of a common conceptual framework on traceability in the food supply chain (SCF), prevents a cohesive development of this concept. The absence has generated confusion and has made it impossible to demonstrate the social and commercial advantages of its implementation. In addition, not having a common framework in countries such as Colombia obstructs the development of public policies.Method: A systematic review of the literature was carried out in four stages: search protocol to consult articles in the databases Scopus, Science Direct and ISI Web; review and selection of relevant articles; extraction and incorporation of data into tables and formats designed for this purpose and elaboration of the conceptual framework.Results: A common conceptual framework is proposed for the design and implementation of a traceability system in the SCF covering the following aspects: definition of traceability, characteristics and properties, schemes, traceable resource unit, motivators and recording systems. The international and national legislation is evaluated and aspects for its incorporation are established. The proposed conceptual framework is exemplified by the meat supply chain to guide the implementation of traceability systems in CSA in Colombia. Conclusions: The conceptual framework for SCF traceability can be a guide for the implementation and development of food chains in the Colombian context. Implementing this in agricultural chains would allow the differentiation of origin, which can be a competitive factor for producers with good agricultural practices, as well as provide effective logistic capacities for all agents of the SCF. The effect of its implementation should be evaluated with special emphasis on the impact on brand positioning and the establishment of fair prices as an effect of tracking and tracing the traceability system.Language: Spanish.

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Weber, H., C. Widemann, and W. Mathis. "A first approach to the distortion analysis of nonlinear analog circuits utilizing X-parameters." Advances in Radio Science 11 (July 4, 2013): 159–63. http://dx.doi.org/10.5194/ars-11-159-2013.

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Abstract. In this contribution a first approach to the distortion analysis of nonlinear 2-port-networks with X-parameters1 is presented. The X-parameters introduced by Verspecht and Root (2006) offer the possibility to describe nonlinear microwave 2-port-networks under large signal conditions. On the basis of X-parameter measurements with a nonlinear network analyzer (NVNA) behavioral models can be extracted for the networks. These models can be used to consider the nonlinear behavior during the design process of microwave circuits. The idea of the present work is to extract the behavioral models in order to describe the influence of interfering signals on the output behavior of the nonlinear circuits. Hereby, a simulator is used instead of a NVNA to extract the X-parameters. Assuming that the interfering signals are relatively small compared to the nominal input signal, the output signal can be described as a superposition of the effects of each input signal. In order to determine the functional correlation between the scattering variables, a polynomial dependency is assumed. The required datasets for the approximation of the describing functions are simulated by a directional coupler model in Cadence Design Framework. The polynomial coefficients are obtained by a least-square method. The resulting describing functions can be used to predict the system's behavior under certain conditions as well as the effects of the interfering signal on the output signal. 1 X-parameter is a registered trademark of Agilent Technologies, Inc.

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Benvenuti, Lorenzo, Alessandro Catania, Giuseppe Manfredini, Andrea Ria, Massimo Piotto, and Paolo Bruschi. "Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs." Electronics 10, no. 10 (May 13, 2021): 1156. http://dx.doi.org/10.3390/electronics10101156.

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The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

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Sturnick, Daniel, Guilherme Saito, Scott Ellis, and Constantine Demetracopoulos. "Ankle and Hindfoot Kinematics of a Next Generation Total Ankle Replacement During Simulated Gait." Foot & Ankle Orthopaedics 3, no. 3 (July 1, 2018): 2473011418S0011. http://dx.doi.org/10.1177/2473011418s00119.

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Category: Ankle Arthritis Introduction/Purpose: Total ankle arthroplasty (TAA) has developed as a viable treatment option for end-stage ankle arthritis. The primary benefit proposed with TAA is that allows for maintained motion of the ankle and hindfoot joint compared to the alternative option of an ankle arthrodesis. Consequently, recent TAA systems have focused on designs that advance kinematic function. Cadaveric gait simulation is a valuable tool for investigating the direct effects of surgical procedures and devices on foot and ankle biomechanics. The objective of this study was to assess whether a next generation TAA system permits normal ankle and hindfoot kinematics using cadaveric gait simulation. Methods: Ten mid-tibia cadaveric specimens were secured to a static mounting fixture relative a six-degree of freedom robotic platform to simulate gait in native-intact and TAA conditions. A force plate was moved relative to the stationary specimen through an inverse tibial kinematic path calculated from in vivo data while extrinsic tendons were actuated using physiologic loads (Figure 1A). Ankle and hindfoot kinematics were measured from reflective markers attached to bones via surgical pins. TAA was performed using a next generation, fixed bearing total ankle system by a fellowship trained foot and ankle surgeon using manufacturer described protocol (Cadence Total Ankle, Integra LifeSciences). Ankle and hindfoot joint kinematics were directly measured using the same kinematic inputs and muscle force as the intact condition. Non-parametric, bias-corrected bootstrapping was used to calculate 95% confidence intervals to compare motion between intact and total ankle replacement conditions. Results: Analyses revealed that no significant difference in average ankle or hindfoot joint kinematics were found between intact and TAA conditions (Figure 1B). This result was consistent in each the ankle, subtalar, and talonavicular joints, and in each plane of motion. Conclusion: This study found that normal kinematics were permitted on average by a next generation, fixed bearing TAA. This finding may indicate that improved functional outcomes following could be expected. However, increased variability and some characteristic differences in the paths of motion throughout stance were observed qualitatively. This report represents an initial analysis of preliminary data, future work will include further analyses and investigation on the influence of factors such as component position and alignment on outcomes. That said, the findings of this study are encouraging and may represent improved kinematic performance in new TAA designs.

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Llorente Monleón, Sandra. "Design and development of a new modular bathroom system = Diseño y desarrollo de un novedoso sistema de baños modulares." Building & Management 1, no. 1 (April 30, 2017): 18. http://dx.doi.org/10.20868/bma.2017.1.3521.

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The techniques of production and in particular of construction tend to be technified, improving its precision, optimizing costs and times of production. This is the strategy to follows for those companies who need to increase its competitiveness. This is the way how modular or prefabrication systems have been introduced in the new construction processes. The modular construction no longer only applies to the structure of a building, but has also specialized in other parts, such as wet rooms; bathrooms and kitchens. Being those stays of the house more reproducible. Modular bathrooms are more common in buildings where houses have the same dimensions and /or distributions, and where therefore their construction is repetitive. The basis of this work is the development of a series production system of modular bathrooms that can be customized, maintaining the specifications and the lines indicated in the project. Also the development of a lifting and assembly tool that allows to minimize the transfer of the modules and facilitate the speed of its installation in its definitive location. The result is an industrialized bath module of high quality, with traceability of the materials and components used, tested and guaranteed, in a assembly line of fast manufacture. The bathroom is delivered completely finished and installed, minimizing the construction deadlines and improving its quality and safety.ResumenLas técnicas de producción y en particular de construcción tienden a tecnificarse, mejorando su precisión, optimizando costes y tiempos de producción. La construcción modular ya no solo se aplica a la estructura de una edificación, sino que también se ha especializado en otras estancias de la casa menos personales y con una composición de elementos más reproducible y por tanto industrializable. Los baños modulares cada vez son más comunes en aquellas edificaciones donde las viviendas tienen las mismas dimensiones y/o distribuciones, y donde por tanto su construcción es repetitiva. La base de este trabajo es el desarrollo de un sistema de fabricación en serie de baños modulares que puedan ser personalizables, manteniendo las especificaciones y prestaciones indicadas en el proyecto. La necesidad de poder introducir sistemas de baja temperatura, como suelos radiantes, para completar las estrategias energéticas del conjunto edificatorio, así como el desarrollo para la introducción en los módulos de una red de saneamiento que incluya cierres hidráulicos de conjunto (bote sifónico) se ve desarrollada de manera que el producto final pueda proporcionar los estándares solicitados por el cliente. Igualmente el desarrollo de un útil de elevación y montaje que permita minimizar el trasiego de los módulos y facilitar la rapidez de su instalación en su ubicación definitiva. El resultado es un módulo de baño industrializado de alta calidad, con trazabilidad de los materiales y componentes utilizados, probado y garantizado, en una cadena de montaje de rápida fabricación y que incluye todas las prescripciones técnicas del proyectista. El baño se entrega totalmente terminado e instalado, minimizando los plazos de obra y mejorando su calidad y seguridad...

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Della Bruna Jr, Emílio, Leonardo Ensslin, and Sandra Rolim Ensslin. "An MCDA-C application to evaluate supply chain performance." International Journal of Physical Distribution & Logistics Management 44, no. 7 (July 29, 2014): 597–616. http://dx.doi.org/10.1108/ijpdlm-05-2012-0157.

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Purpose – The purpose of this paper is to develop a performance evaluation model for the operations of the supply chain of an organization of the refrigeration equipment sector. The tool must aid the decision maker in the performance improvement and creation of competitive advantages. Design/methodology/approach – The study adopts a mixture of qualitative and quantitative approaches and applies them through a case study. The data collection was conducted through unstructured interviews and supplemented by documentary research. The applied intervention instrument is the Multicriteria Decision Aid – Constructivist (MCDA-C). Findings – Identification, organization, ordinal and cardinal measurement and integration of the aspects of the context judged as relevant by the decision maker. In addition, it can be highlighted the current situation diagnosis and elaboration of improvement actions related to lean philosophy and advanced planning systems. Practical implications – The developed model is being used to aid the decision maker in their decisions concerning the improvement of the supply chain operations. Originality/value – The main contributions made by the paper resides in the proposal of solutions for fulfiling gaps identified within the supply chain performance evaluation area and in the application of the MCDA-C to a practical case. Keywords Performance, Supply chain, Multicriteria, Decision, MCDA-C Paper type Case study Resumen Objetivo Objetivo – El objetivo de este artículo es desarrollar un Modelo de Desempeño para las operaciones de cadena de suministro de una organización en el sector de equipos de refrigeración. La herramienta debe ayudar a quién toma las decisiones en mejorar el desempeño y crear ventajas competitivas. Diseño/metodología/enfoque – El estudio usa una combinación de enfoques cualitativos y cuantitativos aplicándolos a un caso estudio. La recolección de datos se hizo a través de entrevistas no estructuradas y se complementó con investigación documental. El instrumento de intervención usado es el Multicriterio De Apoyo a la Decisión-Constructivista (MCDA-C). Hallazgos – Identificación, organización, mediciones ordinales y cardinales e integración de los aspectos de los contextos considerados como relevantes por el tomador de decisiones. Se puede destacar además la situación actual de diagnóstico y la elaboración de acciones de mejoramiento relacionados con la filosofía Lean y los Sistemas avanzados de planificación. Implicaciones prácticas – El modelo desarrollado esta siendo usado para ayudar al toma decisiones en las decisiones concernientes con el mejoramiento de las operaciones de la cadena de suministro. Originalidad/valor – La mayor contribución hecha por este artículo reside en proponer soluciones para cubrir brechas identificadas dentro el área de Evaluación de Rendimiento en la Cadena de Suministro y en la aplicación del MCDA-C a un caso práctico. Palabras Claves Desempeño, Cadena de Suministro, Decisión, Multicriterio, MCDA-C Tipo de papel estudio de caso Resumo Objetivo Objetivo – O objetivo de este artigo é desenvolver um Modelo de Avaliação Desempenho para as operações da cadeia de suprimentos de uma organização do setor de equipamentos de refrigeração. O modelo proposto deve ajudar o tomador de decisões a melhorar o desempenho e criar vantagens competitivas. Desenho/metodologia/enfoque – O estudo faz uso de uma abordagem qualitativa e quantitativa aplicada em um Estudo de Caso. A coleta dos dados foi feita por meio de entrevistas abertas, sendo complementada por pesquisa documental. O instrumento de intervenção usado é o Multicriteria Decision Aid – Constructivist (MCDA-C). Achados – Identificação, organização, medições ordinais e cardinais, e integração dos aspectos do contexto são considerados como relevantes para o tomador de decisões. Além disso, destacam-se o diagnóstico da situação atual e a elaboração de ações de aperfeiçoamento, nas quais se avaliam os efeitos da implementação da Filosofia Enxuta e de um Sistema de Planejamento Avançado na organização. Implicações práticas – O modelo desenvolvido auxilia o tomador de decisões nas decisões concernentes ao melhoramento das operações da cadeia de suprimentos. Originalidade/valor – As principais contribuições do artigo residem na proposição de melhorias em lacunas ainda presentes na avaliação do desempenho da cadeia de suprimentos e também na aplicação da MCDA-C em um caso prático. Palavras-Chave Desempenho, Cadeia de Suprimentos, MCDA-C, Decisão, Multicritério Tipo de papel estudo de caso

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Flores-Rodríguez, José, and Gonzalo Ramírez-Macías. "Pedagogía no lineal en balonmano. Defensa zonal de una y dos líneas en partidos reducidos (Non-linear pedagogy in handball. One and two lines zone defence in small-sided games)." Retos, no. 39 (September 7, 2020): 604–13. http://dx.doi.org/10.47197/retos.v0i39.79640.

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La pedagogía no lineal presenta diferencias importantes respecto a los modelos de enseñanza tradicionalmente empleados en balonmano. La ausencia de investigaciones sobre el proceso de enseñanza-aprendizaje en balonmano desde la pedagogía no lineal motivó el presente trabajo. El objetivo fue conocer la influencia ejercida por dos constreñimientos introducidos en una tarea: defensa zonal de una línea (LI1) y defensa zonal de dos líneas con defensor avanzado (LI2), en los comportamientos, ofensivos y defensivos, realizados por jugadores de balonmano. Estos constreñimientos, representativos de los sistemas defensivos más utilizados en balonmano, se aplicaron en la disputa de 16 partidos reducidos, durante las ocho sesiones en las que se desarrolló el estudio. Se utilizó un diseño observacional puntual/nomomético/multidimendional para registrar los comportamientos de 14 jugadores (M=14.6 años y SD=0.4) de categoría cadete masculino, que se dividieron en dos grupos para la disputa de los partidos. El análisis de coordenadas polares permitió conocer la influencia ejercida por ambos constreñimientos a nivel general, analizando los comportamientos de ambos equipos conjuntamente y, también, de manera específica para cada equipo. Así, se encontraron relaciones significativas de activación mutua entre: (1) LI1 y fijación impar, lanzamiento en penetración, lanzamiento a distancia, bloqueo, cambio de oponente, ayudas y contrabloqueo; y (2) entre LI2 y desmarques, deslizamiento e interceptación. Conocer la influencia ejercida por los constreñimientos aplicados en las tareas (comportamientos que facilitan e inhiben) es clave en la aplicación de la pedagogía no lineal, de esta manera se podrán seleccionar aquellos que ayuden a conseguir los objetivos propuestos. Abstract. Non-linear pedagogy presents important differences regarding the teaching approaches traditionally used in handball. The absence of research that addresses the teaching-learning process in handball from nonlinear pedagogy motivated the present work. The objective was to analyse the influence of certain task constraints: zonal defense of one line (LI1) and zonal defense of two lines with advanced defender (LI2), in the behaviour patterns, offensive and defensive ones, performed by handball players. These constraints, representative of the most used defensive handball systems, were applied in 16 small-sided games, during the eight sessions in which the study was developed. A nomothetic/punctual/monitoring observational design was used to register the behaviours performed by 14 players (M = 14.6 years and SD = 0.4), members of a team that competes in the male cadet category, who were divided into two groups for the matches. The analysis of polar coordinates allowed to know the influence exerted by both constraints at a general level, analyzing jointly the behaviors of both teams and, also, specifically for each team. Thus, significant relationships of mutual activation were found between: (1) LI1 and odd fixation, penetration throw, distance throw, block, opponent change, assist and counter block; and (2) between LI2 and uncheck, slip and intercept. Knowing the influence exerted by the task constraints (behaviors that facilitate and inhibit) is key in the application of non-linear pedagogy, in this way those that help to achieve the proposed objectives can be selected.

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Sánchez-Borrero, Guillermo. "EL EFECTO DEL LIBRO DE TEXTO ESCOLAR EN EL MERCADO EDITORIAL ECUATORIANO." DISEÑO ARTE Y ARQUITECTURA, no. 10 (June 10, 2021): 47–68. http://dx.doi.org/10.33324/daya.v1i10.378.

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El libro de texto escolar es una herramienta de control curricular, su relación con el aprendizaje y enseñanza que la determina el Estado ecuatoriano. El objetivo de los textos escolares es mostrar el universo científico y cultural que se quiere enseñar a los estudiantes y refleja los: valores, estereotipos e ideologías del Ecuador. A partir de 2011 se normalizó y lo controla y distribuye el Ministerio de Educación de forma gratuita en los establecimientos educativos fiscales, fiscomisionales y municipales del Ecuador. Son elaborados y producidos por las más importantes casas editoriales, además revisados y avalados por las universidades del país. Este sistema aparece con la creación de la Ley Orgánica de Educación Intercultural que ha logrado establecer políticas editoriales en el sector educativo, así como dinamizar la economía del sector editorial en toda su cadena productiva tanto intelectual como de fabricación. Es relevante el análisis de la producción editorial por la expansión de los sistemas nacionales de educación y la implementación de los modelos de enseñanza, se presenta varios puntos de vista sobre la representación del saber oficial y el acceso igualitario a la información y conocimiento. Se identifica cómo están distribuidas las casas editoras y la contribución de las universidades del país para la evaluación de contenidos, según su área de experiencia y la asignatura que abarca el texto escolar. El artículo muestra también diferentes cifras sobre la asignación y fondos destinados al proyecto que aporta a la economía de Ecuador. Palabras clave: Textos escolares, políticas editoriales, mercado editorial, impresión, diseño editorial. AbstractThe school textbook is a curricular control tool, its relationship with learning and teaching is determined by the Ecuadorian State. The objective of the textbooks is to show the scientific and cultural universe intended to be taught to students and reflects the values, stereotypes, and ideologies of Ecuador. As of 2011, it was standardized, controlled, and distributed by the Ministry of Education free of charge in public, fiscal, “fiscomisional”, and municipal educational establishments in Ecuador. They are elaborated and produced by the most important publishing houses, also reviewed, and endorsed by the country's universities. This system appears with the creation of the Organic Law of Intercultural Education, which has managed to establish editorial policies in the educational sector, as well as boost the economy of the publishing sector throughout its productive chain, both intellectual and manufacturing. The analysis of editorial production is relevant due to the expansion of national education systems and the implementation of teaching models, various points of view are presented on the representation of official knowledge and equal access to information and knowledge. It is identified how the publishing houses are distributed and the contribution of the country's universities for the evaluation of content, according to their area of experience and the subject covered by the textbook. The article also shows different figures on the allocation and funds destined for the project that contributes to the economy of Ecuador. Keywords: School texts, editorial policies, publishing market, printing, editorial design.

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Navas Bayona, Walter Iván, Halder Yandry Loor Zambrano, and Cristian Ricardo Amen Chinga. "LA CONSOLIDACIÓN DEL BLOCKCHAIN EN LAS EMPRESAS COMO MÉTODO DE PAGO PARA SUS TRANSACCIONES." Investigación & Negocios 13, no. 22 (November 4, 2020): 135. http://dx.doi.org/10.38147/invneg.v13i22.108.

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A lo largo de los últimos 20 o 30 años la evolución del cambio tecnológico, organizacional y financiero, han producido diversas transformaciones en la estructura de instituciones poderosas en el sector económico mundial. El aspecto innovador, interactivo, entre proveedores, productores, usuarios, de diferentes países con diversos marcos institucionales y diversas políticas de todo el mundo, ha implicado una transformación en los sistemas de información y las redes globales. El resultado de estos cambios ha sido el desarrollo de una producción económica a escala mundial, eliminación de barreras comerciales, flujo de capitales, tratados internacionales, producto también de otras fallas en modelos económicos que no tenían relación directa con el nuevo alcance de esta creciente era tecnológica. Las primeras cuatro décadas de internet han traído el correo electrónico, la red informática global, las empresas electrónicas, los medios sociales, la red móvil y el almacenamiento en la nube. Internet ha servido para reducir los costes de investigar, colaborar e intercambiar información. Ha permitido la aparición de nuevos medios de comunicación y entretenimiento, de nuevas formas de comerciar y de organizar el trabajo, y de empresas digitales como nunca las ha habido. El objetivo general de esta investigación es presentar un recuento del impacto del Blockchain en el sistema empresarial, el uso de criptomonedas, el bitcoin como principal moneda digital; sus características, elementos, funcionamiento, beneficios y desventajas de su aplicación en áreas diversas de la economía mundial. Mostrar en resumen la manera como se presenta ante el consumidor y la innovación de su sistema de funcionamiento a través de bloques y cadenas, que se forman a través de las transacciones realizadas. Todo esto a través de una metodología documental, mediante la revisión de trabajos e investigaciones planteadas por diversos autores especialistas en áreas como economía y finanzas, que han presentado a lo largo de sus estudios el creciente interés de usuarios, instituciones financieras y empresas de aplicar este sistema como facilitador en el desarrollo de nuevos negocios, diseño de nuevos productos y servicios. Y presentando como conclusión sus beneficios y desventajas desarrolladas y detectadas hasta el momento a través de la puesta en práctica en algunas instituciones públicas y privadas.Palabras Claves: Blockchain, criptomonedas, bitcoin, globalización. AbstractThroughout the last 20 or 30 years, the evolution of technological, organizational and financial change has produced various transformations in the structure of powerful institutions in the world economic sector. The innovative, interactive aspect, between providers, producers, users, from different countries with different institutional frameworks and diverse policies around the world, has implied a transformation in information systems and global networks. The result of these changes has been the development of economic production on a world scale, elimination of trade barriers, capital flows, international treaties, also the product of other failures in economic models that had no direct relationship with the new scope of this growing era. Technological. The first four decades of the internet have brought email, the global computer network, electronic businesses, social media, the mobile network, and cloud storage. The Internet has served to reduce the costs of researching, collaborating and exchanging information. It has allowed the emergence of new media and entertainment, new ways of trading and organizing work, and digital companies like never before. The general objective of this research is to present an account of the impact of the Blockchain on the business system, the use of cryptocurrencies, bitcoin as the main digital currency; its characteristics, elements, operation, benefits and disadvantages of its application in diverse areas of the world economy. Show in summary how it is presented to the consumer and the innovation of its operating system through blocks and chains, which are formed through the transactions carried out. All this through a documentary methodology, through the review of works and research proposed by various authors specialized in areas such as economics and finance, who have presented throughout their studies the growing interest of users, financial institutions and companies to apply this system as a facilitator in the development of new businesses, design of new products and services. And presenting as a conclusion its benefits and disadvantages developed and detected so far through implementation in some public and private institutions.Keywords: Blockchain, cryptocurrencies, bitcoin, globalization

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Abdelhedi, Fatma, and Nabil Derbel. "Volume 2, Issue 3, Special issue on Recent Advances in Engineering Systems (Published Papers) Articles Transmit / Received Beamforming for Frequency Diverse Array with Symmetrical frequency offsets Shaddrack Yaw Nusenu Adv. Sci. Technol. Eng. Syst. J. 2(3), 1-6 (2017); View Description Detailed Analysis of Amplitude and Slope Diffraction Coefficients for knife-edge structure in S-UTD-CH Model Eray Arik, Mehmet Baris Tabakcioglu Adv. Sci. Technol. Eng. Syst. J. 2(3), 7-11 (2017); View Description Applications of Case Based Organizational Memory Supported by the PAbMM Architecture Martín, María de los Ángeles, Diván, Mario José Adv. Sci. Technol. Eng. Syst. J. 2(3), 12-23 (2017); View Description Low Probability of Interception Beampattern Using Frequency Diverse Array Antenna Shaddrack Yaw Nusenu Adv. Sci. Technol. Eng. Syst. J. 2(3), 24-29 (2017); View Description Zero Trust Cloud Networks using Transport Access Control and High Availability Optical Bypass Switching Casimer DeCusatis, Piradon Liengtiraphan, Anthony Sager Adv. Sci. Technol. Eng. Syst. J. 2(3), 30-35 (2017); View Description A Derived Metrics as a Measurement to Support Efficient Requirements Analysis and Release Management Indranil Nath Adv. Sci. Technol. Eng. Syst. J. 2(3), 36-40 (2017); View Description Feedback device of temperature sensation for a myoelectric prosthetic hand Yuki Ueda, Chiharu Ishii Adv. Sci. Technol. Eng. Syst. J. 2(3), 41-40 (2017); View Description Deep venous thrombus characterization: ultrasonography, elastography and scattering operator Thibaud Berthomier, Ali Mansour, Luc Bressollette, Frédéric Le Roy, Dominique Mottier Adv. Sci. Technol. Eng. Syst. J. 2(3), 48-59 (2017); View Description Improving customs’ border control by creating a reference database of cargo inspection X-ray images Selina Kolokytha, Alexander Flisch, Thomas Lüthi, Mathieu Plamondon, Adrian Schwaninger, Wicher Vasser, Diana Hardmeier, Marius Costin, Caroline Vienne, Frank Sukowski, Ulf Hassler, Irène Dorion, Najib Gadi, Serge Maitrejean, Abraham Marciano, Andrea Canonica, Eric Rochat, Ger Koomen, Micha Slegt Adv. Sci. Technol. Eng. Syst. J. 2(3), 60-66 (2017); View Description Aviation Navigation with Use of Polarimetric Technologies Arsen Klochan, Ali Al-Ammouri, Viktor Romanenko, Vladimir Tronko Adv. Sci. Technol. Eng. Syst. J. 2(3), 67-72 (2017); View Description Optimization of Multi-standard Transmitter Architecture Using Single-Double Conversion Technique Used for Rescue Operations Riadh Essaadali, Said Aliouane, Chokri Jebali and Ammar Kouki Adv. Sci. Technol. Eng. Syst. J. 2(3), 73-81 (2017); View Description Singular Integral Equations in Electromagnetic Waves Reflection Modeling A. S. Ilinskiy, T. N. Galishnikova Adv. Sci. Technol. Eng. Syst. J. 2(3), 82-87 (2017); View Description Methodology for Management of Information Security in Industrial Control Systems: A Proof of Concept aligned with Enterprise Objectives. Fabian Bustamante, Walter Fuertes, Paul Diaz, Theofilos Toulqueridis Adv. Sci. Technol. Eng. Syst. J. 2(3), 88-99 (2017); View Description Dependence-Based Segmentation Approach for Detecting Morpheme Boundaries Ahmed Khorsi, Abeer Alsheddi Adv. Sci. Technol. Eng. Syst. J. 2(3), 100-110 (2017); View Description Paper Improving Rule Based Stemmers to Solve Some Special Cases of Arabic Language Soufiane Farrah, Hanane El Manssouri, Ziyati Elhoussaine, Mohamed Ouzzif Adv. Sci. Technol. Eng. Syst. J. 2(3), 111-115 (2017); View Description Medical imbalanced data classification Sara Belarouci, Mohammed Amine Chikh Adv. Sci. Technol. Eng. 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J. 2(3), 492-497 (2017); View Description Design, Fabrication and Testing of a Dual-Range XY Micro-Motion Stage Driven by Voice Coil Actuators Xavier Herpe, Matthew Dunnigan, Xianwen Kong Adv. Sci. Technol. Eng. Syst. J. 2(3), 498-504 (2017); View Description Self-Organizing Map based Feature Learning in Bio-Signal Processing Marwa Farouk Ibrahim Ibrahim, Adel Ali Al-Jumaily Adv. Sci. Technol. Eng. Syst. J. 2(3), 505-512 (2017); View Description A delay-dependent distributed SMC for stabilization of a networked robotic system exposed to external disturbances." Advances in Science, Technology and Engineering Systems Journal 2, no. 3 (June 2016): 513–19. http://dx.doi.org/10.25046/aj020366.

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Journal articles on the topic 'Cadence Design Systems'

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