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Journal articles on the topic 'Cadence tools'

Author: Grafiati

Published: 5 June 2025

Last updated: 2 August 2025

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1

Tyler, Neil. "SamacSys and Cadence Integrate Tools." New Electronics 51, no. 21 (2019): 9. http://dx.doi.org/10.12968/s0047-9624(23)60410-9.

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Subha Sri Lakshmi, T. "Implementation of Memory Controller using Cadence Tools." CVR Journal of Science & Technology 10, no. 1 (2016): 31–34. http://dx.doi.org/10.32377/cvrjst1007.

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Tyler, Neil. "Cadence Brings Verification IP to the Chip Level." New Electronics 53, no. 18 (2020): 9. http://dx.doi.org/10.12968/s0047-9624(22)61611-0.

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Tyler, Neil. "Cadence Brings Verification IP to the Chip Level." New Electronics 53, no. 18 (2020): 9. http://dx.doi.org/10.12968/s0047-9624(23)60377-3.

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R, Ganesh. "Design Procedure for Digital and Analog ICs using Cadence Tools." CVR Journal of Science & Technology 9, no. 1 (2015): 56–60. http://dx.doi.org/10.32377/cvrjst0911.

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Singh, Gagandeep, and Chakshu Goel. "Area Efficient Carry Select Adder (AE-CSLA) using Cadence Tools." International Journal of Engineering Trends and Technology 10, no. 10 (2014): 492–95. http://dx.doi.org/10.14445/22315381/ijett-v10p296.

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Kiran D.R, Naveen Kumar Y, Prajwal D. Nadig, et al. "Fabrication of CNTFET Simulation Using Cadence Virtuoso." international journal of engineering technology and management sciences 7, no. 3 (2023): 476–79. http://dx.doi.org/10.46647/ijetms.2023.v07i03.65.

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In this paper, the fabrication of CNTFET with the help of simulation using cadence virtuoso is presented. The process of fabricating Carbon Nanotube Field-Effect Transistors (CNTFETs) is a sophisticated task that demands great attention to detail. To aid in the design and optimization of CNTFET fabrication processes, simulation tools are often utilized. CNTFET fabrication simulations generally involve modeling the physical and chemical processes of creating the carbon nanotube channel, as well as the device's metal contacts and other components. Simulation tools such as COMSOL Multiphysics or

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Rahul, Singh, and Chandra Singh Chauhan Ram. "Power Efficient Biquadratic Filter designing using OTA." Indian Journal of Science and Technology 14, no. 29 (2021): 2448–59. https://doi.org/10.17485/IJST/v14i29.2293.

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Abstract <strong>Objectives:</strong> To present a power efficient Universal Biquad Operational Transconductance Amplifier circuit. <strong>Methods:</strong> OTA (operational transconductance amplifier) based Biquad filter is analyzed using three different simulated tools three different tools (CADENCE, XILINX, ORCAD and MATLAB tools) are used for designing the circuit. The 0.18mm CMOS technique is used using the Cadence tool for plan and reproduction. The same circuit has been implemented on ORCAD tool as well as Xilinx tool. <strong>Findings:</strong> The proposed Bi

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Bravyy, Yan, Dmitry Onishchenko, and Maxim Baltin. "A measurement method for biomechanical factors in sprint: maximal anaerobic power and optimal cadence." Russian journal of biomechanics. 28, no. 4 (2024): 129–36. https://doi.org/10.15593/rjbiomech/2024.4.13.

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A methodology for determining maximal anaerobic power and optimal pedaling cadence in sprint cyclists is presented, which is a key factor in track cycling performance. The study examines the impact of pedaling cadence on performance and emphasizes the importance of gear ratio selection for sprints. The research involved 10 professional sprint cyclists aged 15–19 years. Participants performed three maximal sprints with increasing resistance on a cycle ergometer equipped with an electronic braking system and sensors for precise measurement of left and right leg forces and pedaling cadence. This

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Wu, Chang Fu. "Analysis and Realization of Critical Points on Hardware Design of FPGA." Advanced Materials Research 950 (June 2014): 133–38. http://dx.doi.org/10.4028/www.scientific.net/amr.950.133.

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FPGA is one kind of important devices that can realize many functions. As the development of communication technology and computer science, more and more technologies are invented and more and more hardware design technologies are sifted out. Therefore, the hardware design based on ASIC can be not fit on the new theories realization. As a new device, FPGA has many advantages including strength function, shorter design circle, less money, more flexible and more intelligent design tools. More and More hardware designs of FPGA are pay more attentions. Therefore, it is significant to make analysis

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Akashe, Shyam, Sushil Bhushan, and Sanjay Sharma. "Implementation of Technology Scaling on Leakage Reduction Techniques Using Cadence Tools." Journal of Computational and Theoretical Nanoscience 9, no. 12 (2012): 2155–59. http://dx.doi.org/10.1166/jctn.2012.2631.

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Vida, Krisztián, and Rachael M. Roettenbacher. "Finding flares in Kepler data using machine-learning tools." Astronomy & Astrophysics 616 (August 2018): A163. http://dx.doi.org/10.1051/0004-6361/201833194.

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Context. Archives of long photometric surveys, such as the Kepler database, are a great basis for studying flares. However, identifying the flares is a complex task; it is easily done in the case of single-target observations by visual inspection, but is nearly impossible for several year-long time series for several thousand targets. Although automated methods for this task exist, several problems are difficult (or impossible) to overcome with traditional fitting and analysis approaches. Aims. We introduce a code for identifying and analyzing flares based on machine-learning methods, which ar

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Esther Rani, Dr T. "Design Of High Performance Configurable Radix-4 Booth Multiplier Using Cadence Tools." CVR Journal of Science & Technology 6, no. 1 (2014): 66–74. http://dx.doi.org/10.32377/cvrjst0611.

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Smith, Spencer F. C., Matthew A. Short, Martin Sénéchal, and Danielle R. Bouchard. "Validation of Practical Tools to Identify Walking Cadence to Reach Moderate Intensity." International Journal of Exercise Science 12, no. 4 (2019): 1244–53. http://dx.doi.org/10.70252/onjf5135.

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Ribeiro, Jean A. M., Simone G. Oliveira, Luciana Di Thommazo-Luporini, et al. "Energy Cost During the 6-Minute Walk Test and Its Relationship to Real-World Walking After Stroke: A Correlational, Cross-Sectional Pilot Study." Physical Therapy 99, no. 12 (2019): 1656–66. http://dx.doi.org/10.1093/ptj/pzz122.

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Abstract Background After experiencing stroke, individuals expend more energy walking than people who are healthy. However, among individuals who have experienced stroke, the correlation between the energy cost of walking, as measured by validated tests (such as the 6-minute walk test), and participation in walking, as measured by more sensitive tools (such as an ambulatory activity monitor), remains unknown. Objective The main objective of this study was to determine whether the energy cost of walking is correlated with participation in walking. Design This study was a correlational, cross-se

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Srinivasa Rao, V., Rajesh K. Panakala, and Rajesh Kumar Pullakura. "An Area Efficient and High Speed EBCOT for JPEG2000 Using Cadence EDA Tools." IOP Conference Series: Materials Science and Engineering 225 (August 2017): 012239. http://dx.doi.org/10.1088/1757-899x/225/1/012239.

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Gupta, Chirag. "16-Bit Carry Look-Ahead Adder: Design and Layout with Cadence Tools Top of Form." International Journal for Research in Applied Science and Engineering Technology 12, no. 3 (2024): 514–19. http://dx.doi.org/10.22214/ijraset.2024.58859.

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Abstract: The development of highly organised architecture is the primary goal of the current communication world in order to achieve high speed computation with low power consumption. The Carry Look Ahead Adder is highly efficient due to its ability to reduce the propagation time of carry bits, resulting in time savings. The implementation of a 16-Bit Carry Look Ahead Adder using the Cadence tool is carried out in our project. Logical equations for carry generation (G) and carry propagation (P) are used to create the carry and sum for the 1-bit adder. Then, using the Virtuoso schematic editor

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Poluektov, Aleksandr, Konstantin Zolnikov, A. Achkasov, and Yu Chevychelov. "Increasing formalization of tasks of verification of topology and electrical diagram for CAD-CAM design systems." Modeling of systems and processes 17, no. 1 (2024): 102–11. http://dx.doi.org/10.12737/2219-0767-2024-17-1-102-111.

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The article discusses the study of methods for checking the conformity of the topology and electrical circuit in electronic devices. The authors present a new approach to the analysis and verification of topological structure taking into account electrical characteristics, which leads to increased formalization of problems and provides better optimization of interaction between a person and a computer CAD system. The study includes an analysis of modern methods and tools used in the electronic device design process, and also proposes innovative approaches to ensure consistency between topology

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Shylashree, N., Yatish D. Vahvale, N. Praveena, and A. S. Mamatha. "Design and Implementation of 64-bit SRAM and CAM on Cadence and Open-source environment." International Journal of Circuits, Systems and Signal Processing 15 (July 14, 2021): 586–94. http://dx.doi.org/10.46300/9106.2021.15.65.

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Low-power IC design has become a priority in recent years because of the growing proliferation of portable battery-operated devices, bringing Static Random-Access Memory (SRAM) and Content Addressable Memory (CAM) into play. In today's SoCs, embedded SRAM units have become a necessary component. There is a lack of chips in the current world and to manufacture chips there is the requirement of Electronic Design Automation(EDA) tools that can perform better. In this paper, the main motive is to showcase the performance of open-source tools available currently which can still generate the require

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Fleishman, Gregory D., Gelu M. Nita, and Dale E. Gary. "New interactive solar flare modeling and advanced radio diagnostics tools." Proceedings of the International Astronomical Union 6, S274 (2010): 280–83. http://dx.doi.org/10.1017/s1743921311007125.

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AbstractThe coming years will see routine use of solar data of unprecedented spatial and spectral resolution, time cadence, and completeness in the wavelength domain. To capitalize on the soon to be available radio facilities such as the expanded OVSA, SSRT and FASR, and the challenges they present in the visualization and synthesis of the multi-frequency datasets, we propose that realistic, sophisticated 3D active region and flare modeling is timely now and will be a forefront of coronal studies over the coming years. Here we summarize our 3D modeling efforts, aimed at forward fitting of imag

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Islam, Riazul, and Satyendra N. Biswas. "A New Model of Dynamic Logic Circuit with NMOS based Keeper." Acta Universitatis Sapientiae, Electrical and Mechanical Engineering 12, no. 1 (2020): 1–14. http://dx.doi.org/10.2478/auseme-2020-0001.

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Abstract Dynamic logic circuits are widely popular due to a smaller number of transistors and consume less area. But the time to switch between logics is higher due to higher contention value. A new model of the logic using nMOS based keeper circuit is proposed and the performance is evaluated using Cadence tools. Comparative results demonstrate the suitability and competency of the proposed circuit.

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Wuerdig, Rodrigo, Leonardo H. Brendler, Cláudio Diniz, Ricardo Reis, and Sergio Bampi. "Comparative Implementation of PicoSoC System-on-Chip in X-Fab 180 nm CMOS Technology." Journal of Integrated Circuits and Systems 19, no. 1 (2024): 1–7. http://dx.doi.org/10.29292/jics.v19i1.769.

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This paper presents the physical implementation of the PicoSoC System-on-Chip (SoC) using commercial EDA tools, to use it as a comparison source for future advances in open-source EDA tools for digital implementation flows. The PICORV32 is a simple and versatile microcontroller core that can be used for different applications (e.g., Internet of Things). The whole process entails logical and physical synthesis, design goals aspects, and reports by tools under different working conditions. The Logical and Physical synthesis of the PicoSoC for the X-Fab 180 nm node technology, presented in this w

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Chowdhury, Md. Iqbal Bahar. "Verilog-A Implementation of SOI MOSFET-Based Amplifier and Ring Oscillator Circuits." Journal of VLSI Design and Signal Processing 9, no. 1 (2023): 26–33. https://doi.org/10.5281/zenodo.15320070.

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In this work, a single-stage CMOS amplifier circuit and a three-stage CMOS ring oscillator circuit based on silicon-oninsulator-MOSFET (SOI MOSFET) have been implemented in the Cadence environment. In doing so, Verilog-A models of the long-channel (10 µm) SOI-MOSFET (for both NMOS and PMOS) have been utilized because of the unavailability of builtin models for such MOSFETs in the Cadence tools suite. To compare the performance of SOI-MOSFET-based circuits with the bulkMOSFET ones, Verilog-A models for the bulk-MOSFETs are also utilized for a 10 µm long channel. Curve tracer circuit

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Li, Weihui, Haoyu Wen, and Peiji Duan. "Key technologies and international trends in EDA field of digital IC design: a patent analysis." SHS Web of Conferences 140 (2022): 01020. http://dx.doi.org/10.1051/shsconf/202214001020.

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Currently, Electronics Design Automation (EDA) software tools are highly monopolized internationally. In China, EDA suffers from the pain of “stuck neck”. This paper will find out the key technologies in the EDA field through 3D sand table clustering algorithm, and analyze a series of patent data of monopoly three companies (Synopsys, Cadence, Mentor Graphic), in order to help local EDA enterprises perceive the technology status and development trend of the international EDA field.

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А.В., Андрианов. "Использование семейства инструментов CMake для моделирования проектов сложных СБИС в среде Cadence Inсisive". Труды НИИСИ РАН 7, № 4 (2018): 62–67. http://dx.doi.org/10.25682/niisi.2018.4.9980.

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По мере роста сложности современных систем на кристалле (СнК) и количества используемых аппаратных блоков, перед разработчиками встает задача построения эффективной системы моделирования проектов сложных СнК, которая бы соответствовала современным методологиям разработки и тестирования. В статье рассмотрены особенности использования инструментов из пакета Cadence Incisive совместно с CMake для управления сборкой и тестированием проекта сложной СнК, способы сокращения временных затрат на стадии компиляции и элаборации проекта, при использовании методики “Multiple Snapshot Incremental Elaboratio

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Grosheva, Ekaterina, Pavel Chubunov, E. Shmakov, V. Zolnikov, and Ekaterina Skvorcova. "Testing and compilation of digital block models in the CAD software and analytical complex." Modeling of systems and processes 16, no. 3 (2023): 30–41. http://dx.doi.org/10.12737/2219-0767-2023-16-3-30-41.

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The article discusses the important stages of the process of developing a digital device of microelectronics associated with testing and compiling models of digital blocks. The work was carried out as part of the creation of a domestic CAD system designed for the design of various digital microelectronics devices. The presented works were carried out by VSFEU together with ROSELECTRONICS Holding. The authors have developed a model of a digital microprocessor based on SYNTACORE's SCR1 core, a 32-bit fully functional RISC-V architecture model with an IMC instruction set. To simulate the RTL mode

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Sridevi, A., V. Lakshmiprabha, and N. Prabhu. "Design and Analysing the Various Parameters of CMOS Circuit’s under Bi-Triggering Method Using Cadence Tools." Circuits and Systems 07, no. 09 (2016): 2622–32. http://dx.doi.org/10.4236/cs.2016.79227.

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Fernandes, Rachel B., Gijs D. Mulders, Ilaria Pascucci, et al. "pterodactyls: A Tool to Uniformly Search and Vet for Young Transiting Planets in TESS Primary Mission Photometry." Astronomical Journal 164, no. 3 (2022): 78. http://dx.doi.org/10.3847/1538-3881/ac7b29.

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Abstract Kepler’s short-period exoplanet population has revealed evolutionary features such as the Radius Valley and the Hot Neptune desert that are likely sculpted by atmospheric loss over time. These findings suggest that the primordial planet population is different from the Gyr-old Kepler population, and motivates exoplanet searches around young stars. Here, we present pterodactyls, a data reduction pipeline specifically built to address the challenges in discovering exoplanets around young stars and to work with TESS Primary Mission 30-minute cadence photometry, since most young stars wer

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Saraiva, Bruno, Ester Silva, Rodrigo Polaquini Simões, et al. "Heart rate variability and surface electromyography of trained cyclists at different cadences." Motricidade 12, no. 1 (2016): 43. http://dx.doi.org/10.6063/motricidade.4221.

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<p class="ResumoAbstract">The heart rate variability (HRV) and surface electromyography (sEMG) are important tools in the evaluation of cardiac autonomic system and neuromuscular parameters, respectively. The aim of the study was to evaluate the behavior of HRV and sEMG of the vastus lateralis in two exercise protocols on a cycle ergometer at 60 and 80 rpm. Eight healthy men cyclists who have trained for at least two years were evaluated. Reduction was observed followed by stabilization of RMSSD and SDNN indices of HRV (p&lt;0.05) along with increases in the amplitude of the sEMG sig

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Venkateswari, R., and S. Subha Rani. "Design of MICS Band Low Power Transmitter for Implantable Medical Applications." Advanced Materials Research 984-985 (July 2014): 1223–28. http://dx.doi.org/10.4028/www.scientific.net/amr.984-985.1223.

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The cyborg can control robotic arm by means of the brain implant. The design of implantable node is critical because the surgically implanted node should consume very low power. In this paper, an efficient CMOS Transmitter in terms of low power is presented for Implantable Medical Devices in the MICS band. The RF front-end transmitter consists of up-conversion mixer and a power amplifier. The designs have been done using Cadence RF Spectre tools with 180 nm technology and the transmitter front-end consumes 900μW for the MICS band.

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Kazi, Fatima Sharif, and N. Biswas Satyendra. "6 transistors and 1 memristor based memory cell." International Journal of Reconfigurable and Embedded Systems 9, no. 1 (2020): 42–51. https://doi.org/10.11591/ijres.v9.i1.pp42-51.

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Area efficient and stable memory design is one of the most important tasks in designing system on chip. This research concentrates in designing a new type of hybrid memory model by using only nMOS transistors and memristor. The proposed memory cell is very stable during successive read operates and comparatively faster and also occupies less amount of silicon area. The stability of the data during successive read operation and noise margin are in the promising range. Extensive simulation results using LTspice and Cadence software tools demonstrate the validity and competency of the proposed mo

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R.Nirmal, P.Nithila, K.Jayasudha, P.Velumani, M.Barkavi, and Dr D. F. Jingle Jabha. "DESIGN OF A 6T SRAM CELL WITH MINIMAL POWER USING CADENCE VIRTUOSO." Dogo Rangsang Research Journal 13, no. 03 (2023): 97–105. http://dx.doi.org/10.36893/drsr.2023.v13i03n03.097-105.

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It has proven challenging for VLSI designers to lower leakage power at the nanoscale level. This is because high- end gadgets, battery-operated portable pads, and other communication tools are in high demand. Memories are made up of static RAM and dynamic RAM. SRAM has had a significant impact on the worldwide VLSI market sinceit is preferred over DRAM because to its rapid read and write access times. Using a 6T static random access memory cell, this study's novel approach to lowering leakage current at various technologies has been put forth. To reduce the 6T SRAM cell leaking power, three so

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Hentschel, Johannes, Yannis Rammos, Fabian C. Moss, Markus Neuwirth, and Martin Rohrmeier. "An Annotated Corpus of Tonal Piano Music from the Long 19th Century." Empirical Musicology Review 18, no. 1 (2024): 84–95. http://dx.doi.org/10.18061/emr.v18i1.8903.

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We present a dataset of 264 annotated piano pieces of nine composers, composed in the long 19th century (https://doi.org/10.5281/zenodo.7483349). Annotations adhere to the DCML harmony annotation standard and include Roman numerals, phrase boundaries, and cadence types. The scores are encoded in the XML-based MuseScore 3 format. Annotations are embedded within the MuseScore files. In addition, all harmony information, alongside key features of the encoded measure and note objects, is provided in the form of plaintext TSV-formatted tables for increased interoperability with other datasets and a

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Alraho, Senan, Qummar Zaman, and Andreas König. "Reconfigurable Wide Input Range, Fully-Differential Indirect Current-Feedback Instrumentation Amplifier with Digital Offset Calibration for Self-X Measurement Systems." tm - Technisches Messen 87, s1 (2020): s85—s90. http://dx.doi.org/10.1515/teme-2020-0021.

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AbstractThis manuscript presents an implementation of the configurable indirect current-feedback instrumentation amplifier (CFIA) for sensor interface readout circuit. Configuration is achieved by designing digital weighted scalable arrays for some selected elements to serve as tuning knobs controlled by the evolutionary optimization algorithm. This scheme resulting in a programmable circuit for different aspects to support self-x functionality. The robustness and flexibility of the proposed circuit fit to the demands of measurement and sensory systems in industry 4.0 and other intelligent sys

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G. S., Jayadeva, Nikhil Murali, Meghana S., Raksha K. Kumar, and Nithin Anil Nair. "Design and Implementation of a High-Speed D Flip Flop using CMOS Inverter Logic." WSEAS TRANSACTIONS ON ELECTRONICS 13 (December 19, 2022): 125–29. http://dx.doi.org/10.37394/232017.2022.13.16.

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This paper proposes an improvised D- flip flop configuration based on tristate inverter logic, which reduces the power dissipation, decrease the transition time from the input to output as well as reduced time to reach rail to rail voltage. The flip flop uses transmission gate instead of pass transistor to achieve this requirement. The design is simulated using 90nm CMOS technology and data is propagated at 50% duty cycle. The circuit is simulated using Cadence tools to assess the performance with respect to delay and power. These D-flip flops have numerous applications such as buffers, regist

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Antsiferova, Valentina, Ekaterina Grosheva, Anna Ivanova, and Ivanna Abrosimova. "Computer simulation of electrophysical effects in CAD chip design." E3S Web of Conferences 389 (2023): 07015. http://dx.doi.org/10.1051/e3sconf/202338907015.

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The article discusses the characteristics and functions of modern systems for computer-aided design of submicron microcircuits. The main developers of this class of systems are Cadence Design Systems, Mentor Graphics and Synopsys. The paper analyzes in sufficient detail the composition and functionality of software tools for the development of electronic equipment provided by these companies and allowing solving functionally different tasks within the framework of the VLSI design route. The electrophysical effects of the submicron level are analyzed, which include dynamic effects associated wi

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Viraktamath, Dr S. V., Vaishnavi Peshwe, Dhanaraj Shivashimpi, Disha Majjigudda, and Navami Telsang. "Implementation Of Phase Frequency Detector And Voltage Controlled Oscillator." IOSR Journal of Electronics and Communication Engineering 20, no. 1 (2025): 01–08. https://doi.org/10.9790/2834-2001010108.

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An enhanced Phase Frequency Detector (PFD) and Voltage-Controlled Oscillator (VCO) are designed to improve performance in frequency synthesis and clock generation. The PFD achieves reduced dead zone, faster response times, and lower power consumption, ensuring greater accuracy and efficiency in phase detection. The VCO offers a wide tuning range, low phase noise, and high sensitivity, all while maintaining a low power profile, making it suitable for high-frequency applications. Designed and evaluated using Cadence EDA tools, the performance of these components is validated through simulations

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Alrashdi, A., and M. I. Khan. "Design and Comparative Analysis of High Speed and Low Power ALU Using RCA and Sklansky Adders for High-Performance Systems." Engineering, Technology & Applied Science Research 12, no. 2 (2022): 8426–30. http://dx.doi.org/10.48084/etasr.4817.

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This study examines how different initial design decisions affect the area, timing, and power of technology-mapped designs. ASIC design flow, tools used during the flow, and the factors to consider to maximize the performance and power ratio are discussed. The ALU (Arithmetic Logic Unit) is a fundamental part of all processors. In this study, two ALUs were implemented using two different types of adder circuits: a Ripple Carry Adder (RCA) and a Sklansky adder. The Cadence EDA tools were used for the implementation. A comparative analysis was conducted for the two designed ALUs in terms of area

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Krawczyk, Maciej, Małgorzata Syczewska, and Ewa Szczerbik. "Gait kinematics and clinical test changes in post-stroke patients during rehabilitation. Preliminary results of 12 patients of randomized clinical trial." Advances in Rehabilitation 26, no. 1 (2012): 13–18. http://dx.doi.org/10.2478/rehab-2013-0025.

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Abstract More precise knowledge concerning gait patterns of movement in stroke patients incorporating modern diagnostic tools is necessary. Exact information about qualitative and quantitative changes during the process of rehabilitation based on reeducation of functions and relating it to possible changes of motor deficit will possibly lead to better physiotherapy planning. Goal of this study is to assess some components and changes of gait pattern and motor deficit after stroke to develop better physiotherapy this group of patients Materials and methods Consecutively admitting to rehabilitat

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Beinotti, Fernanda, Carla Prazeres Fonseca, Maria do Carmo Silva, Maria Izabel Fernandes de Arruda Serra Gaspar, Enio Walker Azevado Cacho, and Telma Dagmar Oberg. "Bodyweight supported treadmill training associated with functional electrical stimulation in hemiparetic patients." Acta Fisiátrica 14, no. 3 (2007): 159–63. http://dx.doi.org/10.11606/issn.2317-0190.v14i3a102824.

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The loss of the ambulation capacity in individuals with Cerebrovascular Accidents (CVA) has been attributed to hemiparesis, the most frequent cause of post-CVA impairment. New approaches, such as the bodyweight supported treadmill training (BWSTT) associated with functional electrical stimulation (FES), have been suggested as a gait rehabilitation method for hemiparetic patients. Objective: The aim of the present study was to evaluate the efficacy of the BWSTT associated to FES in hemiparetic patients. Methods: Fourteen individuals with hemiparesis due to CVA were randomly selected. The Fugl-M

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Corbett, Hank, Jonathan Carney, Ramses Gonzalez, et al. "The Evryscope Fast Transient Engine: Real-time Detection for Rapidly Evolving Transients." Astrophysical Journal Supplement Series 265, no. 2 (2023): 63. http://dx.doi.org/10.3847/1538-4365/acbd41.

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Abstract Astrophysical transients with rapid developments on subhour timescales are intrinsically rare. Due to their short durations, events like stellar superflares, optical flashes from gamma-ray bursts, and shock breakouts from young supernovae are difficult to identify on timescales that enable spectroscopic follow-up. This paper presents the Evryscope Fast Transient Engine (EFTE), a new data reduction pipeline that is designed to provide low-latency transient alerts from the Evryscopes—a north–south pair of ultra-wide-field telescopes with an instantaneous footprint covering 38% of the en

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Andres, Annchristin, Michael Roland, Marcel Orth, and Stefan Diebels. "From Injury to Full Recovery: Monitoring Patient Progress Through Advanced Sensor and Motion Capture Technology." Sensors 25, no. 13 (2025): 3853. https://doi.org/10.3390/s25133853.

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Background: Advanced sensor insoles and motion capture technology can significantly enhance the monitoring of rehabilitation progress for patients with distal tibial fractures. This study leverages the potential of these innovative tools to provide a more comprehensive assessment of a patient’s gait and weight-bearing capacity following surgical intervention, thereby offering the possibility of improved patient outcomes. Methods: A patient who underwent distal medial tibial plating surgery in August 2023 and subsequently required revision surgery due to implant failure, involving plate removal

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Kumar, Sunil, and Arun Kr Chatterjee. "Comparative study of different Sense Amplifiers in 0.18um technology." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 7, no. 3 (2013): 615–19. http://dx.doi.org/10.24297/ijct.v7i3.3440.

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A comparative study of different types of sense amplifiers [1] using 0.18um technology is presented. The sense amplifiers under considerations are used in SRAM and DRAM cells.The sensing delay of different types of sense amplifiersÂ are evaluated with respect to variation of bitline capacitance. Comparative results are also provided for the variation in delay with respect to power supply. Extensive results based on 0.18um CMOS technology using CADENCE Spectre simulation tools are presented for different architectures of sense amplifiers. From these results it has been proven that if the output

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Reig, Càndid, María-Dolores Cubells-Beltrán, Fernando Pardo, et al. "Dynamic electrical compact model of GMR sensors for neuromorphically inspired applications." AIP Advances 13, no. 2 (2023): 025225. http://dx.doi.org/10.1063/9.0000439.

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Neuromorphism is a state-of-the-art paradigm driving the design of many novel devices, including sensors. The development of such systems, usually involving the implementation of complex mixed CMOS/sensors chips, is constrained by the lack of compact electrical models compatible with the most utilized design tools. This paper proposes a dynamic compact electrical model specifically conceived for bio-inspired applications of giant magnetoresistance (GMR) based magnetic scanning sensors. The model includes blocks for static analysis, frequency sweeps, and transient simulations. The model, writte

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Fatima Sharif, Kazi, and Satyendra N. Biswas. "6 Transistors and 1 Memristor based Memory Cell." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 1 (2020): 42. http://dx.doi.org/10.11591/ijres.v9.i1.pp42-51.

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Area efficient and stable memory design is one of the most important tasks in designing system on chip. This research concentrates in designing a new type of hybrid memory model by using only nMOS transistors and memristor.<br />The proposed memory cell is very stable during successive read operates and<br />comparatively faster and also occupies less amount of silicon area. The<br />stability of the data during successive read operation and noise margin are in<br />the promising range. Extensive simulation results using LTspice and<br />Cadence software tools dem

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Anitha, Didigam, and Mohd Masood Ahmad. "Ultra-low leakage static random access memory design." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 1 (2023): 60. http://dx.doi.org/10.11591/ijres.v12.i1.pp60-69.

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An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T SRAM cells, leakage power of the proposed cell in hold mode reduced significantly. The stability parameters of the proposed cell are calculated using butterfly method and also N-curve method. Proposed SRAM achieves better write margin with slightly less read margin than 6T SRAM. Proposed technique consumes 790 PW of power in hold mode, which is very less compared to other existing techniques. Therefore, the proposed cell is appropria

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Didigam, Anitha, and Masood Ahmad Mohd. "Ultra-low leakage static random access memory design." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 1 (2023): 60–69. https://doi.org/10.11591/ijres.v12.i1.pp60-69.

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An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T SRAM cells, leakage power of the proposed cell in hold mode reduced significantly. The stability parameters of the proposed cell are calculated using butterfly method and also N-curve method. Proposed SRAM achieves better write margin with slightly less read margin than 6T SRAM. Proposed technique consumes 790 PW of power in hold mode, which is very less compared to other existing techniques. Therefore, the proposed cell is appropria

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Arsen, Ahmed Mohammed, Khalaf Mahmood Zaidoon, and Demirel Hüseyin. "New Z copy- current differencing transconductance amplifier active filter using FinFET transistor based current Mode Universal Filter." Global Journal of Engineering and Technology Advances 18, no. 2 (2024): 001–5. https://doi.org/10.5281/zenodo.10947232.

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This research paper presents the design of an active current mode device named Z-copy- Current Differencing Transconductance Amplifier (ZC-CDTA) in conjunction with FinFET (Fin Field-Effect Transistor) transistors. An input bias current can be used to adjust its parasitic resistances at its two current input ports. It is ideal for use in current-mode signal processing, which is steadily more common than voltage-style signal processing, because it operates in current mode on all terminals. The suggested component was implemented using Finfet technology, and its performances were assessed using

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Jin, Jie, Xianming Wu, and Zhijun Li. "Ultra low power mixer with out-of-band RF energy harvesting for wireless sensor networks applications." Engineering review 40, no. 1 (2020): 1–6. http://dx.doi.org/10.30765/er.40.1.01.

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An ultra low power mixer with out-of-band radio frequency (RF) energy harvesting suitable for the wireless sensors network (WSN) application is proposed in this paper. The presented mixer is able to harvest the out-of-band RF energy and keep it working in ultra low power condition and extend the battery life of the WSN. The mixer is designed and simulated with Global Foundries ’ 0.18 μ m CMOS RF process, and it operates at 2.4GHz industrial, scientific, and medical (ISM) band. The Cadence IC Design Tools post-layout simulation results demonstrate that the proposed mixer consumes 248 μ W from a

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Jin, Jie, and Li Cui. "Fully Integrated Memristor and Its Application on the Scroll-Controllable Hyperchaotic System." Complexity 2019 (January 10, 2019): 1–8. http://dx.doi.org/10.1155/2019/4106398.

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In this paper, a fully integrated memristor emulator using operational amplifiers (OAs) and analog multipliers is simulated. Based on the fully integrated memristor, a scroll-controllable hyperchaotic system is presented. By controlling the nonlinear function with programmable switches, the memristor-based hyperchaotic system achieves controllable scroll numbers. Moreover, the memristor-based hyperchaotic system is fully integrated in one single chip, and it achieves lower supply voltage, lower power dissipation, and smaller chip area. The fully integrated memristor and memristor-based hyperch

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