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Journal articles on the topic 'Canonic Signed Digit'

Author: Grafiati

Published: 4 June 2025

Last updated: 1 August 2025

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1

Ruiz, Gustavo A., and Mercedes Granda. "Efficient canonic signed digit recoding." Microelectronics Journal 42, no. 9 (2011): 1090–97. http://dx.doi.org/10.1016/j.mejo.2011.06.006.

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2

Hasan, Y. M., L. J. Karam, M. Falkinburg, A. Helwig, and M. Ronning. "Canonic signed digit Chebyshev FIR filter design." IEEE Signal Processing Letters 8, no. 6 (2001): 167–69. http://dx.doi.org/10.1109/97.923041.

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3

Hartley, R. I. "Subexpression sharing in filters using canonic signed digit multipliers." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 43, no. 10 (1996): 677–88. http://dx.doi.org/10.1109/82.539000.

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4

Sharma, Kapil, Ompal Singh, and Abhishek Bhatt. "High Speed Multi-level Discrete Wavelet Transform using Canonic Signed Digit Technique." International Journal of Computer Sciences and Engineering 7, no. 5 (2019): 1528–31. http://dx.doi.org/10.26438/ijcse/v7i5.15281531.

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5

Nair, Preethi M., Rajesh Mehra, and Chandni. "Reconfigurable Low Pass FIR Filter Design using Canonic Signed Digit for Audio Applications." Indian Journal of Science and Technology 10, no. 16 (2017): 1–6. http://dx.doi.org/10.17485/ijst/2017/v10i16/114305.

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6

Hu, S., D. Teng, S. B. Ko, and A. Dinh. "A Low Power Inverse SINC Filter Using a Modified Canonic Signed Digit Algorithm." i-manager's Journal on Electrical Engineering 1, no. 2 (2007): 36–43. http://dx.doi.org/10.26634/jee.1.2.435.

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7

Kim, Young-Woo, Young-Mo Yang, Jae-Tack Yoo, and Soo-Won Kim. "Approximate processing for low-power digital filtering using variable canonic signed digit coefficients." Electronics Letters 36, no. 1 (2000): 11. http://dx.doi.org/10.1049/el:20000050.

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8

Palchaudhuri, Ayan, and Anindya Sundar Dhar. "Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations." Journal of Electronic Testing 35, no. 6 (2019): 779–96. http://dx.doi.org/10.1007/s10836-019-05840-w.

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9

Pan, Shing-Tai. "A canonic-signed-digit coded genetic algorithm for designing finite impulse response digital filter." Digital Signal Processing 20, no. 2 (2010): 314–27. http://dx.doi.org/10.1016/j.dsp.2009.06.024.

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10

Lal, Roshan, Rajesh Mehra, and Shallu S. "FPGA based Band Pass FIR Filter using Factored Canonic Signed Digit Technique for Satellite Application." International Journal of Computer Applications 156, no. 3 (2016): 45–49. http://dx.doi.org/10.5120/ijca2016912408.

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11

Choudhary, Anjulata, Nishi Pandey, and Meha Shrivastava. "Area and Delay Efficient 2-D DWT using Canonic Signed Digit and Brent Kung Adder Technique." International Journal of Computer Sciences and Engineering 7, no. 10 (2019): 235–39. http://dx.doi.org/10.26438/ijcse/v7i10.235239.

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12

Chandra, Abhijit, and Sudipta Chattopadhyay. "Canonic Signed Digit Based Design of Multiplier-Less Fir Filter Using Self-Organizing Random Immigrants Genetic Algorithm." International Journal of Artificial Intelligence & Applications 4, no. 4 (2013): 21–34. http://dx.doi.org/10.5121/ijaia.2013.4403.

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13

Siddiq, F., H. Jamal, T. Muhammad, and M. Iqbal. "Area Efficient Radix 4 2 64 Point Pipeline FFT Architecture Using Modified CSD Multiplier." Nucleus 51, no. 3 (2014): 345–53. https://doi.org/10.71330/thenucleus.2014.689.

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A modified Fast Fourier Transform (FFT) based radix 42 algorithm for Orthogonal Frequency Division Multiplexing (OFDM) systems is presented. When compared with similar schemes like Canonic signed digit (CSD) Constant Multiplier, the modified CSD multiplier can provide a improvement of more than 36% in terms of multiplicative complexity. In Comparison of area being occupied the amount of full adders is reduced by 32% and amount of half adders is reduced by 42%. The modified CSD multiplier scheme is implemented on Xilinx ISE 10.1 using Spartan-III XC3S1000 FPGA as a target device. The synthesis

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14

Bindiya, T. S., and Elizabeth Elias. "Design of FRM-based MDFT filter banks in the canonic signed digit space using modified meta-heuristic algorithms." International Journal of Signal and Imaging Systems Engineering 9, no. 1 (2016): 20. http://dx.doi.org/10.1504/ijsise.2016.074649.

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15

Satyanarayana, Dr S. V. V., K. Teja Sri, K. Madhavi, G. Jhansi, and B. Jaya Sri. "Design and Implementation of High Speed Low Power Decimation Filter for Hearing AID Applications." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 1 (2023): 27–32. http://dx.doi.org/10.35940/ijrte.a7564.0512123.

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This work is focused on designing and implementing a decimation filter specifically intended for use in hearing aid applications. The filter utilizes distributed arithmetic (DA) and is described in this brief. Our proposal involves the development of a reconfigurable finite impulse response (FIR) filter, which utilizes both offset binary code (OBC) and binary distributed arithmetic (DA) techniques. Additionally, we utilize canonic signed digit (CSD) representation to develop decimation filters, which include the CIC filter, half band filter, and corrector filter. In this work, we have implemen

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16

Manuel, Manju, and Elizabeth Elias. "Design of frequency response masking FIR filter in the Canonic Signed Digit space using modified Artificial Bee Colony algorithm." Engineering Applications of Artificial Intelligence 26, no. 1 (2013): 660–68. http://dx.doi.org/10.1016/j.engappai.2012.02.010.

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17

Dr., S. V. V. Satyanarayana, Teja Sri K, Madhavi K, Jhansi G, and Jaya Sri B. "Design and Implementation of High Speed Low Power Decimation Filter for Hearing AID Applications." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 1 (2023): 27–32. https://doi.org/10.35940/ijrte.A7564.0512123.

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<strong>Abstract: </strong>This work is focused on designing and implementing a decimation filter specifically intended for use in hearing aid applications. The filter utilizes distributed arithmetic (DA) and is described in this brief. Our proposal involves the development of a reconfigurable finite impulse response (FIR) filter, which utilizes both offset binary code (OBC) and binary distributed arithmetic (DA) techniques. Additionally, we utilize canonic signed digit (CSD) representation to develop decimation filters, which include the CIC filter, half band filter, and corrector filter. In

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18

Chen, Ming-Chih, and Tsung-Ting Chen. "Minimizing Design Costs of an FIR Filter Using a Novel Coefficient Optimization Algorithm." Mathematical Problems in Engineering 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/497471.

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This work presents a novel coefficient optimization algorithm to reduce the area and improve the performance of finite impulse response (FIR) filter designs. Two basic architectures are commonly used in filters—direct and transposed. The coefficients of a filter can be encoded in the fewest possible nonzero bits using canonic signed digit (CSD) expressions. The proposed optimization algorithm can share common subexpressions (CS) and reduce the number of replicate operations that involve the CSD coefficients of filters with a transposed architecture. The effectiveness of the algorithm is confir

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19

KAMBOH, HAMID M., and SHOAB A. KHAN. "HIGH THROUGHPUT FILTER ARCHITECTURE FOR OPTIMAL FPGA-BASED IMPLEMENTATIONS." Journal of Circuits, Systems and Computers 22, no. 05 (2013): 1350034. http://dx.doi.org/10.1142/s0218126613500345.

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Modern field programmable gate arrays (FPGAs) offer built in support for efficient implementation of signal processing algorithms in the form of specialized embedded blocks such as high speed carry chains, specialized shift registers, adders, multiply accumulators (MAC) and block memories. These dedicated elements provide increased computational power and are used for efficient implementation of computationally extensive algorithms. This paper proposes a novel algorithm and architecture for the design and implementation of high performance intermediate frequency (IF) filters on FPGAs. In this

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20

Das, Bhagwan, Javed Ali Jamali, Mahendar Kumar, Dilip Kumar Ramnani, and Z. A. Memon. "Design and Performance Analysis of Improved FIR Filter using UltraScale FPGA." Sir Syed University Research Journal of Engineering & Technology 12, no. 1 (2022): 14–22. http://dx.doi.org/10.33317/ssurj.414.

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It is discussed in many studies and demonstrated in the many researches that based on certain applications, analog design of filter has several issues including complex design, re-use Limitations, and accuracy of generating the output at various frequencies. Therefore, instead of analog filter design the digital design of the filter is preferred for both Finite and Infinite Impulse Response Filter. This paper demonstrates the design of the digital FIR filter designed is demonstrated using ultrascale Field Programming Gate Array. The filter is designed using Coefficient multiplier via Canonic S

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21

Pan, Shing-Tai. "CSD-Coded Genetic Algorithm on Robustly Stable Multiplierless IIR Filter Design." Mathematical Problems in Engineering 2012 (2012): 1–15. http://dx.doi.org/10.1155/2012/560650.

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A Canonic-Signed-Digit-(CSD-) coded genetic algorithm (GA) is proposed to find the optimal design of robustly stable infinite impulse response digital filter (IIR). Under the characteristics of the CSD structure, the circuit of the filter can be simplified and also the calculation speed can be raised to increase the hardware’s efficiency. However, the design of CSD has a big challenge: the CSD structure of the system parameters will be destroyed by an optimal design procedure. To solve this problem, in this research a CSD-coded GA is proposed so that the CSD structure can be maintained. Moreov

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22

Wan, Renzhuo, Yuandong Li, Chengde Tian, et al. "Design and Implementation of Sigma-Delta ADC Filter." Electronics 11, no. 24 (2022): 4229. http://dx.doi.org/10.3390/electronics11244229.

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This paper presents a digital decimation filter based on a third-order four-bit Sigma-Delta modulator. The digital decimation filter is an important part of the Sigma-Delta ADC and is designed to make the Sigma-Delta ADC (Analog-to-Digital Converter) meets the requirements of Signal-to-Noise Ratio (SNR) not less than 120 dB and Equivalent Number of Bits (ENOB) not less than 20 bits. It adopts a three-stages cascaded structure including a Cascaded Integrator Comb (CIC) decimation filter, a Finite Impulse Response (FIR) compensation filter, and a half-band (HB) filter. This structure effectively

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23

Tanaka, Yuuki. "Efficient signed-digit-to-canonical-signed-digit recoding circuits." Microelectronics Journal 57 (November 2016): 21–25. http://dx.doi.org/10.1016/j.mejo.2016.09.001.

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24

Lakshmi, Kiran Mukkara, and Venkata Ramanaia K. "Neuronal logic gates realization using CSD algorithm." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 2 (2019): 145–50. https://doi.org/10.11591/ijres.v8.i2.pp145-150.

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Any digital circuit is made with fundamental building blocks i.e. logic gates. Artificial neural networks (ANN) became an emerging area in various applications such as prediction problems, pattern recognition, and robotics and system identification due to its processing capabilities with parallel architecture. Realization of Boolean logic with neural networks is referred as neuronal logic. ANN computes faster as it requires of low and simple precision computations. Also, it requires economic and low precision hardware. Neural network contains more number of addition and multiplication processe

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25

Tanaka, Yuuki, and Shugang Wei. "Efficient squaring circuit using canonical signed-digit number representation." IEICE Electronics Express 11, no. 2 (2014): 20130955. http://dx.doi.org/10.1587/elex.11.20130955.

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26

Ruiz, G. A., and M. A. Manzano. "Self-timed multiplier based on canonical signed-digit recoding." IEE Proceedings - Circuits, Devices and Systems 148, no. 5 (2001): 235. http://dx.doi.org/10.1049/ip-cds:20010524.

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27

Cherri, A. K., M. S. Alam, and A. A. S. Awwal. "Optoelectronic symbolic substitution based canonical modified signed-digit arithmetic." Optics & Laser Technology 29, no. 3 (1997): 151–57. http://dx.doi.org/10.1016/s0030-3992(96)00062-x.

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28

Cherri, A. K., and N. I. Khachab. "Canonical quaternary signed-digit arithmetic using optoelectronics symbolic substitution." Optics & Laser Technology 28, no. 5 (1996): 397–403. http://dx.doi.org/10.1016/0030-3992(95)00109-3.

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29

Yang, Sejung. "Efficient transform using canonical signed digit in reversible color transforms." Journal of Electronic Imaging 18, no. 3 (2009): 033010. http://dx.doi.org/10.1117/1.3206966.

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30

Chang, Te Jen, Ping Sheng Huang, Shan Jen Cheng, Ching Yin Chen, and I. Hui Pan. "Low-Complexity Multiplication Using Complement and Signed-Digit Recoding Methods." Applied Mechanics and Materials 619 (August 2014): 342–46. http://dx.doi.org/10.4028/www.scientific.net/amm.619.342.

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In this paper, a fast multiplication computing method utilizing the complement representation method and canonical recoding technique is proposed. By performing complements and canonical recoding technique, the number of partial products can be reduced. Based on these techniques, we propose algorithm provides an efficient multiplication method. On average, our proposed algorithm to reduce the number of k-bit additions from (0.25k+logk/k+2.5) to (k/6 +logk/k+2.5), where k is the bit-length of the multiplicand A and multiplier B. We can therefore efficiently speed up the overall performance of t

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31

Tanaka, Yuuki. "Another Implementation of Efficient Recoding Circuit for Signed Digit to Residue Canonical Signed Digit on Modulo 2ⁿ-1." Applied Mechanics and Materials 888 (February 2019): 78–82. http://dx.doi.org/10.4028/www.scientific.net/amm.888.78.

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In this paper, we propose an efficient SD-to-RCSD recoding circuit structure on modulo. This structure is based on the parallel prefix addition circuit, that is, a carry for each digits is precalculated in parallel.

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32

Mathew, S., R. Mehra, and Chandni. "FPGA Based Equiripple Canonical Signed Digit FIR Filter for Audio Applications." Indian Journal of Science and Technology 10, no. 16 (2017): 1–6. http://dx.doi.org/10.17485/ijst/2017/v10i16/114306.

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33

S, Saloni, and Dr Neelam Rup Prakash. "Low Power 4*4 Canonical Signed Digit Multiplier using 90nm Technology." IJIREEICE 5, no. 6 (2017): 205–10. http://dx.doi.org/10.17148/ijireeice.2017.5635.

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34

TAN, Jia-jie, San-wei HUANG, and Chang-qin ZOU. "Optimal algorithm for FIR digital filter with canonical signed digit coefficients." Journal of Computer Applications 31, no. 6 (2012): 1727–29. http://dx.doi.org/10.3724/sp.j.1087.2011.01727.

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35

Aliasgari, Mohammad, Yeganeh M. Marghi, Mohammadreza Baharani, and Sied Mehdi Fakhraie. "Multiplierless filter-bank based multicarrier system by using canonical signed digit representation." Wireless Communications and Mobile Computing 16, no. 5 (2014): 563–77. http://dx.doi.org/10.1002/wcm.2553.

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36

Ravichandran, S., S. Muthukkumar, and M. Sabarish. "Design and Development of Diminution of Multiplier in FIR Sieve Consuming Mutual Sub-Expression Removal Algorithm." Asian Journal of Science and Applied Technology 10, no. 2 (2021): 26–33. http://dx.doi.org/10.51983/ajsat-2021.10.2.3072.

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The difficulty of Finite-Impulse-Response (FIR) sieve out is ruled with means of that wide variety of adders or subtractors that are consumed toward enforce these co-green multipliers. The Common-Sub-expression-Elimination (CSE) set of rules is founded totally at that Canonical-Signed-Digit (CSD) depiction of clear out co-efficient pro imposing stumpy difficulty FIR sieves. Now, decrease of multiplier inside rectilinear phase FIR sieves is completed through changing this multiplier quantity toward Minimum-Signed-Powers-of-Two (MNSPT) or Canonical-Signed-Digit (CSD) illustration of this multipl

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37

Manoj, V. J., and E. Elizabeth. "Design of non-uniform filter bank transmultiplexer with canonical signed digit filter coefficients." IET Signal Processing 3, no. 3 (2009): 211. http://dx.doi.org/10.1049/iet-spr.2008.0209.

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38

Nam, MyungWoo, and Young-Seok Lee. "Study on the Generation of Inaudible Binary Random Number Using Canonical Signed Digit Coding." Journal of Korea Institute of Information, Electronics, and Communication Technology 8, no. 4 (2015): 263–69. http://dx.doi.org/10.17661/jkiiect.2015.8.4.263.

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39

Xu, Fei, Chip-Hong Chang, and Ching-Chuen Jong. "Hamming weight pyramid – A new insight into canonical signed digit representation and its applications." Computers & Electrical Engineering 33, no. 3 (2007): 195–207. http://dx.doi.org/10.1016/j.compeleceng.2006.09.001.

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40

Geetha, V., and G. Murugesan. "Performance analysis of Horner's rule-based canonical signed digit lifting architecture for two-dimensional discrete wavelet transform." International Journal of Biomedical Engineering and Technology 23, no. 2/3/4 (2017): 123. http://dx.doi.org/10.1504/ijbet.2017.082654.

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41

Geetha, V., and G. Murugesan. "Performance analysis of Horner's rule-based canonical signed digit lifting architecture for two-dimensional discrete wavelet transform." International Journal of Biomedical Engineering and Technology 23, no. 2/3/4 (2017): 123. http://dx.doi.org/10.1504/ijbet.2017.10003492.

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42

Williams, T., M. Ahmadi, and W. C. Miller. "Design of 2D FIR and IIR Digital Filters with Canonical Signed Digit Coefficients Using Singular Value Decomposition and Genetic Algorithms." Circuits, Systems & Signal Processing 26, no. 1 (2007): 69–89. http://dx.doi.org/10.1007/s00034-005-1015-9.

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43

Hussain, Md Zakir, and Kazi Nikhat Parvin. "Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 12, no. 01 (2020): 8–12. http://dx.doi.org/10.18090/samriddhi.v12i01.2.

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This study represents the designing and implementation of a bandpass finite impulse response (FIR) filter of order 31 using windowing techniques. The frequency parameters used are of a typical GSM receiver,19 which is one of the applications of software-defined radio (SDR). To minimize filter area, various multiplication techniques like a canonical signed digit, Vedic multiplier, booth multiplier, and modified booth multiplier are used. Adders like ripple carry adder, carry save adder, carry look ahead adder, and Kogge-Stone adder are used to add the product from the multiplier unit. A compari

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44

Krishna, Merugumalli Rama, K. Sri Lakshmi, S. Lalitha, and C. Amulya. "Low Latency and Efficient LUT Based Multiplier for DSP Applications." International Journal of Advance Research and Innovation 8, no. 2 (2020): 91–96. http://dx.doi.org/10.51976/ijari.822016.

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In digital signal processing memory based computation plays a vital role for DSP applications, which has multiplication with a fixed set of coefficient. LUT optimization for memory based multiplication can be done with these three computational techniques like Anti symmetry product coding (APC) and Odd multiple storage (OMS), combined APC-OMS. OMS technique with the modified APC-OMS based LUT multiplier can be discussed in terms of area and delay. These techniques are coded in VHDL language and synthesized in Xilinx ISE design suite 14.7. Thus, this proposes the APC-OMS based LUT multiplier ca

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45

Jridi, Maher, Ayman Alfalou, and Pramod Kumar Meher. "Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression." VLSI Design 2012 (May 30, 2012): 1–12. http://dx.doi.org/10.1155/2012/209208.

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The canonical signed digit (CSD) representation of constant coefficients is a unique signed data representation containing the fewest number of nonzero bits. Consequently, for constant multipliers, the number of additions and subtractions is minimized by CSD representation of constant coefficients. This technique is mainly used for finite impulse response (FIR) filter by reducing the number of partial products. In this paper, we use CSD with a novel common subexpression elimination (CSE) scheme on the optimal Loeffler algorithm for the computation of discrete cosine transform (DCT). To meet th

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46

Chen, Ming-Chih, and Hong-Yi Wu. "Low-Cost Design of an FIR Filter by Using a Coefficient Mapping Method." Mathematical Problems in Engineering 2013 (2013): 1–6. http://dx.doi.org/10.1155/2013/495207.

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This work presents a novel coefficient mapping method to reduce the area cost of the finite impulse response (FIR) filter design, especially for optimizing its coefficients. Being capable of reducing the area cost and improving the filter performance, the proposed mapping method consists of four steps: quantization of coefficients, import of parameters, constitution of prime coefficients with parameters, and constitution of residual coefficients with prime coefficients. Effectiveness of the proposed coefficient mapping method is verified by selecting the 48-tap filter of IS-95 code division mu

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47

Siddiqui, M. F., A. W. Reza, J. Kanesan, and H. Ramiah. "Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture." Scientific World Journal 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/620868.

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A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD) representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coeffi

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48

Arumugam, N., and B. Paramasivan. "An integrated FIR adaptive filter design by hybridizing canonical signed digit (CSD) and approximate booth recode (ABR) algorithm in DA architecture for the reduction of noise in the sensor nodes." Multidimensional Systems and Signal Processing 32, no. 4 (2021): 1277–311. http://dx.doi.org/10.1007/s11045-021-00783-y.

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49

Arun, C. A., and Prakasam Periasamy. "Design of Eight Parallel 512-Point MDF FFT/IFFT Processor for WPAN Applications." Journal of Circuits, Systems and Computers 28, no. 05 (2019): 1950088. http://dx.doi.org/10.1142/s0218126619500889.

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This paper presents a high-speed FFT algorithm for high data rate wireless personal area network applications. In a wireless personal area network, the FFT/IFFT block leads the major role. Computational requirements of FFT processors are a heavy burden in most real-time applications. From the previous work, it can be recognized that most of the FFT structures follow the divide and conquer algorithms, which improve the computational efficiency. In the proposed model, a new design of 512-point FFT/IFFT processor is derived by mixed approach for a Radix-26 algorithm, which has been presented and

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50

Nguyen, Hung, Sheraz Khan, Cheol-Hong Kim, and Jong-Myon Kim. "A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis." Electronics 7, no. 8 (2018): 137. http://dx.doi.org/10.3390/electronics7080137.

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The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of rotary machines. The complexity and cost of the associated hardware limit the use of FFT in real-time applications. In this paper, an efficient hardware architecture for FFT implementation is proposed based on the radix-2 decimation in frequency algorithm (R2DIF) and a feedback pipelined technique (FB) that allows effective sharing of storage between the input and output data at each stage of the FFT process vi

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