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Journal articles on the topic 'Carry Look Ahead Adder (CLAA)'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." International Daily journal, Discovery Publication 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.32686.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each

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2

Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." Discovery The International Daily journal 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.33104.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design.High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each s

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3

Maroju, SaiKumar, and P. Samundiswary Dr. "Design and Performance Analysis of Various Adders using Verilog." International Journal of Computer Science and Mobile Computing 2, no. 9 (2013): 128–38. https://doi.org/10.5281/zenodo.32564.

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Adders are one of the most widely digital components in the digital integrated circuit design and are the necessary part of Digital Signal Processing (DSP) applications. With the advances in technology, researchers have tried and are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper, the design of various adders such as Ripple Carry Adder (RCA), Carry Skip Adder (CSkA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLaA), Carry Save Adder (CSA), Carry Select Adder (CSlA), Carry Bypass Add

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4

S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster spee

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5

Balasubramanian, Padmanabhan, and Weichen Liu. "High-speed and energy-efficient asynchronous carry look-ahead adder." PLOS ONE 18, no. 10 (2023): e0289569. http://dx.doi.org/10.1371/journal.pone.0289569.

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Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm

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6

Neeraj, Jain, Gour Puran, and Shrman Brahmi. "A High Speed Low Power Adder in Multi Output Domino Logic." International Journal of Computer Applications 105, no. 7 (2014): 30–33. https://doi.org/10.5281/zenodo.33240.

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Speed and power is the major constraint in modern digital design so it is required to design the high speed, less number of transistors as a prime consideration. The low power carry look ahead adder using static CMOS transmission gate logic that overcomes the limitation of series connected pass transistors in the carry propagation path. In this approach it is required to find the longest critical paths in the multi-bit adders and then shortening the path to reduce the total critical path delay. The design simulation on microwind layout tool shows the worst-case delay in ns and total power cons

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7

Shishir, A. Bagal, R. Asamwar Saikiran, and Dhengre Sujal. "An Exhaustive Review on Optimization of Carry-Look-Ahead Adder Using Hybrid Logic." International Journal of Innovative Science and Research Technology (IJISRT) 10, no. 2 (2025): 1548–54. https://doi.org/10.5281/zenodo.14964543.

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A revolutionary method for designing contemporary digital circuits is the use of hybrid logic in the creation of carry-look ahead adders (CLAs), which combine CMOS and memristor technology. By combining the scalability and dependability of CMOS technology with the special qualities of memristors—such as their small size, low power consumption, and non-volatile nature—this review paper investigates developments in CLA architectures. The compiled studies demonstrate how hybrid memristor-CMOS designs can be used to get around drawbacks in conventional CLA implementations, such as decr

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8

Chirag, M., and K.B.Ramesh. "Design and Implementation of 4-bit Multiplier using Vedic System." Journal of VLSI Design and its Advancement 7, no. 2 (2024): 38–44. https://doi.org/10.5281/zenodo.12635137.

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<em>An efficient and fast 4-bit multiplier is designed, analyzed and presented. It is achieved using a Carry-Look Ahead adder, in short CLA adder, circuit. The ancient technique known presently as ‘Vedic Mathematics’ and is based on </em><em>'Urdhva Tiryakbhyam sutra' algorithm. This type of modification increases the speed of the asked multiplication by nearly 45%. It further delves into the differences between the traditional method and the proposed method. This article expands further about all the topics mentioned above.</em>

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9

RamakrishnaReddy, Eamani, Nallathambi Vinodhkumar, and Asaithambi Sasikumar. "A low-power high speed full adder cell using carbon nanotube field effect transistors." A low-power high speed full adder cell using carbon nanotube field effect transistors 31, no. 1 (2023): 134–42. https://doi.org/10.11591/ijeecs.v31.i1.pp134-142.

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The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1- bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model

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10

YUAN, SHOUCAI, and YAMEI LIU. "DUAL THRESHOLD VOLTAGE DOMINO ADDER DESIGN WITH PASS TRANSISTOR LOGIC USING STANDBY SWITCH FOR REDUCING SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 03 (2014): 1450043. http://dx.doi.org/10.1142/s0218126614500431.

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Standby switch can strongly turn off all the high threshold voltage transistors, which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce sub-threshold leakage current. Sub-threshold leakage currents are especially important in burst mode type integrated circuits where the system is in an idle mode in the majority of the time. The standby switch allows a domino system to enter and leave a low leakage standby mode within a single clock cycle. In addition, we combine domino dynamic logic with pass transistor XNOR and pass transistor NAND gates to achieve logic 1 out

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11

Ch., Praveen Kumar, and Praveen Kumar K. "IMPLEMENTATION OF A 8 BIT HIGH PERFORMANCE MULTIPLIER USING HDL." International Journal of Advances in Engineering & Scientific Research 1, no. 6 (2014): 23–30. https://doi.org/10.5281/zenodo.10725210.

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<strong><em>Abstract</em></strong> <em>This paper presents an area efficient implementation of a 8 bit high performance parallel multiplier.  Radix-8  Booth  multiplier  with  carry  look ahead adder and modified carry look ahead adder are presented here. The design is structured for 8   bit multiplication. Carry Look ahead Adder is used as the final adder to enhance the speed of operation. Finally the performance improvement of the proposed multipliers is validated  by  implementing  a  multiplier  with  modified carry&nbsp

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12

Crawley, D. G., and G. A. J. Amaratunga. "Pipelined carry look-ahead adder." Electronics Letters 22, no. 12 (1986): 661. http://dx.doi.org/10.1049/el:19860452.

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13

Hari Kishore, K., B. K. V.Prasad, Y. Manoj Sai Teja, D. Akhila, K. Nikhil Sai, and P. Sravan Kumar. "Design and comparative analysis of inexact speculative adder and multiplier." International Journal of Engineering & Technology 7, no. 2.8 (2018): 413. http://dx.doi.org/10.14419/ijet.v7i2.8.10472.

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A Carry look ahead adder is a sort of the summer used in the logic design of the digital systems. The CLA boost up the speed by decreasing the measure of duration needed to calculate the carry bits. The CLA based outline of the inexact speculative adder is pipelined architecture to incorporate couple of logic paths along its basic way and in this manner, improving the recurrence of operation. This paper presents the comparative analysis of the pipelined inexact speculative adder and the general carry look ahead adder and showed that the delay is reduced to 48.27% when compared to carry look ah

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14

Nikhita, Matti*1 Rohini Hongal 2. R. B. Shettar 3. "PERFORMANCE ANALYSIS OF DIFFERENT N-BIT ADDERS USING REVERSIBLE LOGIC ON FPGA BOARD USING CHIPSCOPE." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 8 (2017): 307–18. https://doi.org/10.5281/zenodo.843985.

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In current scenario, high-performance chips releasing large amounts of heat impose practical limitation. Reversible circuits that conserve information, by uncomputing bits instead of throwing them away. Reversible logic design attracting more interest due to its low power consumption. The paper gives brief idea to build variety of n-bit adders like Ripple carry adder, Carry look ahead adder, Carry save adder, Carry skip adder and Carry select adder circuits using the basic reversible gate like Peres gate, TSG, MTS, Taffoli, HNG etc. The designed adders are verified using chipscope on FPGA plat

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15

Lavanya, P., B. Chinna Rao, and T. Vishnu Murty. "High Efficient Carry Select Adder using Zero Carry Look Ahead Adder." International Journal of Engineering Trends and Technology 18, no. 1 (2014): 42–46. http://dx.doi.org/10.14445/22315381/ijett-v18p208.

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16

Corsonello, P., S. Perri, and G. Cocorullo. "Hybrid carry-select statistical carry look-ahead adder." Electronics Letters 35, no. 7 (1999): 549. http://dx.doi.org/10.1049/el:19990375.

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17

Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas

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18

Dr., Anuradha M. Sandi. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2019): 40–50. https://doi.org/10.5281/zenodo.3245207.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas

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19

Becker, Bernd, and Reiner Kolla. "On the Construction of Optimal Time Adders." Fundamenta Informaticae 12, no. 2 (1989): 205–20. http://dx.doi.org/10.3233/fi-1989-12207.

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In this paper we present the design of a novel optimal time adder: the conditional carry adder. In order to perform addition a tree-like combination of multiplexer cells is used in the carry computation part. We show that, for the complete conditional carry adder, this results in an overall computation time which seems to be substantially shorter than for any other known (optimal time) adder (e.g. carry look ahead adders ([5]) or conditional sum adders ([12])). The second part of this paper contains a uniform approach to the computation of the carry function resulting in seven different classe

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20

Kostrzewski, Andrew, Dai Hyun Kim, Yao Li, and George Eichmann. "Fast hybrid parallel carry look-ahead adder." Optics Letters 15, no. 16 (1990): 915. http://dx.doi.org/10.1364/ol.15.000915.

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21

Afridi, Shaik Mahammad Ameer. "4-bit Carry Look Ahead Adder Using MGDI Technique." International Journal for Research in Applied Science and Engineering Technology 9, no. 9 (2021): 855–60. http://dx.doi.org/10.22214/ijraset.2021.38075.

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Abstract: Today's high-performance processor is built with arithmetic logic units that add and subtract key components. Design considerations related to low power and high performance digital VLSI circuits have become more prevalent in today's world. In order to develop low-power and high-performance processors, the designers need to design their adder circuits with the required speed and power dissipation for their applications. This topic introduces the concept of a adder using MGDI Technique. The Exact Speculative Carry Look Ahead Adder the use of the Modified-GDI (Modified-Gate Diffusion I

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22

Aritra, Mitra, Bakshi Amit, Sharma Bhavesh, and Didwania Nilesh. "Design of a High Speed Adder." International Journal of Scientific & Engineering Research 6, no. 4 (2015): 918–21. https://doi.org/10.5281/zenodo.33243.

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In this paper we have compared different addition algorithms such as Ripple Carry Adder, Carry Save Adder, Carry Select Adder, Carry Look Ahead Adder & Kogge Stone Adder for different performance parameters i.e. Area Utilization, Speed of operation and Power Consumption. A high speed Adder is then designed by merging Kogge Stone & Carry Select Algorithms. The circuits have been designed using Verilog HDL & Synthesize using TSMC 180 nm standard cell. The performance parameters are obtained with the help of Cadence Encounter RTL Compiler.

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23

Gupta, Chirag. "16-Bit Carry Look-Ahead Adder: Design and Layout with Cadence Tools Top of Form." International Journal for Research in Applied Science and Engineering Technology 12, no. 3 (2024): 514–19. http://dx.doi.org/10.22214/ijraset.2024.58859.

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Abstract: The development of highly organised architecture is the primary goal of the current communication world in order to achieve high speed computation with low power consumption. The Carry Look Ahead Adder is highly efficient due to its ability to reduce the propagation time of carry bits, resulting in time savings. The implementation of a 16-Bit Carry Look Ahead Adder using the Cadence tool is carried out in our project. Logical equations for carry generation (G) and carry propagation (P) are used to create the carry and sum for the 1-bit adder. Then, using the Virtuoso schematic editor

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24

Rashmi, B. K., J. Rohith, Suresh Mudaladavar Shreya, Hosageri Supreet, and P. Mattada Mahantesh. "Performance and analysis of different adder topologies." i-manager’s Journal on Electronics Engineering 14, no. 3 (2024): 31. http://dx.doi.org/10.26634/jele.14.3.20675.

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This paper gives an overview of area, power, delay for four different 64-bit adders. The design metrics in VLSI are low area and delay alongside low power designs. Adder is one of the necessary components of almost every kind of digital and high- performance systems such as FIR filters, digital signal processors and microprocessors etc. Different types of adders are carry tree adder, carry save adder, carry look ahead adder and carry select adder. In this work we have designed, simulated and synthesized these adder topologies and compared the results in cadence tool.

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25

Balasubramanian, Padmanabhan, and Nikos E. Mastorakis. "High-Speed and Energy-Efficient Carry Look-Ahead Adder." Journal of Low Power Electronics and Applications 12, no. 3 (2022): 46. http://dx.doi.org/10.3390/jlpea12030046.

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The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry t

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26

Haruehanroengra, Sansiri, and Wei Wang. "Efficient Design of QCA Adder Structures." Solid State Phenomena 121-123 (March 2007): 553–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.121-123.553.

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Optimizing arithmetic primitives such as quantum-dot cellular automata (QCA) adders is important for investigating high-performance QCA computers in this emerging nano-technological paradigm. In this paper, we demonstrate that QCA ripple carry adder and bit-serial adder designs actually outperform carry-look-ahead and carry-select adder designs because of the increase in required interconnects. Simulation results obtained by using the QCADesigner tool for the proposed adder designs are also presented.

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27

Kamaraju, M., P. Ashok Babu, P. Himasri, and S. Akshitha. "Power and Area Efficient Four-Bit Vedic Multiplier Implemented Using a Modified Five-Bit Adder with CMOS and TG Configuration." Journal of Controller and Converters 9, no. 1 (2024): 27–36. http://dx.doi.org/10.46610/jcc.2024.v090i01.005.

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Vedic multipliers are incredibly fast, efficient, and flexible, perfect for efficiently handling tasks like signal processing. Vedic multipliers are the go-to choice for maximizing performance and efficiency in digital designs, as the existing method adders like Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA) have more delay, area and power. The project proposal presents a novel 4-bit Vedic multiplier essential to system functionality. Optimizing the balancing area and delay is necessary for improving the system as a whole. This project aims to strike this

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28

S, Pragadeswaran, Vasanthi M, Veera Boopathy E, et al. "OPTIMIZING VLSI ARCHITECTURE WITH CARRY LOOK AHEAD TECHNOLOGY BASED HIGH-SPEED, INEXACT SPECULATIVE ADDER." Archives for Technical Sciences 2, no. 31 (2024): 220–29. https://doi.org/10.70102/afts.2024.1631.220.

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This paper describes the design of the Carry Look-ahead Adder (CLA), which uses the Inexact Speculative Adder (ISA). The speculative adder is designed for high-speed VLSI architecture and features advanced compensation techniques and optimized hardware efficiency. Considered to be the adder's critical path, it is finely pipelined to contain a few logic gates along its carry propagation chain. This increases the frequency of operation by employing CLA, which is pipelined with some logic gates. To lower the model's power consumption, a separate planned ISA stage has been clocked gated. The Field

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29

Durga, Gaddam Naga, and D. V. A. N. Ravi Kumar. "Gdi Technique Based Carry Look Ahead Adder Design." IOSR Journal of VLSI and Signal Processing 4, no. 6 (2014): 01–09. http://dx.doi.org/10.9790/4200-04610109.

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30

Kesav, V. Silpa, G. Sai Srinadh, and Shaik Javeed. "High Performance ALU Using Carry Look-ahead Adder." CVR Journal of Science & Technology 15, no. 1 (2018): 62–66. http://dx.doi.org/10.32377/cvrjst1511.

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31

Doran, R. W. "Variants of an improved carry look-ahead adder." IEEE Transactions on Computers 37, no. 9 (1988): 1110–13. http://dx.doi.org/10.1109/12.2261.

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32

Chu, Shunan. "Comparative Analysis of Optimization Schemes of Carry Look-ahead Adder." Journal of Physics: Conference Series 2290, no. 1 (2022): 012008. http://dx.doi.org/10.1088/1742-6596/2290/1/012008.

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Abstract Conventional CLA adder has has a large number of transistors and high input impedance, which affects various performance aspects, resulting in high delay and power consumption. Therefore, to increase the performance and reduce delay, several optimized structures of CLA are proposed. From the perspective of structure and power, this paper selects four different design schemes and uses Cadence Virtuoso 90nm technology to compare and analyze the optimization results in aspects of circuit area, delay and power consumption. The analysis results show that the conventional 4-bit adder struct

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33

Bhati, Satyandra, Neeraj Sharma, and Meetu Nag. "Performance Analysis of High Speed and Low Power Binary Adders." IOP Conference Series: Materials Science and Engineering 1224, no. 1 (2022): 012026. http://dx.doi.org/10.1088/1757-899x/1224/1/012026.

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Abstract In all the arithmetic operations, addition is one of the most important and initial operations used in most of the mathematical equations. The operation is performed by many adders present in the digital world. These adders give us carries with preferred delay and power. The three main features like structure, logic, and compact circuit layout help design a better adder. This Paper aims to analyse and compare various additions for high-speed, low-power and fast calculation. The various adder designs seen in digital signal processing applications require computationally efficient addin

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34

Lin, Yu Shen, and Damu Radhakrishnan. "Delay Efficient 32-Bit Carry-Skip Adder." VLSI Design 2008 (April 2, 2008): 1–8. http://dx.doi.org/10.1155/2008/218565.

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The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25 m C

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35

Bala, Anku, and Rajesh Mehra. "Area Efficient Design Analysis of Carry Look Ahead Adder." International Journal of Computer Applications 119, no. 20 (2015): 1–4. http://dx.doi.org/10.5120/21180-4215.

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36

Akbari, Omid, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. "RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 8 (2018): 1089–93. http://dx.doi.org/10.1109/tcsii.2016.2633307.

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37

Desoete, Bart, and Alexis De Vos. "A reversible carry-look-ahead adder using control gates." Integration 33, no. 1-2 (2002): 89–104. http://dx.doi.org/10.1016/s0167-9260(02)00051-2.

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38

Alkurwy, Salah Hasan, and Isam Salah Hameed. "A novel pipelined carry adder design based on half adder." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 2 (2022): 763–70. https://doi.org/10.11591/ijeecs.v25.i2.pp763-770.

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A new design of binary parallel adder circuit is presented in this paper. The pipeline technique is applied to implement a group of a half adder (HA) blocks to architect the proposed adder. The pipelined carry adder (PCA) method is suitable for carrying out the desired adder by using the HA circuits of XOR and AND gates. The applied technique reduces the critical path delay by 27% compared with the ripple carry adder (RCA) and relatively lowers logic gates by 55% compared with the carry look-ahead adder (CLA). The coded design of the proposed circuit is implemented and simulated on the Cyclone

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39

Swami G, Narayan, Bhuvana D T, Keerthana M R, Ankita B, and Manoja E. "Optimization of Delay and Area for Approximate Radix-8 Booth Multiplier." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–6. https://doi.org/10.55041/ijsrem39405.

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This paper investigates the optimization of Radix-8 Booth Multipliers, which are essential for efficient arithmetic operations in modern digital systems, particularly in applications such as digital signal processing, telecommunications, and image processing where rapid and accurate calculations are crucial. The study aims to enhance performance by focusing on reducing both delay and area while ensuring that acceptable accuracy levels are maintained for error-tolerant applications. To achieve these optimization goals, we compare three methodologies: the Carry Save Adder (CSA), the Kogge Stone

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40

Sharma, Vaishali. "Design, Implementation & Performance of Vedic Multiplier Based on Look Ahead Carry Adder for Different Bit Lengths." International Journal for Research in Applied Science and Engineering Technology 10, no. 1 (2022): 24–30. http://dx.doi.org/10.22214/ijraset.2022.39759.

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Abstract: This paper proposed the layout of Vedic Multiplier based totally on Urdhva Trigbhyam approach of multiplication. It is most effective Vedic sutras for multiplication. Urdhva triyagbhyam is a vertical and crosswise approach to discover product of two numbers. Multiplication is an essential quintessential feature in arithmetic logic operation. Computational overall performance of a DSP device is limited via its multiplication overall performance and since, multiplication dominates the execution time of most DSP algorithms. Multiplication is one of the simple arithmetic operations and i

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Alkurwy, Salah Hasan, and Isam Salah Hameed. "A novel pipelined carry adder design based on half adder." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 2 (2022): 763. http://dx.doi.org/10.11591/ijeecs.v25.i2.pp763-770.

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<span lang="EN-US">A new design of binary parallel adder circuit is presented in this paper. The pipeline technique is applied to implement a group of a half adder (HA) blocks to architect the proposed adder. The pipelined carry adder (PCA) method is suitable for carrying out the desired adder by using the HA circuits of XOR and AND gates. The applied technique reduces the critical path delay by 27% compared with the ripple carry adder (RCA) and relatively lowers logic gates by 55% compared with the carry look-ahead adder (CLA). The coded design of the proposed circuit is implemented and

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B., Paulin Boale, Simon Ntumba B., and Eugene Mbuyi M. "Performance of Adder Architectures on Encrypted Integers." International Journal of Engineering and Advanced Technology 10, no. 6 (2021): 216–21. http://dx.doi.org/10.35940/ijeat.f3083.0810621.

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The fully Homomorphic encryption scheme is corner stone of privacy in an increasingly connected world. It allows to perform all kinds of computations on encrypted data. Although, time of computations is bottleneck of numerous applications of real life. In this paper, a brief description is made on the homomorphic encryption scheme TFHE of Illaria Chillota and the others. TFHE, implemented in c language in a library, improves the bootstrapping execution time of the FHEW scheme to 13 milliseconds. TFHE performs homomorphic processing on a multitude of logic gates. This variety made it possible t

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Paulin, Boale B., Ntumba B. Simon, and Mbuyi MThe fully Homomorphic encryption scheme is corner stone of privacy in an increasingly connected world. It allows to perform all kinds of computations on encrypted data. Although time of computations is bottleneck of numerous applications of real life. In this paper a. brief description is made on the homomorphic encryption scheme TFHE of Illaria Chillota and the others. TFHE implemented in c. language in a. library improves the bootstrapping execution time of the FHEW scheme to 13 milliseconds. TFHE performs homomorphic processing on a. multitude of logic gates. This variety made it possible to construct implement five adder architectures and compare them in terms of the execution time of the bootstrapping per logic gate. In a. singleprocessor computing environment the Carry Look-ahead Adder completed a. two-integer addition in 90 seconds whereas the Ripple carry Adder did the same processing in 109 seconds. An improvement in processing time of 15% is observed. And the same ratio of about 15% was obtained on four integers respectively for 279 seconds for the first adder and 320 seconds for Wallace's dedicated adder. While in the dual-processor environment a. 50% improvement was seen on all adders in the same processing on integers. The Carry Look-ahead Adder saw his handling improved by the sum of two numbers from 90 seconds to 46 seconds and four numbers from 279 seconds to 139 seconds respectively. Keywords: fully Homomorphic encryption bootstrapping logic gate binary adder. Eugene. "Performance of Adder Architectures on Encrypted Integers." International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249-8958 (Online), Volume-10 Issue-6, August 202 10, no. 6 (2021): 216–21. https://doi.org/10.35940/ijeat.F3083.0810621.

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The fully Homomorphic encryption scheme is corner stone of privacy in an increasingly connected world. It allows to perform all kinds of computations on encrypted data. Although, time of computations is bottleneck of numerous applications of real life. In this paper, a brief description is made on the homomorphic encryption scheme TFHE of Illaria Chillota and the others. TFHE, implemented in c language in a library, improves the bootstrapping execution time of the FHEW scheme to 13 milliseconds. TFHE performs homomorphic processing on a multitude of logic gates. This variety made it possible t

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44

Saini, Vikas K., Shamim Akhter, and Tanuj Chauhan. "Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits." VLSI Design 2016 (June 8, 2016): 1–8. http://dx.doi.org/10.1155/2016/1260879.

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Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparativ

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Hussain, Md Zakir, and Kazi Nikhat Parvin. "Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 12, no. 01 (2020): 8–12. http://dx.doi.org/10.18090/samriddhi.v12i01.2.

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This study represents the designing and implementation of a bandpass finite impulse response (FIR) filter of order 31 using windowing techniques. The frequency parameters used are of a typical GSM receiver,19 which is one of the applications of software-defined radio (SDR). To minimize filter area, various multiplication techniques like a canonical signed digit, Vedic multiplier, booth multiplier, and modified booth multiplier are used. Adders like ripple carry adder, carry save adder, carry look ahead adder, and Kogge-Stone adder are used to add the product from the multiplier unit. A compari

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Gurusamy, L., Muhammad Kashif, and Norhuzaimin Julai. "Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library." Applied Mechanics and Materials 833 (April 2016): 149–56. http://dx.doi.org/10.4028/www.scientific.net/amm.833.149.

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This This paper addresses a novel technique in implementing hybrid parallel-prefix adder (HPA) incorporating prefix-tree structure with Carry Select Adder (CSEA). Ling’s algorithm is used to optimise the pre-processing blocks (white nodes) and intermediate Generate-Propagate blocks (Black nodes) of the prefix tree to minimise the congestion of wires which contributes to reduction in chip size and to improve performance. The resulting prefix-tree arrangement is then merged into a sequence of modified CSEA. Experimental results show that HPA has speed improvement of 62% and 13% power reduction i

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M, Siva Kumar. "Low Power Carry Look-Ahead Adder using Transmission Gate Multiplexer." International Journal of Emerging Trends in Engineering Research 8, no. 1 (2020): 13–17. http://dx.doi.org/10.30534/ijeter/2020/03812020.

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Mahmoodi-Meimand, H., A. Afzali-Kusha, and M. Nourani. "Adiabatic carry look-ahead adder with efficient power clock generator." IEE Proceedings - Circuits, Devices and Systems 148, no. 5 (2001): 229. http://dx.doi.org/10.1049/ip-cds:20010439.

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Gil, Sang Keun. "Optical Look-ahead Carry Full-adder Using Dual-rail Coding." Journal of the Optical Society of Korea 9, no. 3 (2005): 111–18. http://dx.doi.org/10.3807/josk.2005.9.3.111.

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HU, ZHENGHAO. "Variants of an improved m-valued carry look-ahead adder." International Journal of Electronics 71, no. 5 (1991): 799–803. http://dx.doi.org/10.1080/00207219108925522.

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