Relevant bibliographies by topics / Carry look-ahead (CLA) adders

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Academic literature on the topic 'Carry look-ahead (CLA) adders'

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Published: 2 June 2025
Last updated: 22 June 2025

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Journal articles on the topic "Carry look-ahead (CLA) adders"

1

Balasubramanian, Padmanabhan, and Nikos E. Mastorakis. "High-Speed and Energy-Efficient Carry Look-Ahead Adder." Journal of Low Power Electronics and Applications 12, no. 3 (2022): 46. http://dx.doi.org/10.3390/jlpea12030046.

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The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.
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Dr., Anuradha M. Sandi. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2019): 40–50. https://doi.org/10.5281/zenodo.3245207.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increase in hard & fast circuits, delay also increases simultaneously. That’s the reason these Carry look ahead adders (CLA) are used. The carry look ahead adder speeds up the addition by reducing the amount of time required to determine carry bits. It uses two blocks, carry generator (Gi) and carry propagator (Pi) which finds the carry bit in advance for each bit position from the nearest LSB, if the carry is 1 then that position is going to propagate a carry to next adder.
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Kamaraju, M., P. Ashok Babu, P. Himasri, and S. Akshitha. "Power and Area Efficient Four-Bit Vedic Multiplier Implemented Using a Modified Five-Bit Adder with CMOS and TG Configuration." Journal of Controller and Converters 9, no. 1 (2024): 27–36. http://dx.doi.org/10.46610/jcc.2024.v090i01.005.

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Vedic multipliers are incredibly fast, efficient, and flexible, perfect for efficiently handling tasks like signal processing. Vedic multipliers are the go-to choice for maximizing performance and efficiency in digital designs, as the existing method adders like Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA) have more delay, area and power. The project proposal presents a novel 4-bit Vedic multiplier essential to system functionality. Optimizing the balancing area and delay is necessary for improving the system as a whole. This project aims to strike this balance, significantly improving the performance of digital systems. Here, a 5-bit adder with a unique configuration is used in place of a Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA). Using CMOS & TG Configuration, all other internal structures have been created. Performance comparisons of the CMOS and TG 5-bit Adders with the adders above are shown in terms of power, latency, and area. Various adders: 5-bit Adder with CMOS & TG design, the CMOS & TG based CLA, the CSA, and the RCA, are also involved in the multiplier's adder unit selection process. The new multiplier provides the perfect answer for energy-efficient designs by combining low power consumption with small size.
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Hari Kishore, K., B. K. V.Prasad, Y. Manoj Sai Teja, D. Akhila, K. Nikhil Sai, and P. Sravan Kumar. "Design and comparative analysis of inexact speculative adder and multiplier." International Journal of Engineering & Technology 7, no. 2.8 (2018): 413. http://dx.doi.org/10.14419/ijet.v7i2.8.10472.

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A Carry look ahead adder is a sort of the summer used in the logic design of the digital systems. The CLA boost up the speed by decreasing the measure of duration needed to calculate the carry bits. The CLA based outline of the inexact speculative adder is pipelined architecture to incorporate couple of logic paths along its basic way and in this manner, improving the recurrence of operation. This paper presents the comparative analysis of the pipelined inexact speculative adder and the general carry look ahead adder and showed that the delay is reduced to 48.27% when compared to carry look ahead adder and also we have designed the pipelined multiplier using the Inexact speculative adders and observed that the delay is reduced to 48.32% when compared to the normal multiplier. This entail Xilinx ISE Design Suite 14.5 Tool.
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Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increase in hard & fast circuits, delay also increases simultaneously. That’s the reason these Carry look ahead adders (CLA) are used. The carry look ahead adder speeds up the addition by reducing the amount of time required to determine carry bits. It uses two blocks, carry generator (Gi) and carry propagator (Pi) which finds the carry bit in advance for each bit position from the nearest LSB, if the carry is 1 then that position is going to propagate a carry to next adder.
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Ziouzios, Dimitris, Dimitris Tsiktsiris, Nikolaos Baras, Stamatia Bibi, and Minas Dasygenis. "A generator tool for Carry Look-ahead Adders (CLA)." SHS Web of Conferences 102 (2021): 04021. http://dx.doi.org/10.1051/shsconf/202110204021.

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A carry look-ahead adder (CLA) is a digital circuit which is used widely used in any electronic computational device to improve speed calculation by reducing the time required to define carry bits. Despite the fact that CLA is used massively in modern digital systems, there is no online tool to automatically generate the HDL description. For this reason we developed a cloud based tool to automate the design of optimized CLA and provide custom testbenches to verify their correctness for singed and unsigned numbers. It is also can be used by the students to create and understand deeply the way CLA works.
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Balasubramanian, Padmanabhan, and Weichen Liu. "High-speed and energy-efficient asynchronous carry look-ahead adder." PLOS ONE 18, no. 10 (2023): e0289569. http://dx.doi.org/10.1371/journal.pone.0289569.

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Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm CMOS process technology. The proposed BCLA has a slight edge over the proposed SCLA, and the proposed BCLA reports the following optimizations in design metrics such as cycle time (delay), area, and power compared to a recently presented state-of-the-art asynchronous CLA for a 32-bit addition: (i) 32.6% reduction in cycle time, 29% reduction in area, 4.3% reduction in power, and 35.5% reduction in energy for RZH, and (ii) 31.4% reduction in cycle time, 28.9% reduction in area, 4.4% reduction in power, and 34.4% reduction in energy for ROH. Also, the proposed BCLA reports reductions in cycle time and power/energy compared to many other asynchronous adders.
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Saini, Vikas K., Shamim Akhter, and Tanuj Chauhan. "Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits." VLSI Design 2016 (June 8, 2016): 1–8. http://dx.doi.org/10.1155/2016/1260879.

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Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparative analysis of different types of adders in Synopsis Design Compiler using different standard cell libraries at 32/28 nm. Also, the designs are analyzed for the stuck at faults (s-a-0, s-a-1) using Synopsis TetraMAX.
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S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster speed. Concurrently, Look Ahead Adders are strategically deployed in the initial stages of the enhanced adder to capitalize on their computational prowess, particularly beneficial for smaller bit numbers. A 64-bit hybrid CSLA is realized on the Xilinx Spartan 6 FPGA development board. The resultant modified hybrid carry select adder demonstrates notable improvements in speed and energy efficiency, surpassing conventional carry select adder implementations.</em>
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Rout, Shasanka Sekhar, Rajesh Kumar Patjoshi, Sarmila Garnaik, and Ranjita Rout. "Comparative Analysis of Heterogeneous Adders: Evaluating Performance across 12-bit, 14-bit, and 16-bit Configurations." Journal of Information Assurance and Security 19, no. 4 (2024): 136–45. https://doi.org/10.2478/ias-2024-0010.

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Abstract Digital Signal Processing (DSP) heavily relies on repetitive addition and multiplication operations, making adders a crucial component in DSP systems. Likewise, in processor design, an efficient adder circuit is essential for optimizing compactness, achieving high speed, and minimizing power consumption, particularly when utilizing Xilinx technology. This study delves into the exploration and design of an effective adder architecture by examining various parallel, synchronous adders and proposing a novel combination. The presented research introduces heterogeneous adders composed of concatenated homogeneous sub-adders such as Ripple Carry Adder (RCA) and Carry Look Ahead Adder (CLA), which is implemented by using VIVADO 2017.1. The comprehensive assessment involves simulation, synthesis, and Register-Transfer Level (RTL) implementation to generate utilization and power reports. Specifically, this paper focuses on the design of 12-bit, 14-bit, and 16-bit heterogeneous adders. Through a thorough analysis, power consumption and area utilization are scrutinized and compared across each model. The combination of 4-bit RCA + 8-bit CLA, 10-bit RCA + 4-bit CLA, and 4-bit RCA + 12-bit CLA provide the least total on-chip power consumption of 8.141 W, 9.482 W, and 10.827 W in 12-bit, 14-bit and 16-bit heterogeneous adders respectively. Similarly, 6-bit RCA + 6-bit CLA, 6-bit RCA + 8-bit CLA, and 6-bit RCA + 10-bit CLA provides less area utilization. The goal is to identify the model exhibiting the least power consumption and optimal area utilization, contributing to the advancement of efficient adder circuits for DSP systems and processor designs.
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Dissertations / Theses on the topic "Carry look-ahead (CLA) adders"

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Wei, Lan. "Implementation of Pipelined Bit-parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1943.

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<p>Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis. The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.</p>
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Γιαννοπούλου, Λεμονιά. "Σχεδίαση παράλληλης διάταξης επεξεργαστών σε ένα chip : δημιουργία και μελέτη high radix RNS αθροιστή". Thesis, 2012. http://hdl.handle.net/10889/6136.

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Η άθροιση μεγάλων αριθμών είναι μια χρονοβόρα και ενεργοβόρα διαδικασία. Πολλές μέθοδοι έχουν αναπτυχθεί για να μειωθεί η καθυστέρηση υπολογισμού του αθροίσματος λόγω της μετάδοσης κρατουμένου. Τέτοιες είναι η πρόβλεψη κρατουμένου (carry look ahead) και η επιλογή κρατουμένου (carry select). Αυτές οι αρχιτεκτονικές δεν είναι επαρκώς επεκτάσιμες για μεγάλους αριθμούς (με πολλά bits) ή πολλούς αριθμούς, διότι παράγονται μεγάλα και ενεργοβόρα κυκλώματα. Στην παρούσα εργασία μελετάται η μέθοδος υπολοίπου (RNS), η οποία χρησιμοποιεί συστήματα αριθμών μεγαλύτερα από το δυαδικό. Ορίζεται μια βάση τριών αριθμών και οι αριθμοί αναπαρίστανται στα εκάστοτε τρία συστήματα της βάσης. Η άθροιση γίνεται παράλληλα σε κάθε σύστημα και τέλος οι αριθμοί μετατρέπονται πάλι στο δυαδικό. Τα πλεονεκτήματα αυτής της προσέγγισης είναι η παραλληλία και η απουσία μεγάλων κυκλωμάτων διάδοσης κρατουμένου. Το μειονέκτημα είναι ότι χρειάζονται κυκλώματα μετατροπής από και προς το δυαδικό σύστημα. Αυτού του είδους οι αθροιστές συγκρίνονται για κατανάλωση ενέργειας με τους γνωστούς carry look ahead και carry select. Διαπιστώθηκε ότι οι RNS αθροιστές καταναλώνουν λιγότερη ενέργεια.<br>The addition of many-bits numbers is a time and power consuming task. Many methods are developed to reduce the sum calculation delay due to carry propagation. Such techniques are Carry Look Ahead and Carry Select, Those techniques are not scalable to many bits numbers or a set of many numbers: the circuits needed are big and power consuming. In this thesis, the the RNS technique is investigated. This technique uses radix bigger than binary. A 3-numbers base is defined and the numbers that participate in the sum are represented uniquely in each element radix. The addition is performed in parallel in each radix. Finally the result is transformed back to the binary numbers system. The advantages of this technique are the parallelization of the process and the lack of carry propagation circuits. The disadvantage is that transformation circuits are need from/to binary system. The RNS adders are compared to CLA and CS for power. Such adders are compared to CLA and CS for power consumption. It is found that RNS adders consume less energy.
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Book chapters on the topic "Carry look-ahead (CLA) adders"

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Blotti, Antonio, Maurizio Castellucci, and Roberto Saletti. "Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45716-x_13.

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Kumar, Vinay, Chandan Kumar Jha, Gaurav Thapa, and Anup Dandapat. "Design of Low Power and High Speed Carry Look Ahead Adder (CLAA) Based on Hybrid CMOS Logic Style." In Lecture Notes in Electrical Engineering. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2728-1_61.

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Sowmya, K. B., Chandana, and M. D. Anjana. "The Vedic Design-Carry Look Ahead (VD-CLA): A Smart and Hardware-Friendly Implementation of the FIR Filter for ECG Signal Denoising." In Advances in Multidisciplinary Medical Technologies ─ Engineering, Modeling and Findings. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-57552-6_12.

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Sivasaravanababu, S., T. R. Dineshkumar, and G. Saravana Kumar. "Assertion Driven Modified Booth Encoding and Post Computation Model for Speed MAC Applications." In Recent Trends in Intensive Computing. IOS Press, 2021. http://dx.doi.org/10.3233/apc210289.

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The Multiply-Accumulate Unit (MAC) is the core computational block in many DSP and wireless application but comes with more complicated architectures. Moreover the MAC block also decides the energy consumption and the performance of the overall design; due to its lies in the maximal path delay critical propagation. Developing high performance and energy optimized MAC core is essential to optimized DSP core. In this work, a high speed and low power signed booth radix enabled MAC Unit is proposed with highly configurable assertion driven modified booth algorithm (AD-MBE). The proposed booth core is based on core optimized booth radix-4 with hierarchical partial product accumulation design and associated path delay optimization and computational complexity reduction. Here all booth generated partial products are added as post summation adder network which consists of carry select adder (CSA) &amp; carry look ahead (CLA) sequentially which narrow down the energy and computational complexity. Here increasing the operating frequency is achieved by accumulating encoding bits of each of the input operand into assertion unit before generating end results instead of going through the entire partial product accumulation. The FPGA implementation of the proposed signed asserted booth radix-4 based MAC shows significant complexity reduction with improved system performance as compared to the conventional booth unit and conventional array multiplier.
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Conference papers on the topic "Carry look-ahead (CLA) adders"

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Barman, Jayeeta, and Vinay Kumar. "Approximate Carry Look Ahead Adder (CLA)for Error Tolerant Applications." In 2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI). IEEE, 2018. http://dx.doi.org/10.1109/icoei.2018.8553739.

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Kostrzewski, Andrew, Dai Kyun Kim, Yao Li, and George Eichmann. "An optical-carry, look-ahead adder based on a content-addressable memory." In OSA Annual Meeting. Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.tuuu4.

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We will discuss a new optical parallel- arithmetic processing scheme that uses a nonholographic optoelectronic content-addressable memory (CAM). To increase the processing speed, a carry look-ahead addition (CLA) scheme can be used. We will also present the design of a 4-bit CAM-based optical-carry look-ahead adder, as well as our experimental results.
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Eichmann, George, Andrew Koslrzewski, Dai Hyun Kim, and Yao Li. "Optical higher-order symbolic recognition." In OSA Annual Meeting. Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.tuuu8.

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We will discuss a new optical parallel-arithmetic processing scheme that uses a nonholographic optoelectronic content-addressable memory (CAM). To increase the processing speed, a carry look-ahead addition (CLA) scheme can be used. We will also present the design of a 4-bit CAM-based optical-carry look-ahead adder, as well as our experimental results.
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Kalyani Garimella, Lalitha M., Sri R. Sudha Garimella, Kevin Duda, and Eric Fetzer. "New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A." In 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2013. http://dx.doi.org/10.1109/mwscas.2013.6674915.

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Preethi, K., and P. Balasubramanian. "FPGA implementation of synchronous section-carry based carry look-ahead adders." In 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS). IEEE, 2014. http://dx.doi.org/10.1109/icdcsyst.2014.6926150.

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Islam, Md Saiful, Muhammad Mahbubur Rahman, Zerina Begum, and Mohd Zulfiquar Hafiz. "Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders." In 2009 International Conference on Advances in Computational Tools for Engineering Applications (ACTEA). IEEE, 2009. http://dx.doi.org/10.1109/actea.2009.5227871.

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Voyiatzis, I., and C. Efstathiou. "SIC pair generation in near-optimal time with carry-look ahead adders." In 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS). IEEE, 2018. http://dx.doi.org/10.1109/dtis.2018.8368573.

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V, Gayatri, Amirtha T, and S. Padmapriya. "Optimized Vedic Multiplier $\mathrm{N}^{\ast}\mathrm{N}$ using Adder Approximations and Modified Carry Look Ahead Adders." In 2024 International Conference on Science Technology Engineering and Management (ICSTEM). IEEE, 2024. http://dx.doi.org/10.1109/icstem61137.2024.10561072.

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