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Journal articles on the topic 'Carry Select Adder (CSA)'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

Hossain, Muhammad Saddam, and Farhadur Arifin. "Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder." AIUB Journal of Science and Engineering (AJSE) 20, no. 2 (2021): 1–7. http://dx.doi.org/10.53799/ajse.v20i2.119.

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Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed

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2

A., Mounika, and Srinivasa Reddy K. "Designing and Performance Evaluation of Carry Select Adder." International Journal of VLSI System Design and Communication systems 3, no. 5 (2015): 0754–57. https://doi.org/10.5281/zenodo.48670.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSA) is one of the fastest adder in processor architectures. This paper presents a modified carry select adder(CSA) that operates at low power and proves more area and delay efficient. Validation of the logic is done through extensive simulations for measuring the power and delay. Simple and efficient gate level modification is used in order to reduce the area, delay and power of CSA.The result analysis shows that the proposed structure(CSA CBL) is better tha

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3

Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." International Daily journal, Discovery Publication 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.32686.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each

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Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." Discovery The International Daily journal 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.33104.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design.High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each s

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5

Maroju, SaiKumar, and P. Samundiswary Dr. "Design and Performance Analysis of Various Adders using Verilog." International Journal of Computer Science and Mobile Computing 2, no. 9 (2013): 128–38. https://doi.org/10.5281/zenodo.32564.

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Adders are one of the most widely digital components in the digital integrated circuit design and are the necessary part of Digital Signal Processing (DSP) applications. With the advances in technology, researchers have tried and are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper, the design of various adders such as Ripple Carry Adder (RCA), Carry Skip Adder (CSkA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLaA), Carry Save Adder (CSA), Carry Select Adder (CSlA), Carry Bypass Add

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6

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Design of Low Power, Area-Efficient Carry Select Adder." International Journal of Engineering Research & Technology 2, no. 10 (2013): 3582–86. https://doi.org/10.5281/zenodo.32569.

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Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is des

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7

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Design of Low Power, Area-Efficient Carry Select Adder." International Journal of Engineering Research & Technology 2, no. 10 (2013): 3582–86. https://doi.org/10.5281/zenodo.33081.

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Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is des

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8

Swetha, Tarigoppula, Sravan K. Vittapu, Ravichand Sankuru, Balla Hindupriya, Bairagoni Anand, and Gangadi Chandra Vardhan Reddy. "Implementation of Area Efficient Carry Select Adder using Binary to Excess1 Code." Journal of VLSI Design and Signal Processing 9, no. 3 (2023): 29–36. http://dx.doi.org/10.46610/jovdsp.2023.v09i03.004.

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Adders are widely used as essential parts in the design of digital integrated circuits. The Carry Select Adder (CSA) is unique among conventional adder topologies in that it operates quickly. There is a need for speedier arithmetic units as well as ones that use less power and take up less space as the mobile sector grows quickly. The Carry-Select method for adder design with carry propagation achieves a good trade-off between performance and cost. However, because it uses two ripple carry adders (RCA), the traditional CSA design still has a significant area overhead. A Binary to Excess-1 code

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9

Priyanka, Sharma* K. Srinivasarao. "DESIGN AND IMPLEMENTATION OF CARRY SELECT ADDER USING KOGGE-STONE TECHNIQUE." International Journal OF Engineering Sciences & Management Research 3, no. 6 (2016): 62–69. https://doi.org/10.5281/zenodo.55861.

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In VLSI System design digital adder with optimum power is one of the important area of research. For many data processing purpose CSA perform fast air thematic function. So, it is clear that there is need to reduce the power consumption in CSA. This paper discusses about to reduce the power dissipation in CSA for many applications. For reduction purpose we use one of the most important approaches, which are Kogge –stone configuration. The proposed design with Kogge-stone adder CSA has reduced power dissipation compared with CMOS technology CSA. The simulation performed using SPICE circui

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10

Shanigarapu, Chaithanya, and M.Srujana. "Designing and Comparative Analyses of Carry Select Adders (CSL, CSL with BEC, CSL with CBL)." International Journal of Multidisciplinary Education Research 4, no. 7(2) (2015): 101–5. https://doi.org/10.5281/zenodo.33099.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSA) is one of the fastest adders used in many data - processing processors. The structure of CSA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSA. The result analysis shows that the proposed structure(csa CBL) is better than the conventional CSA and CSA with BEC.

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11

Balasubramanian, Padmanabhan, and Nikos E. Mastorakis. "High-Speed and Energy-Efficient Carry Look-Ahead Adder." Journal of Low Power Electronics and Applications 12, no. 3 (2022): 46. http://dx.doi.org/10.3390/jlpea12030046.

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The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry t

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12

Ponnusamy, Anitha, and Palaniappan Ramanathan. "Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop." Applied Mechanics and Materials 573 (June 2014): 187–93. http://dx.doi.org/10.4028/www.scientific.net/amm.573.187.

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The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. Th

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13

Saini, Vikas K., Shamim Akhter, and Tanuj Chauhan. "Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits." VLSI Design 2016 (June 8, 2016): 1–8. http://dx.doi.org/10.1155/2016/1260879.

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Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparativ

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14

Sathyanarayan, Pavitha Uppinakere, Mamtha Mohan, Sandeep Kakde, and Annam Karhik. "Efficient carry select 16-bit square root adder with complementary metal-oxide semiconductor implementation." Indonesian Journal of Electrical Engineering and Computer Science 26, no. 1 (2022): 172–83. https://doi.org/10.11591/ijeecs.v26.i1.pp172-183.

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The adder is the maximum usually used mathematics block in programs inclusive of central processing unit (CPU) and virtual sign processing. As a result, it is important to expand a space-saving, low-strength, high-overall performance adder circuit. The hassle is diagnosed to layout mathematics sub structures with minimized strength dissipation, low area, and minimal time postpone of common-sense circuits. In conventional carry select adder (CSA), the time required to generate the sum output is less than other basic adder circuits but the principal difficulty is the location because the variety

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Sathyanarayan, Pavitha Uppinakere, Mamtha Mohan, Sandeep Kakde, and Annam Karthik. "Efficient carry select 16-bit square root adder with complementary metal-oxide semiconductor implementation." Indonesian Journal of Electrical Engineering and Computer Science 26, no. 1 (2022): 172. http://dx.doi.org/10.11591/ijeecs.v26.i1.pp172-183.

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The adder is the maximum usually used mathematics block in programs inclusive of <span lang="EN-US">central processing unit (CPU) and virtual sign processing. As a result, it is important to expand a space-saving, low-strength, high-overall performance adder circuit. The hassle is diagnosed to layout mathematics sub structures with minimized strength dissipation, low area, and minimal time postpone of common-sense circuits. In conventional <a name="_Hlk95894088"></a>carry select adder (CSA), the time required to generate the sum output is less than other basic adder circuits

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16

S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster spee

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17

B Gowda, Ranjith, and R. M Banakar. "Design of high speed low power optimized square root BK adder." International Journal of Engineering & Technology 7, no. 2.12 (2018): 240. http://dx.doi.org/10.14419/ijet.v7i2.12.11289.

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Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these t

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18

Balasubramanian, Padmanabhan, and Nikos Mastorakis. "Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions." Electronics 7, no. 12 (2018): 369. http://dx.doi.org/10.3390/electronics7120369.

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Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing bi

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19

Mohsin, Syed, Rahul J. Gowda, Asha CN, and Sumalatha S. "Physical Design of 64-bit Multiplier and Accumulator (MAC) Unit Using Vedic Multiplier and CLA Adder." Journal of Electrical Engineering and Electronics Design 1, no. 1 (2023): 5–9. http://dx.doi.org/10.48001/joeeed.2023.115-9.

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In digital signal processing, communication systems and many other applications, multiplier and accumulator units play a crucial role. This work presents an overview of 64-bit MAC Unit, where Vedic multiplier is used as multiplier unit and compared Carry select adders (CSA) and Carry look-ahead adder (CLA) which must be used for adder unit, accumulator unit consist of Parallel in parallel out (PIPO) shift registers. As a result, CLA adder to be more effective in terms of lower delay by comparing with other adders. The MAC Unit was modelled using Verilog-HDL, where its functional verification a

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20

Venkata Sudhakar, Chowdam, Suresh Babu Potladurty, and Prasad Reddy Karipireddy. "Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 2 (2025): 398. https://doi.org/10.11591/ijres.v14.i2.pp398-411.

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<p>The multiplier is an essential component in real-time applications. Even though approximation arithmetic affects output accuracy in multipliers, it offers a realistic avenue to constructing power area and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this paper, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HA) and full adders (A-FA), which are strategically placed to add partial products at the most significant b

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Suguna, T., and M. Janaki Rani. "Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications." International Journal of Interactive Mobile Technologies (iJIM) 14, no. 05 (2020): 73. http://dx.doi.org/10.3991/ijim.v14i05.13343.

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In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL

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Ravichandran, S., M. Umamaheswari, and R. Benjohnson. "Design and Development of Revolve Rescheduling Technique for Hash Event Blake Overshadowing Carry Select Adder thru Binary to Excess Converter." Asian Journal of Computer Science and Technology 5, no. 2 (2016): 5–12. http://dx.doi.org/10.51983/ajcst-2016.5.2.1771.

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Cryptographic hash events remain consumed broadly appearing in numerous concentrations mostly for the situation high-pitched hustle then safety. NIST prepared SHA- 3 struggle then the last ring-shaped contestants are BLAKE, KECCAK, SKEIN, JH THEN GROSTL. Amongst the five contestants enterprise besides planning of BLAKE remains evaluated in this manuscript. Hash event BLAKE remains the single-way cryptography which requires no key is consumed though referring and getting the communication. Inside the area of cryptography swiftness and privacy are the transactions. To achieve excessive swiftness

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23

Cheng, Wei, and jianping Hu. "A Structured Approach for Optimizing 4-Bit Carry-Lookahead Adder." Open Electrical & Electronic Engineering Journal 8, no. 1 (2014): 133–42. http://dx.doi.org/10.2174/1874129001408010133.

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This paper presents a comparative research of low-power and high-speed 4-bit full adder circuits. The representative adders used are a ripple carry adder (RCA) and a carry-lookahead adder (CLA). We also design a proposed carrylookahead adder (PCLA) using a new method that uses NAND gate for modification which helps in reducing the powerdelay product (PDP) for high performance applications. To yield more realistic rise and fall times in the simulations, layouts have been made in a 0.13 􀀁m process for the RCA circuit, CLA circuit and PCLA circuit. The layouts designed were simulated by HSPICE ba

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Shikha, Singh, and B. Shukla Yagnesh. "Implementation of FinFET technology based low power 4×4 Wallace tree multiplier using hybrid full adder." TELKOMNIKA 21, no. 05 (2023): 1139–46. https://doi.org/10.12928/telkomnika.v21i5.24304.

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Many systems, including digital signal processors, finite impulse response (FIR) filters, application-specific integrated circuits, and microprocessors, use multipliers. The demand for low power multipliers is gradually rising day by day in the current technological trend. In this study, we describe a 4×4 Wallace multiplier based on a carry select adder (CSA) that uses less power and has a better power delay product than existing multipliers. HSPICE tool at 16 nm technology is used to simulate the results. In comparison to the traditional CSA-based multiplier, which has a power consumpti

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SENTHILPARI, C., K. DIWAKAR, and AJAY KUMAR SINGH. "LOW POWER, LOW LATENCY, HIGH THROUGHPUT 16-BIT CSA ADDER USING NONCLOCKED PASS-TRANSISTOR LOGIC." Journal of Circuits, Systems and Computers 18, no. 03 (2009): 581–96. http://dx.doi.org/10.1142/s0218126609005277.

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As the CMOS technology continues to scale to achieve higher performance, power dissipation and robustness to leakage and, process variations are becoming major obstacles for circuit design in the nanoscale technologies. Due to increased density of transistors in integrated circuits and higher frequencies of operation, power consumption, propagation delay, PDP, and area is reaching the lower limits. We have designed 16-bit adder circuit by Carry-Select Adder (CSA) using different pass-transistor logic. The adder cells are designed by DSCH3 CAD tools and layout are generated by Microwind 3 VLSI

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Gurusamy, L., Muhammad Kashif, and Norhuzaimin Julai. "Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library." Applied Mechanics and Materials 833 (April 2016): 149–56. http://dx.doi.org/10.4028/www.scientific.net/amm.833.149.

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This This paper addresses a novel technique in implementing hybrid parallel-prefix adder (HPA) incorporating prefix-tree structure with Carry Select Adder (CSEA). Ling’s algorithm is used to optimise the pre-processing blocks (white nodes) and intermediate Generate-Propagate blocks (Black nodes) of the prefix tree to minimise the congestion of wires which contributes to reduction in chip size and to improve performance. The resulting prefix-tree arrangement is then merged into a sequence of modified CSEA. Experimental results show that HPA has speed improvement of 62% and 13% power reduction i

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Chandrasekharan, Raji, and Sarappadi Narasimha Prasad. "Fault tolerant design for 8-bit Dadda multiplier for neural network applications." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 3 (2025): 2697. https://doi.org/10.11591/ijece.v15i3.pp2697-2705.

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As digital electronic systems continue to shrink in size, they face increased susceptibility to transient errors, especially in critical applications like neural networks, which are not inherently error-resilient. Multipliers, fundamental components of neural networks, must be both fault tolerant and efficient. However, traditional fault free designs consume excessive power and require substantial silicon real estate. Among existing multiplier architectures, the Dadda multiplier stands out for its speed and efficiency, but it lacks fault tolerance needed for robust neural network applications.

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N B V V S S Mani Manjari and Dr. S V R K RAO. "High Throughput DWT Architecture for Signal Processing." International Journal of Scientific Research in Science and Technology 11, no. 4 (2024): 79–88. http://dx.doi.org/10.32628/ijsrst24114109.

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The Discrete Wavelet Transform (DWT) is essential in signal processing systems because it is capable of accurately recording both frequency and time-domain features. Nevertheless, the computational intricacy of DWT presents notable obstacles to processing in real-time, particularly in circumstances with large data consumption. This study presents a VLSI technology designed to accelerate DWT processing utilizing CMOS gates. The goal is to improve throughput while maintaining area efficiency. The architecture utilizes parallelism and pipelining techniques to take use of the fundamental redundanc

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Hameed, Ahmed Salah, and Marwa Jawad Kathem. "High speed modified carry save adder using a structure of multiplexers." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 1591. http://dx.doi.org/10.11591/ijece.v11i2.pp1591-1598.

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Adders are the heart of data path circuits for any processor in digital computer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. In this paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed in designing all stages of traditional CSA. By modifying the design of full adder in CSA, the complexity and area of the design can be reduced, resulting in reduc

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Kamaraju, M., P. Ashok Babu, P. Himasri, and S. Akshitha. "Power and Area Efficient Four-Bit Vedic Multiplier Implemented Using a Modified Five-Bit Adder with CMOS and TG Configuration." Journal of Controller and Converters 9, no. 1 (2024): 27–36. http://dx.doi.org/10.46610/jcc.2024.v090i01.005.

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Vedic multipliers are incredibly fast, efficient, and flexible, perfect for efficiently handling tasks like signal processing. Vedic multipliers are the go-to choice for maximizing performance and efficiency in digital designs, as the existing method adders like Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA) have more delay, area and power. The project proposal presents a novel 4-bit Vedic multiplier essential to system functionality. Optimizing the balancing area and delay is necessary for improving the system as a whole. This project aims to strike this

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Chang, T. Y., and M. J. Hsiao. "Carry-select adder using single ripple-carry adder." Electronics Letters 34, no. 22 (1998): 2101. http://dx.doi.org/10.1049/el:19981706.

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Ahmed, Salah Hameed, and Jawad Kathem Marwa. "High speed modified carry save adder using a structure of multiplexers." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 1591–98. https://doi.org/10.11591/ijece.v11i2.pp1591-1598.

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Adders are the heart of data path circuits for any processor in digitalcomputer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. Inthis paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed indesigning all stages of traditional CSA. By modifying the design of full adderin CSA, the complexity and area of the design can be reduced, resulting inreduced de

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Aritra, Mitra, Bakshi Amit, Sharma Bhavesh, and Didwania Nilesh. "Design of a High Speed Adder." International Journal of Scientific & Engineering Research 6, no. 4 (2015): 918–21. https://doi.org/10.5281/zenodo.33243.

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In this paper we have compared different addition algorithms such as Ripple Carry Adder, Carry Save Adder, Carry Select Adder, Carry Look Ahead Adder & Kogge Stone Adder for different performance parameters i.e. Area Utilization, Speed of operation and Power Consumption. A high speed Adder is then designed by merging Kogge Stone & Carry Select Algorithms. The circuits have been designed using Verilog HDL & Synthesize using TSMC 180 nm standard cell. The performance parameters are obtained with the help of Cadence Encounter RTL Compiler.

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Kokilavani, V., K. Preethi, and P. Balasubramanian. "FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders." Advances in Electronics 2015 (May 27, 2015): 1–13. http://dx.doi.org/10.1155/2015/713843.

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Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work,

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E.Kumar, M.Surekha, B.Jagadeesh, P.Venkata Sai Ramakrishna, N.V.S.S Sujith, and B.Manjunadha. "Design and Implementation of Area Efficient 16-bit Carry Skip Adder." international journal of engineering technology and management sciences 7, no. 2 (2023): 339–44. http://dx.doi.org/10.46647/ijetms.2023.v07i02.041.

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Adders are fundamental unit in many computer systems. One of the most efficient adder architectures in terms of delay and area is the carry-skip adder. In this paper an area efficient 16-bit carry-skip adder to achieve high speed and low area were designed. CSA is a rapid adder that is used in data processing systems to execute quick arithmetic operations. As a result, a Modified Carry Skip Adder (MCSA) is developed using a single Ripple Carry Adder (RCA) and a Binary to Excess-1 Converter (BEC) instead of twin RCAs to save size while sacrificing speed. The design is coded in VHDL and its area

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Bobba, Ramyabanu, and Pooja Illa. "XOR Based Carry Select Adder for Area and Delay." International Journal of Innovative Science and Research Technology 5, no. 6 (2020): 1615–21. http://dx.doi.org/10.38124/ijisrt20jun1117.

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Low power and area proficient high-speed circuits are the most important areas in VLSI design research. Carry select adder is one of the fastest adders with the low area and power consumption. The paper introduces a 16-bit carry select adder with an optimized multiplexer based full adder circuit using Gate Diffusion Input logic (GDI) technology. Comparison is done on Area, Power and Delay parameters. Our circuit requires only two XOR gates and a multiplexer. In this, each logic gate is designed using GDI technology. This further reduces the transistor count resulting in Area, power, delay and

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Keerthan, Chilagani, and Bathini Trinay. "High-Speed Area-Efficient VLSI Architecture of Three Operand Binary Adder." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 04 (2025): 1–9. https://doi.org/10.55041/ijsrem44578.

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This paper proposes a novel high-speed three-operand binary adder architecture, namely the Han-Carlson adder, which mitigates the inherent limitations of traditional Carry Save Adders (CSAs). The CSA's drawbacks, including slow carry propagation and increased power consumption, are alleviated by the Han-Carlson adder's innovative prefix computation and carry lookahead architecture.The Han-Carlson adder's design exploits the benefits of prefix computation to generate the carry signals in parallel, thereby reducing the critical path delay. Furthermore, the carry lookahead mechanism enables the a

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Lavanya, P., B. Chinna Rao, and T. Vishnu Murty. "High Efficient Carry Select Adder using Zero Carry Look Ahead Adder." International Journal of Engineering Trends and Technology 18, no. 1 (2014): 42–46. http://dx.doi.org/10.14445/22315381/ijett-v18p208.

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K, P. Heena. "A Comparative Study on Ripple Carry Adder and Modified Square Root Carry Select Adder in Radix-4 8*8 Booth Multiplier." International Journal of Innovative Science and Research Technology (IJISRT) 9, no. 2 (2024): 4. https://doi.org/10.5281/zenodo.10784386.

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In digital circuits multiplication is a fundamental operation, extensively utilized in various computational tasks. The efficiency and performance of the multiplier circuit significantly impact the overall system performances, especially in applications demanding high-speed computation with minimal power consumption. This study presents a comparative analysis between two distinct implementations of Radix-4 8*8 Booth multiplier employing different adder architectures: Ripple carry adder and Modified Square Root Carry select adder. Multiplier with modified square root carry select adder reduced

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Swami G, Narayan, Bhuvana D T, Keerthana M R, Ankita B, and Manoja E. "Optimization of Delay and Area for Approximate Radix-8 Booth Multiplier." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–6. https://doi.org/10.55041/ijsrem39405.

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This paper investigates the optimization of Radix-8 Booth Multipliers, which are essential for efficient arithmetic operations in modern digital systems, particularly in applications such as digital signal processing, telecommunications, and image processing where rapid and accurate calculations are crucial. The study aims to enhance performance by focusing on reducing both delay and area while ensuring that acceptable accuracy levels are maintained for error-tolerant applications. To achieve these optimization goals, we compare three methodologies: the Carry Save Adder (CSA), the Kogge Stone

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PinnikaVenkateswarlu and Kalpana Ragutla. "An Efficient SQRT Architecture of Carry Select Adder Design by HA and Common Boolean Logic." SSRG International Journal of Electronics and Communication Engineering 1, no. 8 (2014): 36–41. https://doi.org/10.5281/zenodo.33082.

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As we are aware that carry select adder is the fastest one amongdata processing element, on the other hand due to having pairs of ripple carry adder structure traditional carry select adder consumes more area. So proposed scheme is to developa low power and low area half adder based (CSLA) using simple using common Boolean logic (CBL), where it employs one half adders to perform the summation operation for the common Boolean logic (CBL) and carry zero respectively. Half adder and CBL have to be designed where half adder requires one XOR gate, one AND gate where CBL requires only one NOT as wel

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M. B., Veena, and Shreya S. K. "Implementation of Ripple Carry Adder and Carry Save Adder using 7nm FinFET Technology." WSEAS TRANSACTIONS ON ELECTRONICS 14 (December 31, 2023): 163–69. http://dx.doi.org/10.37394/232017.2023.14.20.

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The semiconductor industry’s continuous effort to miniaturize and be more powerful to increase the overall performance. This has led to the use of FinFET technology for packing more transistors into a smaller space and using power more efficiently compared to planner MOS technologies. Compared to the MOS technology, FinFET technology provides better advantages such as improved transistor performance, lower leakage currents, and enhanced power efficiency. The proposed work includes integrating fundamental components like the NAND gate, 2:1 MUX, and full adder (FA). These components are combined

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You, Yuan, Tang, and Qiao. "An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell." Electronics 8, no. 10 (2019): 1129. http://dx.doi.org/10.3390/electronics8101129.

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In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed C

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Saravanakumar, Saravanakumar, Vijeyakumar Vijeyakumar, and Sakthisudhan Sakthisudhan. "FPGA Implementation of High Speed Hardware Efficient Carry Select Adder." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (2018): 43. http://dx.doi.org/10.11591/ijres.v7.i1.pp43-47.

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This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder ha

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Saravanakumar, Vijeyakumar, and Sakthisudhan. "FPGA Implementation of High Speed Hardware Efficient Carry Select Adder." International Journal of Reconfigurable and Embedded Systems 7, no. 1 (2018): 43–47. https://doi.org/10.11591/ijres.v7.i1.pp43-47.

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This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder (CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA.  The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA a

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Rashmi, B. K., J. Rohith, Suresh Mudaladavar Shreya, Hosageri Supreet, and P. Mattada Mahantesh. "Performance and analysis of different adder topologies." i-manager’s Journal on Electronics Engineering 14, no. 3 (2024): 31. http://dx.doi.org/10.26634/jele.14.3.20675.

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This paper gives an overview of area, power, delay for four different 64-bit adders. The design metrics in VLSI are low area and delay alongside low power designs. Adder is one of the necessary components of almost every kind of digital and high- performance systems such as FIR filters, digital signal processors and microprocessors etc. Different types of adders are carry tree adder, carry save adder, carry look ahead adder and carry select adder. In this work we have designed, simulated and synthesized these adder topologies and compared the results in cadence tool.

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Corsonello, P., S. Perri, and G. Cocorullo. "Hybrid carry-select statistical carry look-ahead adder." Electronics Letters 35, no. 7 (1999): 549. http://dx.doi.org/10.1049/el:19990375.

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Kantabutra, V. "A recursive carry-lookahead/carry-select hybrid adder." IEEE Transactions on Computers 42, no. 12 (1993): 1495–99. http://dx.doi.org/10.1109/12.260639.

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Teoh Yong Keong, Siti Fatimah Abd Rahman, Mohamad Faris Mohamad Fathil, Mohamed Fauzi Packeer Mohamed, Adilah Ayoib, and Thikra S. Dhahi. "High Efficiency Carry Save Adder using Modified–gate Diffusion Input Technique." International Journal of Nanoelectronics and Materials (IJNeaM) 17, June (2024): 53–59. http://dx.doi.org/10.58915/ijneam.v17ijune.835.

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Addition is a fundamental function in the design of a digital system, necessary for applications such as signal processing, arithmetic operations, multiplexers, and control systems. Hence, the digital system’s performance is considerably reliant on the efficiency of the adders. Therefore, designing a 4-bit carry save adder (CSA) that consumes less power, occupies a smaller area, and operates at a higher speed is proposed using the modified–gate diffusion input (MOD–GDI) technique. The primary focus is to reduce the area occupied by decreasing the transistor count as compared with other logic s

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Mr., Vijay V. Gotmare, and Pankaj Agarwal Dr. "Design of High-Speed Hybrid Carry Select Adders using VHDL." Journal of Information, Knowledge and Research in Electronics and Communication, March 1, 2016, 1251–53. https://doi.org/10.5281/zenodo.46809.

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Carry select adder (CSA) is a square-root time high-speed adder. CSA is one of the fastest adders used in many data processing systems to perform fast arithmetic operations. In this project we propose to design hybrid carry select adders with a focus on high speed. CSA is a compromise between the longer delay Ripple carry adder (RCA) and the shorter delay Carry look-ahead adder (CLA). Conventionally carry select adders are realize using the full adders and 2:1 multiplexers. On the other hand hybrid carry select adders involve a combination of carry select and carry look-ahead adders.In this wo

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