Relevant bibliographies by topics / Carry select Adder (CSLA)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Carry select Adder (CSLA)'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "Carry select Adder (CSLA)"

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You, Yuan, Tang, and Qiao. "An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell." Electronics 8, no. 10 (2019): 1129. http://dx.doi.org/10.3390/electronics8101129.

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In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed C
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Dhandapani, Vaithiyanathan. "An efficient architecture for carry select adder." World Journal of Engineering 14, no. 3 (2017): 249–54. http://dx.doi.org/10.1108/wje-08-2016-0043.

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Purpose Adders play a vital role in almost all digital designs, as all four arithmetic operations can be confined within addition. Hence, area and power optimization of the adders will result in overall circuit optimization. Being the fastest adder, the carry select adder (CSLA) gains higher importance among the different adder styles. However, it suffers from the drawback of increased power and area. The implementation of CSLA in digital circuits requires lots of study for optimization. Hence, to overcome this problem, various improvements were made to the CSLA structure to reduce area and, c
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S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster spee
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Anand, B., and V. V. Teresa. "Improved Modified Area Efficient Carry Select Adder (MAE-CSLA) Without Multiplexer." Journal of Computational and Theoretical Nanoscience 14, no. 1 (2017): 269–76. http://dx.doi.org/10.1166/jctn.2017.6316.

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The Carry Select Adder (CSLA) is the fastest adders that perform arithmetic operations in many processors. There are lot of modifications that are proposed to reduce the area of CSLA one such efficient technique is presented in this paper. Here the area is reduced by eliminating the multiplexer that selects the carry in of regular CSLA by using a simple XOR gate. Here the XOR gate is used to generate the first sum output of the ripple carry adders in the second stage of the CSLA adder. Then the XOR gate is implemented with AOI. This AOI implementation will further reduce the area consumption o
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Balasubramanian, Padmanabhan, and Nikos Mastorakis. "Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions." Electronics 7, no. 12 (2018): 369. http://dx.doi.org/10.3390/electronics7120369.

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Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing bi
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BalaSurya, S. Dinesh, Sudalaimani M., S. Kakkum perumal, M. Lakshmana Rajesh, and Dr J. Sam Alaric. "Implementation of Carry Skip Adder using Carry Select Adder with Improved Area, Delay, and Power Efficiency." International Journal of Innovative Research in Information Security 10, no. 03 (2024): 131–41. http://dx.doi.org/10.26562/ijiris.2024.v1003.03.

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This paper presented a Carry Skip Adder (CSKA) structure with less area, less delay, and lower power consumption. This can be achieved with Carry Select Adder's (CSLA) help. The proposed structure uses AND-OR-INVERT (AOI) and OR-AND- INVERT (OAI) compound gates for the skip logic. The use of Carry Select Adder will reduce the number of LUTs used (i.e.) the area of the proposed structure, reduce delay in performing processes, and also reduce power consumption. Simulation of the proposed hybrid CSKA-CSLA structure reveals a reduction in area, delay, and power consumption compared with the CSKA-R
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Saranya, R., B. Paulchamy, K. Kalpana, V. V. Teresa, and P. Logamurthy. "Area-Delay-Power-Efficient GDI Architecture Select Adder to Carry." E3S Web of Conferences 616 (2025): 02005. https://doi.org/10.1051/e3sconf/202561602005.

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The signal processing system is extremely popular in this day and age. All of the primary circuits in the digital signal processing system are built around the adder, which is the fundamental building block. Today’s needs for lowering the delay, space, and power consumption of adder circuits boost the overall efficiency of the system, propelling it to the next stage of technological development. Despite the fact that the Carry Select Adder (CSLA) takes up more space, it is being utilised in place of the ripple carry adder in order to reduce propagation delays. In other models, a Carry Select A
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A., Nithya, G. Priyanka A., Ajitha B., Gracia Nirmala Rani D., and Rajaram S. "FPGA Implementation of Low Power and Area Efficient Carry Select Adder." International Journal of Enhanced Research in Science Technology & Engineering 3, no. 7 (2014): 321–27. https://doi.org/10.5281/zenodo.33237.

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In this paper, we have proposed a modified carry select adder which is known as fastest adders that can perform arithmetic operations in Digital signal processors. Modification in the gate level of the Square root Carry Select Adder (SQRT CSLA) structure results in the reduction of area and power of the CSLA structure which offers a simple and efficient function. Depending upon the Regular SQRT CSLA, we have modified the structure of the adders. The proposed design for 128-bit modified CSLA has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the del
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M, Syed Mustafaa, Sathish M, Nivedha S, Magribatul Noora A K, and Safrin Sifana T. "Design of Carry Select Adder using BEC and Common Boolean Logic." Indian Journal of VLSI Design 1, no. 3 (2022): 5–9. http://dx.doi.org/10.54105/ijvlsid.c1205.031322.

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Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and po
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Syed, Mustafaa M., M. Sathish, S. Nivedha, Magribatul Noora A. K. Mohammed, and Sifana T. Safrin. "Design of Carry Select Adder using BEC and Common Boolean Logic." Indian Journal of VLSI Design (IJVLSID) 1, no. 3 (2022): 5–9. https://doi.org/10.54105/ijvlsid.C1205.031322.

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Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and po
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Dissertations / Theses on the topic "Carry select Adder (CSLA)"

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Meruguboina, Dronacharya. "EFFICIENT DESIGN OF CARRY SELECT ADDER USING DOMINO MANCHESTER CARRY CHAIN." OpenSIUC, 2017. https://opensiuc.lib.siu.edu/theses/2125.

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Significant characteristic of any VLSI design circuit is its power, reliability, operating frequency and implementation cost. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. This thesis describes the design and the optimization of high performance carry select adder. Previous researchers believed that existing CSA designs has reached theoretical speed bound. But, only a considerable portion of hardware resources of traditional adders are used in worst case scenario. Based on this observation our proposed design will
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Wei, Lan. "Implementation of Pipelined Bit-parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1943.

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<p>Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis. The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.</p>
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Allwin, Priscilla Sharon. "A Low-Area, Energy-Efficient 64-Bit Reconfigurable Carry Select Modified Tree-Based Adder for Media Signal Processing." Wright State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1566754181334305.

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Chen, Wei-Cheng, and 陳威誠. "Design of Self-Repair Carry Select Adder." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/18930659095287123901.

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碩士<br>國立勤益科技大學<br>電子工程系<br>99<br>In this paper, the High Reliability and Low Cost Self-Repair (SR) Carry-Select Adder (CSA) design is proposed. The capability of architecture can on-line detect all single stuck-at faults and repair in normal operation mode. In the area, this paper choose a better way to reduce the area. A self-repair CSA constructed by n two-bit modules has merely one backup redundancy with fault diagnosis circuitry. Effectively reduce the number of transistors, and the proposed new circuit to improve the previous literature the problem of fault coverage. The design is based o
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Hsu, Chih Wei, and 徐志維. "Hardware Sharing Near Threshold Voltage Carry Select Adder Circuit Design." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/q78uyy.

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Su, Fong-Jia, and 蘇峰加. "Self-Repair Carry Select Adder Design Based on Two-Rail Code." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/63228400005549086936.

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碩士<br>國立勤益科技大學<br>電子工程系<br>100<br>In the thesis, we propose both totally self-checking and self-repair functions for carry select adder (CSA) design. Based on this architecture, single fault existing in the CSA can be real-time detected and repaired in the normal operation mode. The full adder cores used to design CSA is designed by using complementary pass-transistor logic (CPL). Due to its complementary and symmetric characteristics, CPL is befitted in design of the backup circuit with reduced redundancy to achieve self-repair function for the carry select adder in case of fault occurred. Tw
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Bo-Ruei, Chen, and 陳柏瑞. "Design of Add-One Carry Select Adder with Self-Repair Mechanism." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/66455422583765708186.

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碩士<br>國立勤益科技大學<br>電子工程系<br>100<br>In this thesis, the self-repair (SR) carry-select adder (CSA) design is proposed. The proposed CSA circuit has the capability of on-line totally self-checking (TSC) all single stack-at faults occurred. There are two kinds of TSC circuits proposed, one is based on conventional CSA and the other is based on CSA with add-one circuit. Because of dual backup circuits be arranged in the self-repair mechanism, it has the capability for repairing single or dual faulty function unit. As a result, the proposed self-repair carry-select adder design has higher reliability
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Lee, Ming-En, and 李明恩. "Totally Self-Checking Carry-Select Adder Design Based on Two-Rail Code." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/30393058530093757192.

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碩士<br>國立勤益科技大學<br>電子工程系<br>98<br>In this paper, the Totally Self-Checking (TSC) Carry-Select Adder (CSA) design is proposed. The capability of TSC can on-line detect all single stuck-at faults in normal operation mode. The proposed CSA has not only self-checking capability but also reduced transistor count. The design is based on TSMC 0.18um process technology, and a real chip is implemented. The transistor count of proposed totally self-checking CSA design is less than conventional CSA, and even reduced 34.85% compared with [7] for thirty-two bits design. The reduced ratio of transistor-count
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Liao, Irene M. J., and 廖美貞. "A Carry-Select-Adder Optimization Technique for High-Performance Booth-Encoded Wallace-Tree Multipliers." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/45267729737681347070.

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碩士<br>國立清華大學<br>資訊工程學系<br>89<br>In this thesis, we present two carry-select adder partitioning algorithms for high-performance Booth-encoded Wallace-tree multipliers. By taking various data arrival times into account, we propose a branch-and-bound algorithm and a heuristic algorithm to partition an n-bit carry-select adder into a number of adder blocks such that the overall delay of the design is minimized. The experimental results show that our proposed algorithm can achieve on an average 9.1% delay reduction with less than 1% of area overhead on 15 multipliers ranges from 16X16-bit to 64X64-
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CHEN, YU-YUAN, and 陳鈺媛. "The Design of a ROMless Direct Digital Frequency Synthesizer-Carry Select Adder Design and Analysis." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/76882683464879755591.

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碩士<br>華梵大學<br>電子工程學系碩士班<br>96<br>In this thesis, we design a ROMless direct digital frequency synthesizer (DDFS). The chip contains a digital part with a 32-bit phase accumulator realized by a carry select adder. We use the full-custom IC design flow to truly grasps the circuit characteristics, first we use ModelSim to simulate the phase accumulator to confirm our design concept, Next we use HSPICE with TSMC 0.35um 2P4M CMOS model to simulate both the digital part and the analog part. The simulation results show that the current consumption is 8.617mA and the SFDR can reach 42dBc.
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Books on the topic "Carry select Adder (CSLA)"

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Gokhale, U. M., and Prajakta Wasekar. High Performance Carry Select Adder Using Binary Excess Converter. GRIN Verlag GmbH, 2015.

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Satpathy, Pinaki. Design and Implementation of carry select adder using T-Spice. Anchor Academic Publishing, 2016.

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Book chapters on the topic "Carry select Adder (CSLA)"

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Rooj, Nilkantha, Snehanjali Majumder, and Vinay Kumar. "A Novel Design of Carry Select Adder (CSLA) for Low Power, Low Area, and High-Speed VLSI Applications." In Methodologies and Application Issues of Contemporary Computing Framework. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-2345-4_2.

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Arunakumari, S., K. Rajasekahr, S. Sunithamani, and D. Suresh Kumar. "Carry Select Adder Using Binary Excess-1 Converter and Ripple Carry Adder." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2308-1_30.

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Kishore, Pinninti, P. V. Sridevi, and K. Babulu. "Low Power and Optimized Ripple Carry Adder and Carry Select Adder Using MOD-GDI Technique." In Lecture Notes in Electrical Engineering. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2728-1_15.

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Rongali, Siva, and Rajanbabu Mallavarapu. "Gate Diffusion Input-Based Design for Carry Select Adder." In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_26.

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Rohini, D., M. Harsha Vardhan Reddy, and G. Kishor. "Power Optimized Carry Select Adder Using Reversible Logic Gates." In Advances in Engineering Research. Atlantis Press International BV, 2025. https://doi.org/10.2991/978-94-6463-662-8_63.

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Pritty and Mansi Jhamb. "Low Power and Highly Reliable 8-Bit Carry Select Adder." In Lecture Notes in Electrical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-4692-1_41.

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Kavitkar, Shivkumar, and A. Anita Angeline. "Design and Implementation of Multi-bit Self-checking Carry Select Adder." In Lecture Notes in Electrical Engineering. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7251-2_12.

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Deepthi, Kummetha, Pratheeksha Bhaskar, M. Priyanka, B. V. Sonika, and B. N. Shashikala. "Design and Implementation of High-Speed Low-Power Carry Select Adder." In Cognitive Informatics and Soft Computing. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1056-1_41.

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Jujjuru, Jaya Lakshmi, and Rajanbabu Mallavarapu. "Improved SQRT Architecture for Carry Select Adder Using Modified Common Boolean Logic." In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_36.

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Ykuntam, Yamini Devi, Bujjibabu Penumutchi, and Srilakshmi Gubbala. "Design of Speed and Area Efficient Non Linear Carry Select Adder (NLCSLA) Architecture Using XOR Less Adder Module." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-8865-3_7.

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Conference papers on the topic "Carry select Adder (CSLA)"

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Solanki, Garima, Sourav Agarwal, Tushar Mishra, and Vansh Khandelwal. "Design and Implementation of BIST logic for High Speed and Energy Efficient Carry Select Adder(CSLA)." In 2024 Third International Conference on Smart Technologies and Systems for Next Generation Computing (ICSTSN). IEEE, 2024. http://dx.doi.org/10.1109/icstsn61422.2024.10670853.

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Balasubramanian, Padmanabhan, and Douglas L. Maskell. "Fast Bipartitioned Hybrid Adder Utilizing Carry Select and Carry Lookahead Logic." In 2024 9th International Conference on Mathematics and Computers in Sciences and Industry (MCSI). IEEE, 2024. https://doi.org/10.1109/mcsi63438.2024.00023.

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Allada, Sankara Rao, Dr Anjanee Kumar, Kandregula Jyoshna, Kirla Pravallika, B. Medisetti Chandrasekhar, and Konathala Venkat. "Optimized 64-Bit Carry Select Adder Using Enhanced Full Adder for Reduced Power and Delay." In First International Conference on Computer, Computation and Communication (IC3C-2025). River Publishers, 2025. https://doi.org/10.13052/rp-9788743808268a074.

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Thakur, Gunjan, Devanshi Patel, and Jay Patel. "Design of Optimized Carry Select Adder (OCSA) for Low-Power IoT Applications." In 2025 International Conference on Sustainable Energy Technologies and Computational Intelligence (SETCOM). IEEE, 2025. https://doi.org/10.1109/setcom64758.2025.10932418.

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V, Senbagaseelan, Ragul T, Subbulakshmi A, and R. Rajesh Kanna. "Design and Implementation of a 4-Bit Carry Select Adder using MTCMOS-Based Ripple Carry Adder with 10T Full Adders in 90nm Technology." In 2025 International Conference in Advances in Power, Signal, and Information Technology (APSIT). IEEE, 2025. https://doi.org/10.1109/apsit63993.2025.11086236.

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N., Sukrutha, Khushi Ligade, Preeti Ramanna Patil, and Premananda B.S. "Performance Analysis of 4-Bit Hybrid Low Power Carry Select Adder using FinFET Technology." In 2025 3rd International Conference on Smart Systems for applications in Electrical Sciences (ICSSES). IEEE, 2025. https://doi.org/10.1109/icsses64899.2025.11009690.

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Tapadar, Avinaba, Sujan Sarkari, Ayan Dutta, and Jishan Mehedi. "Power and Area Aware Improved SQRT Carry Select Adder (CSIA)." In 2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI). IEEE, 2018. http://dx.doi.org/10.1109/icoei.2018.8553702.

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Chen, Y., Hai Li, K. Roy, and Chena-Kok Koh. "Cascaded carry-select adder (C/sup 2/SA): a new structure for low-power CSA design." In ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design. IEEE, 2005. http://dx.doi.org/10.1109/lpe.2005.195498.

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Chen, Yiran, Hai Li, Kaushik Roy, and Cheng-Kok Koh. "Cascaded carry-select adder (C2SA)." In the 2005 international symposium. ACM Press, 2005. http://dx.doi.org/10.1145/1077603.1077634.

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Dinesh, S., and S. M. Ramesh. "Speed, area, power analysis of modified carry select adder with conventional carry select adder." In PHYSICAL MESOMECHANICS OF CONDENSED MATTER: Physical Principles of Multiscale Structure Formation and the Mechanisms of Nonlinear Behavior: MESO2022. AIP Publishing, 2023. http://dx.doi.org/10.1063/5.0144638.

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