Dissertations / Theses on the topic 'Cascaded H-bridge Multi-Level Inverter'

This report is about control, design and implementation of a low voltage-fed quasi Z-source three-level inverter. The topology has been interesting for photovoltaic-systems due to its ability to boost the incoming voltage without needing an extra switching control. The topology was first simulated in Simulink and later implemented on a full-bridge module to measure the harmonic distortion and estimating the power losses of the inverter. An appropriate control scheme was used to set up a shootthrough and design a three-level inverter. The conclusion for the report is that the quasi Z-source inverter could boost the DC-link voltage in the simulation. But there should be more consideration to the internal resistance of the components for the implementation stage as it gave out a lower output voltage than expected.

This Master degree project was developed during an exchange program, established between the University of Bologna and the Technical University of Munich (TUM). The research activity was conducted at the Institute of Energy Conversion Technology (TUM department) in collobaration with Prof. Dr.-Ing. Hans-Georg Herzog and his research team. A symmetric 3-Phase Cascaded H-bridge Multilevel Inverter (CHBMLI), that is available in the TUM university laboratory, is reconfigured to operate as proposed using a Level Doubling Network (LDN). The LDN takes the form of a 3-phase half-bridge inverter that shares a common DC bus connected to a floating capacitor. This configuration allows almost to double number of output voltage levels. The LDN concept has inherent self-balancing capability that guarantees to maintain voltage across the LDN capacitor at nearly constant value and without any closed-loop control, while it does not consume or supply any power, apart from losses in the circuit. The proposed topology preserves the merit of CHBMLI modular structure, improving overall inverter’s reliability with reduced number of switching devices and required isolated DC sources compare with standard CHBMLI topology. Therefore, it significantly improves power quality, allows to reduce average device switching frequency, while minimizing cost and size of the power filter. Operation of the circuit is extensively verified by simulation in MATLAB/Simulink framework and experiments, performed on a grid-connected 3-phase five level laboratory prototype, specifically built as a part of the current Master Thesis. This work is a first step towards studying the proposed topology. Nevertheless, it provides a baseline for future analyses of the architecture and its possible variations.

This thesis investigates space-vector modulation and one-dimensional modulation applied to the cascaded H-bridge multi-level converter as a model for one port of the UNIFLEX-PM power converter system. The UNIFLEX-PM converter is a modular system including galvanic isolation at medium frequency intended to replace transformers in future distribution and transmission systems. Power converters in this application must produce good quality voltage waveforms with low power loss. In this work, modulation methods are developed using theoretical analyses and simulation studies, before being verified experimentally using a low voltage, laboratory-based power converter operating at the low switching frequencies applicable to high-power applications. Using space-vector modulation, the relationship between the phase of the sampling process and the distortion of the line voltages is used to reduce the harmonic distortion of the output voltages. Different loads are attached to the cells of the cascaded H-bridge converter and limits are derived determining the range of loads for which it is possible to equalize the capacitor voltages. An algorithm which uses redundant states to balance the capacitor voltages without increasing the switching frequency is applied to space-vector modulation and one-dimensional modulation and its performance is compared to the derived limits. The geometrical effect of capacitor voltage ripple on the space-vector diagram is used to derive the influence on the spectrum of the line-voltages. It is identified that second and fourth harmonics of the capacitor voltages contribute to fifth and seventh harmonics of the line voltages. A feed-forward scheme to compensate for the ripple of the capacitor voltage is derived and is shown to reduce the magnitude of un-wanted harmonics. All the methods developed in this thesis can be applied to converters with any number of cells.

Renewable energy is harnessed from continuously replenishing natural processes. Some commonly known are sunlight, water, wind, tides, geothermal heat and various forms of biomass. The focus on renewable energy has over the past few decades intensified greatly. This thesis contributes to the research on developing renewable energy technologies, within the wind power, wave power and marine current power projects at the division of Electricity, Uppsala University. In this thesis grid connection of permanent magnet generator based renewable energy sources is evaluated. A tap transformer based grid connection system has been constructed and experimentally evaluated for a vertical axis wind turbine. Full range variable speed operation of the turbine is enabled by using the different step-up ratios of a tap transformer. This removes the need for a DC/DC step or an active rectifier on the generator side of the full frequency converter and thereby reduces system complexity. Experiments and simulations of the system for variable speed operation are done and efficiency and harmonic content are evaluated.  The work presented in the thesis has also contributed to the design, construction and evaluation of a full-scale offshore marine substation for wave power intended to grid connect a farm of wave energy converters. The function of the marine substation has been experimentally tested and the substation is ready for deployment. Results from the system verification are presented. Special focus is on the transformer losses and transformer in-rush currents. A control and grid connection system for a vertical axis marine current energy converter has been designed and constructed. The grid connection is done with a back-to-back 2L-3L system with a three level cascaded H-bridge converter grid side. The system has been tested in the laboratory and is ready to be installed at the experimental site. Results from the laboratory testing of the system are presented.<br>Wind Power<br>Wave Power<br>Marine Currnet Power

The Queensland University of Technology (QUT) allows the presentation of theses for the Degree of Doctor of Philosophy in the format of published or submitted papers, where such papers have been published, accepted or submitted during the period of candidature. This thesis is composed of ten published /submitted papers and book chapters of which nine have been published and one is under review. This project is financially supported by an Australian Research Council (ARC) Discovery Grant with the aim of investigating multilevel topologies for high quality and high power applications, with specific emphasis on renewable energy systems. The rapid evolution of renewable energy within the last several years has resulted in the design of efficient power converters suitable for medium and high-power applications such as wind turbine and photovoltaic (PV) systems. Today, the industrial trend is moving away from heavy and bulky passive components to power converter systems that use more and more semiconductor elements controlled by powerful processor systems. However, it is hard to connect the traditional converters to the high and medium voltage grids, as a single power switch cannot stand at high voltage. For these reasons, a new family of multilevel inverters has appeared as a solution for working with higher voltage levels. Besides this important feature, multilevel converters have the capability to generate stepped waveforms. Consequently, in comparison with conventional two-level inverters, they present lower switching losses, lower voltage stress across loads, lower electromagnetic interference (EMI) and higher quality output waveforms. These properties enable the connection of renewable energy sources directly to the grid without using expensive, bulky, heavy line transformers. Additionally, they minimize the size of the passive filter and increase the durability of electrical devices. However, multilevel converters have only been utilised in very particular applications, mainly due to the structural limitations, high cost and complexity of the multilevel converter system and control. New developments in the fields of power semiconductor switches and processors will favor the multilevel converters for many other fields of application. The main application for the multilevel converter presented in this work is the front-end power converter in renewable energy systems. Diode-clamped and cascade converters are the most common type of multilevel converters widely used in different renewable energy system applications. However, some drawbacks – such as capacitor voltage imbalance, number of components, and complexity of the control system – still exist, and these are investigated in the framework of this thesis. Various simulations using software simulation tools are undertaken and are used to study different cases. The feasibility of the developments is underlined with a series of experimental results. This thesis is divided into two main sections. The first section focuses on solving the capacitor voltage imbalance for a wide range of applications, and on decreasing the complexity of the control strategy on the inverter side. The idea of using sharing switches at the output structure of the DC-DC front-end converters is proposed to balance the series DC link capacitors. A new family of multioutput DC-DC converters is proposed for renewable energy systems connected to the DC link voltage of diode-clamped converters. The main objective of this type of converter is the sharing of the total output voltage into several series voltage levels using sharing switches. This solves the problems associated with capacitor voltage imbalance in diode-clamped multilevel converters. These converters adjust the variable and unregulated DC voltage generated by renewable energy systems (such as PV) to the desirable series multiple voltage levels at the inverter DC side. A multi-output boost (MOB) converter, with one inductor and series output voltage, is presented. This converter is suitable for renewable energy systems based on diode-clamped converters because it boosts the low output voltage and provides the series capacitor at the output side. A simple control strategy using cross voltage control with internal current loop is presented to obtain the desired voltage levels at the output voltage. The proposed topology and control strategy are validated by simulation and hardware results. Using the idea of voltage sharing switches, the circuit structure of different topologies of multi-output DC-DC converters – or multi-output voltage sharing (MOVS) converters – have been proposed. In order to verify the feasibility of this topology and its application, steady state and dynamic analyses have been carried out. Simulation and experiments using the proposed control strategy have verified the mathematical analysis. The second part of this thesis addresses the second problem of multilevel converters: the need to improve their quality with minimum cost and complexity. This is related to utilising asymmetrical multilevel topologies instead of conventional multilevel converters; this can increase the quality of output waveforms with a minimum number of components. It also allows for a reduction in the cost and complexity of systems while maintaining the same output quality, or for an increase in the quality while maintaining the same cost and complexity. Therefore, the asymmetrical configuration for two common types of multilevel converters – diode-clamped and cascade converters – is investigated. Also, as well as addressing the maximisation of the output voltage resolution, some technical issues – such as adjacent switching vectors – should be taken into account in asymmetrical multilevel configurations to keep the total harmonic distortion (THD) and switching losses to a minimum. Thus, the asymmetrical diode-clamped converter is proposed. An appropriate asymmetrical DC link arrangement is presented for four-level diode-clamped converters by keeping adjacent switching vectors. In this way, five-level inverter performance is achieved for the same level of complexity of the four-level inverter. Dealing with the capacitor voltage imbalance problem in asymmetrical diodeclamped converters has inspired the proposal for two different DC-DC topologies with a suitable control strategy. A Triple-Output Boost (TOB) converter and a Boost 3-Output Voltage Sharing (Boost-3OVS) converter connected to the four-level diode-clamped converter are proposed to arrange the proposed asymmetrical DC link for the high modulation indices and unity power factor. Cascade converters have shown their abilities and strengths in medium and high power applications. Using asymmetrical H-bridge inverters, more voltage levels can be generated in output voltage with the same number of components as the symmetrical converters. The concept of cascading multilevel H-bridge cells is used to propose a fifteen-level cascade inverter using a four-level H-bridge symmetrical diode-clamped converter, cascaded with classical two-level Hbridge inverters. A DC voltage ratio of cells is presented to obtain maximum voltage levels on output voltage, with adjacent switching vectors between all possible voltage levels; this can minimize the switching losses. This structure can save five isolated DC sources and twelve switches in comparison to conventional cascade converters with series two-level H bridge inverters. To increase the quality in presented hybrid topology with minimum number of components, a new cascade inverter is verified by cascading an asymmetrical four-level H-bridge diode-clamped inverter. An inverter with nineteen-level performance was achieved. This synthesizes more voltage levels with lower voltage and current THD, rather than using a symmetrical diode-clamped inverter with the same configuration and equivalent number of power components. Two different predictive current control methods for the switching states selection are proposed to minimise either losses or THD of voltage in hybrid converters. High voltage spikes at switching time in experimental results and investigation of a diode-clamped inverter structure raised another problem associated with high-level high voltage multilevel converters. Power switching components with fast switching, combined with hard switched-converters, produce high di/dt during turn off time. Thus, stray inductance of interconnections becomes an important issue and raises overvoltage and EMI issues correlated to the number of components. Planar busbar is a good candidate to reduce interconnection inductance in high power inverters compared with cables. The effect of different transient current loops on busbar physical structure of the high-voltage highlevel diode-clamped converters is highlighted. Design considerations of proper planar busbar are also presented to optimise the overall design of diode-clamped converters.

This thesis describes the flexible voltage control of a multi-level-voltage-reinjection voltage source converter. The main purposes are to achieve reactive power generation flexibility when applied for HVdc transmission systems, reduce dynamic voltage balancing for direct series connected switches and an improvement of high power converter efficiency and reliability. Waveform shapes and the impact on ac harmonics caused by the modulation process are studied in detail. A configuration is proposed embracing concepts of multi level, soft-switching and harmonic cancellation. For the configuration, the firing sequence, waveform analysis, steady-state and dynamic performances and close-loop control strategies are presented. In order not to severely compromise the original advantages of the converter, the modulated waveforms are proposed based on the restrictions imposed mathematically by the harmonic cancellation concept and practically by the synthesis circuit complexity and high switching losses. The harmonic impact on the ac power system prompted by the modulation process is studied from idealistic and practical aspects. The circuit topology being proposed in this thesis is developed from a 12-pulse bridge and a converter used classically for inverting power from separated dc sources. Switching functions are deduced and current paths through the converter are analysed. Safe and steady-state operating regions of the converter are studied in phasor diagrams to facilitate the design of simple controllers for active power transfer and reactive power generations. An investigation into the application of this topology to the back-to-back VSC HVdc interconnection is preformed via EMTDC simulations.

碩士<br>元智大學<br>電機工程學系<br>106<br>A procedure in this paper, the hardware design of Implementation and drive of the multi-level multi-phase cascaded H-bridge inverter is developed. By means of isolation of transformer and optocoupler, the power module of high reliability is provided. The inverter consists of two main parts Constitute: 1. Driver board drive circuit is responsible for driving the power module. 2. DC link capacitor and current detection circuit of the power board circuit board, is responsible for stabilizing the power supply and detection motor current and H-bridge MOSFET power output circuit. These two parts of the design are closely related to the entire inverter power output and performance.

The automobile industry is moving fast towards Electric Vehicles (EV); however this paradigm shift is currently making its smooth transition through the phase of Hybrid Electric Vehicles. There is an ever-growing need for integration of hybrid energy sources especially for vehicular applications. Different energy sources such as batteries, ultra-capacitors, fuel cells etc. are available. Usage of these varied energy sources alone or together in different combinations in automobiles requires advanced power electronic circuits and control methodologies. An exhaustive literature survey has been carried out to study the power electronic converter, switching modulation strategy to be employed and the particular machine to be used in an EV. Adequate amount of effort has been put into designing the vehicle specifications. Owing to stronger demand for higher performance and torque response in an EV, the Permanent Magnet Synchronous Machine has been favored over the traditional Induction Machine. The aim of this thesis is to demonstrate the use of a multi level inverter fed Brush Less Direct Current (BLDC) motor in a field oriented control fashion in an EV and make it follow a given drive cycle. The switching operation and control of a multi level inverter for specific power level and desired performance characteristics is investigated. The EV has been designed from scratch taking into consideration the various factors such as mass, coefficients of aerodynamic drag and air friction, tire radius etc. The design parameters are meant to meet the requirements of a commercial car. The various advantages of a multi level inverter fed PMSM have been demonstrated and an exhaustive performance evaluation has been done. The investigation is done by testing the designed system on a standard drive cycle, New York urban driving cycle. This highly transient driving cycle is particularly used because it provides rapidly changing acceleration and deceleration curves. Furthermore, the evaluation of the system under fault conditions is also done. It is demonstrated that the system is stable and has a ride-through capability under different fault conditions. The simulations have been carried out in MATLAB and Simulink, while some preliminary studies involving switching losses of the converter were done in PSIM.

Conventional 2-level inverters have been quite popular in industry for drives applications. It used pulse width modulation techniques to generate a voltage waveform with high quality. For achieving this, it had to switch at high frequencies and also the switching is between 0 and Vdc. Also additional LC filters are required before feeding to a motor. 3-phase IM is the work horse of the industry. Several speed control techniques have been established namely the V/f control technique and for high performance, vector control is adopted. An electric drive system comprises of a rectifier, inverter, a motor and a load. each module is a topic by itself. This thesis work discusses the novel inverter topologies to overcome the demerits of a conventional 2-level inverter or even the basic multilevel topologies, for an electric drive. The word ‘multilevel’ itself signifies that inverter can generate more than two levels. The idea was first originated by Nabae, Takahashi and Akagi to bring an additional voltage level so that the waveform becomes a quasi square wave. This additional voltage level brought additional benefits in terms of reduced dv/dt and requirement of low switching frequency. But this was not without any cost. The inverter structure is slightly more complicated than a 2-level and also required more devices. But the advantage it gave was superior enough to such an extent that the above topology (popularly known as NPC) has become quite popular in industry. This topology was later modified to equalize the semiconductor losses among switches by replacing the clamping diodes with controllable switches and such topologies are popularly known as Active NPCs (ANPCs) because of the replacement of diodes with active switches. 3-level flying capacitors were then introduced where the additional voltage level is provided using charged capacitors. But this capacitor voltage has to be maintained at its nominal value during the inverter operation. An additional floating capacitor, which is an electrolytic capacitor is needed for this. Increasing the number of electrolytic capacitors reduces the reliability of the inverter drive since they are the weakest link in any inverters and its count has to be kept to the minimum. By using a H-bridge cell in each of the three phases, three voltage levels can be easily obtained.This is commonly known as Cascaded H-bridge (CHB) multilevel inverter. The above three topologies have been discussed with respect to generation of three pole voltage levels and these topologies are quite suited also. A higher number of voltage levels will reduce the switching frequency even lesser and also the dv/dt. On increasing the number of levels further and further, finally the inverter need not do any PWM switching and just generating the levels is sufficient enough for a good quality waveform and also low dv/dt. But when the above topologies are scaled for more than three voltage levels, all of them suffer serious drawbacks which is briefly discussed below. The diode clamped inverter (known as NPC if it is 3-level), when extended to more than three levels suffers from the neutral point balancing issue and also the count of clamping diodes increase drastically. FC inverters, when extended beyond 3-level, the number of electrolytic capacitors increases and also balancing of these capacitors to their nominal voltages becomes complicated. In the case of multilevel CHB, when extended beyond 3-level, the requirement of isolated DC sources also increases. To generate isolated supplies, phase shifting transformer and 8, 12 or 24 pulse diode rectifier is needed which increases the weight , size and cost of the drive. Therefore its application is limited. In this thesis, the aim is to develop a novel method to develop a multilevel inverter without the drawbacks faced by the basic multilevel topologies when scaled for higher number of voltage levels. This is done through stacking the basic or hybrid combination of these basic multilevel topologies through selector switches. This method is experimentally verified by stacking two 5-level inverters through a 2-level selector switch (whose switching losses can be minimized through soft cycle commutation). This will generate nine levels.Generating 9-levels through scaling the basic topologies is disadvantageous, the comparison table is provided in the thesis. This is true for any higher voltage level generation. Each of the above 5-level inverter is developed through cascading an FC with a capacitor fed H-bridge. The device count can be reduced by making the FC-CHB module common to the selector switches by shifting the selector switches between the DC link and the common FC-CHB module. Doing so, reduces the modular feature of the drive but the device count can be reduced. The FFT plot at different frequencies of operation and the switching losses of the different modules-FC, CHB and the selector switches are also plotted for different frequencies of operation. The next step is to check whether this method can be extended to any number of stackings for generation of more voltage levels. For this, a 49-level inverter is developed in laboratory by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading an FC with three CHBs. When there are 49 levels in the pole voltage waveform, there is no need to do any regular PWM since the output waveform will be very close to a sine wave even without any PWM switching. The technique used is commonly known in literature as Nearest Level Control (NLC). This method of stacking and cascading has the advantage that the FC and the CHB modules now are of very low voltages and the switching losses can be reduced. The switching losses of the different modules are calculated and plotted for different operating frequencies in the thesis. To reduce the voltages of the modules further, a 6-phase machine has been reconfigured as a 3-phase machine, the advantage being that now the DC link voltage requirement is half of that needed earlier for the same power. This further reduces voltages of the modules by half and this allows the switches to be replaced with MOSFETs, improving the efficiency of the drive. This topology is also experimentally verified for both steady state and transient conditions. So far the research focussed on a 3-phase IM fed through a stacked MLI. It can be observed that a stacked MLI needs as many DC sources as the number of stackings. A 6-phase machine apart from reduced DC link voltage requirement, has other advantages of better fault tolerant capability and better space harmonics. They are serious contenders for applications like ship propulsion, locomotive traction, electric vehicles, more electric aircraft and other high power industrial applications. Using the unique property of a 6-phase machine that its opposite windings always draw equal and opposite current, the neutral point (NP) (formed as a result of stacking two MLIs) voltage can be balanced. It was observed that the net mid point current drawn from the mid point can be made zero in a switching interval. It was later observed that with minimal changes, the mid point current drawn from the NP can be made instantaneously zero and the NP voltage deviation is completely arrested and the topology needs only very low capacity series connected capacitors energized from a single DC link. This topology is also experimentally verified using the stacked 9-level inverter topology discussed above but now for 6-phase application and experimental results are provided in the thesis. Single DC link enables direct back to back conversion and power can be fed back to the mains at any desired power factor. All the experimental verification is done on a DSP (TMS320F28335) and FPGA (Spartan 3 XCS3200) platform. An IM is run using V/f control scheme and the above inverter topologies are used to drive the motor. The IGBTs used are SKM75GB123D for the stacked 9-level inverter in the 3-phase and 6-phase experiments. For the 49-level inverter experiment, MOSFETs-IRF260N were used. Both steady state and transient results ensure that the proposed inverter topologies are suitable for high power applications.

Conventional 2-level inverters have been quite popular in industry for drives applications. It used pulse width modulation techniques to generate a voltage waveform with high quality. For achieving this, it had to switch at high frequencies and also the switching is between 0 and Vdc. Also additional LC filters are required before feeding to a motor. 3-phase IM is the work horse of the industry. Several speed control techniques have been established namely the V/f control technique and for high performance, vector control is adopted. An electric drive system comprises of a rectifier, inverter, a motor and a load. each module is a topic by itself. This thesis work discusses the novel inverter topologies to overcome the demerits of a conventional 2-level inverter or even the basic multilevel topologies, for an electric drive. The word ‘multilevel’ itself signifies that inverter can generate more than two levels. The idea was first originated by Nabae, Takahashi and Akagi to bring an additional voltage level so that the waveform becomes a quasi square wave. This additional voltage level brought additional benefits in terms of reduced dv/dt and requirement of low switching frequency. But this was not without any cost. The inverter structure is slightly more complicated than a 2-level and also required more devices. But the advantage it gave was superior enough to such an extent that the above topology (popularly known as NPC) has become quite popular in industry. This topology was later modified to equalize the semiconductor losses among switches by replacing the clamping diodes with controllable switches and such topologies are popularly known as Active NPCs (ANPCs) because of the replacement of diodes with active switches. 3-level flying capacitors were then introduced where the additional voltage level is provided using charged capacitors. But this capacitor voltage has to be maintained at its nominal value during the inverter operation. An additional floating capacitor, which is an electrolytic capacitor is needed for this. Increasing the number of electrolytic capacitors reduces the reliability of the inverter drive since they are the weakest link in any inverters and its count has to be kept to the minimum. By using a H-bridge cell in each of the three phases, three voltage levels can be easily obtained.This is commonly known as Cascaded H-bridge (CHB) multilevel inverter. The above three topologies have been discussed with respect to generation of three pole voltage levels and these topologies are quite suited also. A higher number of voltage levels will reduce the switching frequency even lesser and also the dv/dt. On increasing the number of levels further and further, finally the inverter need not do any PWM switching and just generating the levels is sufficient enough for a good quality waveform and also low dv/dt. But when the above topologies are scaled for more than three voltage levels, all of them suffer serious drawbacks which is briefly discussed below. The diode clamped inverter (known as NPC if it is 3-level), when extended to more than three levels suffers from the neutral point balancing issue and also the count of clamping diodes increase drastically. FC inverters, when extended beyond 3-level, the number of electrolytic capacitors increases and also balancing of these capacitors to their nominal voltages becomes complicated. In the case of multilevel CHB, when extended beyond 3-level, the requirement of isolated DC sources also increases. To generate isolated supplies, phase shifting transformer and 8, 12 or 24 pulse diode rectifier is needed which increases the weight , size and cost of the drive. Therefore its application is limited. In this thesis, the aim is to develop a novel method to develop a multilevel inverter without the drawbacks faced by the basic multilevel topologies when scaled for higher number of voltage levels. This is done through stacking the basic or hybrid combination of these basic multilevel topologies through selector switches. This method is experimentally verified by stacking two 5-level inverters through a 2-level selector switch (whose switching losses can be minimized through soft cycle commutation). This will generate nine levels.Generating 9-levels through scaling the basic topologies is disadvantageous, the comparison table is provided in the thesis. This is true for any higher voltage level generation. Each of the above 5-level inverter is developed through cascading an FC with a capacitor fed H-bridge. The device count can be reduced by making the FC-CHB module common to the selector switches by shifting the selector switches between the DC link and the common FC-CHB module. Doing so, reduces the modular feature of the drive but the device count can be reduced. The FFT plot at different frequencies of operation and the switching losses of the different modules-FC, CHB and the selector switches are also plotted for different frequencies of operation. The next step is to check whether this method can be extended to any number of stackings for generation of more voltage levels. For this, a 49-level inverter is developed in laboratory by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading an FC with three CHBs. When there are 49 levels in the pole voltage waveform, there is no need to do any regular PWM since the output waveform will be very close to a sine wave even without any PWM switching. The technique used is commonly known in literature as Nearest Level Control (NLC). This method of stacking and cascading has the advantage that the FC and the CHB modules now are of very low voltages and the switching losses can be reduced. The switching losses of the different modules are calculated and plotted for different operating frequencies in the thesis. To reduce the voltages of the modules further, a 6-phase machine has been reconfigured as a 3-phase machine, the advantage being that now the DC link voltage requirement is half of that needed earlier for the same power. This further reduces voltages of the modules by half and this allows the switches to be replaced with MOSFETs, improving the efficiency of the drive. This topology is also experimentally verified for both steady state and transient conditions. So far the research focussed on a 3-phase IM fed through a stacked MLI. It can be observed that a stacked MLI needs as many DC sources as the number of stackings. A 6-phase machine apart from reduced DC link voltage requirement, has other advantages of better fault tolerant capability and better space harmonics. They are serious contenders for applications like ship propulsion, locomotive traction, electric vehicles, more electric aircraft and other high power industrial applications. Using the unique property of a 6-phase machine that its opposite windings always draw equal and opposite current, the neutral point (NP) (formed as a result of stacking two MLIs) voltage can be balanced. It was observed that the net mid point current drawn from the mid point can be made zero in a switching interval. It was later observed that with minimal changes, the mid point current drawn from the NP can be made instantaneously zero and the NP voltage deviation is completely arrested and the topology needs only very low capacity series connected capacitors energized from a single DC link. This topology is also experimentally verified using the stacked 9-level inverter topology discussed above but now for 6-phase application and experimental results are provided in the thesis. Single DC link enables direct back to back conversion and power can be fed back to the mains at any desired power factor. All the experimental verification is done on a DSP (TMS320F28335) and FPGA (Spartan 3 XCS3200) platform. An IM is run using V/f control scheme and the above inverter topologies are used to drive the motor. The IGBTs used are SKM75GB123D for the stacked 9-level inverter in the 3-phase and 6-phase experiments. For the 49-level inverter experiment, MOSFETs-IRF260N were used. Both steady state and transient results ensure that the proposed inverter topologies are suitable for high power applications.

碩士<br>崑山科技大學<br>電子工程研究所<br>100<br>The multi-level H-bridge DC-AC inverter has been widely used in the AC power grid-connected photovoltaic power system. Because, its output waveform is high quality and low electromagnetic interference. Hence, it is widely used in many large-scale photo voltaic (PV) systems. The most common application of many H-type bridges square wave inverter cascaded series to approximate the stairs-sine waveform. Multi-level H-bridge inverter can output different pulse width modulation (PWM) waveforms, then cascades them to change harmonic properties and affecting the inveter output waveform quality. The main issue of this thesis is to research how to improve the operational characteristics of the multi-level inverter, and the relevance inverter cascading series and power quality.

Multilevel voltage source inverters have been receiving more and more attention from the industry and academia as a choice for high voltage and high power applications. The high voltage multilevel inverters can be constructed with existing low voltage semiconductor switches, which already have a mature technology for handling low voltages, thus improving the reliability of the overall inverter system. These multilevel inverters generate the output voltage in the form of multi-stepped waveform with smaller amplitude. This will result in less dv/dt at the motor inputs and electromagnetic interference (EMI) caused by switching is considerably less. Because of the multi-stepped waveform, the instantaneous error in the output voltage will be always less compared to the conventional two-level inverter output voltage. It will reduce the unwanted harmonic content in the output voltage, which will enable to switch the inverter at lower frequencies. Many interesting multi level inverter topologies are proposed by various research groups across the world from industry and academic institutions. But apart from the conventional 3-level NPC and H-bridge topology, others are not yet highly preferred for general high power drives applications. In this respect, two different five-level inverter topologies and one three-level inverter topology for high power induction motor drive applications are proposed in this work. Existing knowledge from published literature shows that, the three-level voltage space vector diagram can be generated for an open-end winding induction motor by feeding the motor phase windings with two two-level inverters from both sides. In such a configuration, each inverter is capable of assuming 8 switching states independent of the other. Therefore a total of 64 switching combinations are possible, whereas the conventional NPC inverter have 27 possible switching combinations. The main drawback for this configuration is that, it requires a harmonic filter or isolated voltage source to suppress the common mode currents through the motor phase winding. In general, the harmonic filters are not desirable because, it is expensive and bulky in nature. Some topologies have been presented, in the past, to suppress the common mode voltage on the motor phase windings when the both inverters are fed with a single voltage source. But these schemes under utilize the dc-link voltage or use the extra power circuit. The scheme presented in chapter-3 eliminates the requirement of harmonic filter or isolated voltage source to block the common mode current in the motor phase windings. Both the two-level inverters, in this scheme, are fed with the same voltage source with a magnitude of Vdc/2 where Vdc is the voltage magnitude requires for the NPC three-level inverter. In this scheme, the identical voltage profile winding coils (pole pair winding coils), in the four pole induction motor, are disconnected electrically and reconnected in two star groups. The isolated neutrals, provided by the two star groups, will not allow the triplen currents to flow in the motor phase windings. To apply identical fundamental voltage on disconnected pole pair winding, decoupled space vector PWM is used. This PWM technique eliminates the first center band harmonics thereby it will allow the inverters to operate at lower switching frequency. This scheme doesn’t require any additional power circuit to block the triplen currents and also it will not underutilize the dc-bus voltage. A five-level inverter topology for four pole induction motor is presented in chapter-3. In this topology, the disconnected pole pair winding coils are effectively utilized to generate a five-level voltage space vector diagram for a four pole induction motor. The disconnected pole pair winding coils are fed from both sides with conventional two-level inverters. Thereby the problems like capacitor voltage balancing issues are completely eliminated. Three isolated voltage sources, with a voltage magnitude of Vdc/4, are used to block the triplen current in the motor phase windings. This scheme is also capable of generating 61 space vector locations similar to conventional NPC five-level inverter. However, this scheme has 1000 switching combinations to realize 61 space vector locations whereas the NPC five-level inverter has 125 switching combinations. In case of any switch failure, using the switching state redundancy, the proposed topology can be operated as a three-level inverter in lower modulation index. But this topology requires six additional bi-directional switches with a maximum voltage blocking capacity of Vdc/8. However, it doesn’t require any complicated control algorithm to generate the gating pulses for bidirectional switches. The above presented two schemes don’t require any special design modification for the induction machine. Although the schemes are presented for four pole induction motor, this technique can be easily extend to the induction motor with more than four poles and thereby the number of voltage levels on the phase winding can be further increased. An alternate five-level inverter topology for an open-end winding induction motor is presented in chapter-4. This topology doesn’t require to disconnect the pole pair winding coils like in the previous propositions. The open-end winding induction motor is fed from one end with a two-level inverter in series with a capacitor fed H-bridge cell, while the other end is connected to a conventional two-level inverter to get a five voltage levels on the motor phase windings. This scheme is also capable of generating a voltage space vector diagram identical to that of a conventional five-level inverter. A total of 2744 switching combinations are possible to generate the 61 space vector locations. With such huge number switching state redundancies, it is possible to balance the H-bridge capacitor voltage for full modulation range. In addition to that, the proposed topology eliminates eighteen clamping diode having different voltage ratings compared to the NPC inverter. The proposed topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor fed H-bridge cell. All the proposed topologies are experimentally verified on a 5 h.p. four pole induction motor using V/f control. The PWM signals for the inverters are generated using the TMS320F2812 and GAL22V10B/SPARTAN XC3S200 FPGA platforms. Though the proposed inverter topologies are suggested for high-voltage and high-power industrial IM drive applications, due to laboratory constraints the experimental results are taken on the 5h.p prototypes. But all the proposed schemes are general in nature and can be easily implemented for high-voltage high-power drive applications with appropriate device ratings.

Multilevel voltage source inverters have been receiving more and more attention from the industry and academia as a choice for high voltage and high power applications. The high voltage multilevel inverters can be constructed with existing low voltage semiconductor switches, which already have a mature technology for handling low voltages, thus improving the reliability of the overall inverter system. These multilevel inverters generate the output voltage in the form of multi-stepped waveform with smaller amplitude. This will result in less dv/dt at the motor inputs and electromagnetic interference (EMI) caused by switching is considerably less. Because of the multi-stepped waveform, the instantaneous error in the output voltage will be always less compared to the conventional two-level inverter output voltage. It will reduce the unwanted harmonic content in the output voltage, which will enable to switch the inverter at lower frequencies. Many interesting multi level inverter topologies are proposed by various research groups across the world from industry and academic institutions. But apart from the conventional 3-level NPC and H-bridge topology, others are not yet highly preferred for general high power drives applications. In this respect, two different five-level inverter topologies and one three-level inverter topology for high power induction motor drive applications are proposed in this work. Existing knowledge from published literature shows that, the three-level voltage space vector diagram can be generated for an open-end winding induction motor by feeding the motor phase windings with two two-level inverters from both sides. In such a configuration, each inverter is capable of assuming 8 switching states independent of the other. Therefore a total of 64 switching combinations are possible, whereas the conventional NPC inverter have 27 possible switching combinations. The main drawback for this configuration is that, it requires a harmonic filter or isolated voltage source to suppress the common mode currents through the motor phase winding. In general, the harmonic filters are not desirable because, it is expensive and bulky in nature. Some topologies have been presented, in the past, to suppress the common mode voltage on the motor phase windings when the both inverters are fed with a single voltage source. But these schemes under utilize the dc-link voltage or use the extra power circuit. The scheme presented in chapter-3 eliminates the requirement of harmonic filter or isolated voltage source to block the common mode current in the motor phase windings. Both the two-level inverters, in this scheme, are fed with the same voltage source with a magnitude of Vdc/2 where Vdc is the voltage magnitude requires for the NPC three-level inverter. In this scheme, the identical voltage profile winding coils (pole pair winding coils), in the four pole induction motor, are disconnected electrically and reconnected in two star groups. The isolated neutrals, provided by the two star groups, will not allow the triplen currents to flow in the motor phase windings. To apply identical fundamental voltage on disconnected pole pair winding, decoupled space vector PWM is used. This PWM technique eliminates the first center band harmonics thereby it will allow the inverters to operate at lower switching frequency. This scheme doesn’t require any additional power circuit to block the triplen currents and also it will not underutilize the dc-bus voltage. A five-level inverter topology for four pole induction motor is presented in chapter-3. In this topology, the disconnected pole pair winding coils are effectively utilized to generate a five-level voltage space vector diagram for a four pole induction motor. The disconnected pole pair winding coils are fed from both sides with conventional two-level inverters. Thereby the problems like capacitor voltage balancing issues are completely eliminated. Three isolated voltage sources, with a voltage magnitude of Vdc/4, are used to block the triplen current in the motor phase windings. This scheme is also capable of generating 61 space vector locations similar to conventional NPC five-level inverter. However, this scheme has 1000 switching combinations to realize 61 space vector locations whereas the NPC five-level inverter has 125 switching combinations. In case of any switch failure, using the switching state redundancy, the proposed topology can be operated as a three-level inverter in lower modulation index. But this topology requires six additional bi-directional switches with a maximum voltage blocking capacity of Vdc/8. However, it doesn’t require any complicated control algorithm to generate the gating pulses for bidirectional switches. The above presented two schemes don’t require any special design modification for the induction machine. Although the schemes are presented for four pole induction motor, this technique can be easily extend to the induction motor with more than four poles and thereby the number of voltage levels on the phase winding can be further increased. An alternate five-level inverter topology for an open-end winding induction motor is presented in chapter-4. This topology doesn’t require to disconnect the pole pair winding coils like in the previous propositions. The open-end winding induction motor is fed from one end with a two-level inverter in series with a capacitor fed H-bridge cell, while the other end is connected to a conventional two-level inverter to get a five voltage levels on the motor phase windings. This scheme is also capable of generating a voltage space vector diagram identical to that of a conventional five-level inverter. A total of 2744 switching combinations are possible to generate the 61 space vector locations. With such huge number switching state redundancies, it is possible to balance the H-bridge capacitor voltage for full modulation range. In addition to that, the proposed topology eliminates eighteen clamping diode having different voltage ratings compared to the NPC inverter. The proposed topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor fed H-bridge cell. All the proposed topologies are experimentally verified on a 5 h.p. four pole induction motor using V/f control. The PWM signals for the inverters are generated using the TMS320F2812 and GAL22V10B/SPARTAN XC3S200 FPGA platforms. Though the proposed inverter topologies are suggested for high-voltage and high-power industrial IM drive applications, due to laboratory constraints the experimental results are taken on the 5h.p prototypes. But all the proposed schemes are general in nature and can be easily implemented for high-voltage high-power drive applications with appropriate device ratings.