Relevant bibliographies by topics / CELL Broadband Engine

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'CELL Broadband Engine'

Author: Grafiati
Published: 4 June 2021
Last updated: 4 February 2022

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Journal articles on the topic "CELL Broadband Engine"

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Shi, Guochun, Volodymyr Kindratenko, Frederico Pratas, Pedro Trancoso, and Michael Gschwind. "Application Acceleration with the Cell Broadband Engine." Computing in Science & Engineering 12, no. 1 (January 2010): 76–81. http://dx.doi.org/10.1109/mcse.2010.4.

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Riley, Mack W., and Mike Genden. "Cell Broadband Engine Debugging for Unknown Events." IEEE Design & Test of Computers 24, no. 5 (September 2007): 486–93. http://dx.doi.org/10.1109/mdt.2007.157.

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Kurzak, Jakub, and Jack Dongarra. "QR Factorization for the Cell Broadband Engine." Scientific Programming 17, no. 1-2 (2009): 31–42. http://dx.doi.org/10.1155/2009/239720.

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The QR factorization is one of the most important operations in dense linear algebra, offering a numerically stable method for solving linear systems of equations including overdetermined and underdetermined systems. Modern implementations of the QR factorization, such as the one in the LAPACK library, suffer from performance limitations due to the use of matrix–vector type operations in the phase of panel factorization. These limitations can be remedied by using the idea of updating of QR factorization, rendering an algorithm, which is much more scalable and much more suitable for implementation on a multi-core processor. It is demonstrated how the potential of the cell broadband engine can be utilized to the fullest by employing the new algorithmic approach and successfully exploiting the capabilities of the chip in terms of single instruction multiple data parallelism, instruction level parallelism and thread-level parallelism.
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de Kruijf, M., and K. Sankaralingam. "MapReduce for the Cell Broadband Engine Architecture." IBM Journal of Research and Development 53, no. 5 (September 2009): 10:1–10:12. http://dx.doi.org/10.1147/jrd.2009.5429076.

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Johns, C. R., and D. A. Brokenshire. "Introduction to the Cell Broadband Engine Architecture." IBM Journal of Research and Development 51, no. 5 (September 2007): 503–19. http://dx.doi.org/10.1147/rd.515.0503.

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Shimizu, K., H. P. Hofstee, and J. S. Liberty. "Cell Broadband Engine processor vault security architecture." IBM Journal of Research and Development 51, no. 5 (September 2007): 521–28. http://dx.doi.org/10.1147/rd.515.0521.

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Riley, M. W., J. D. Warnock, and D. F. Wendel. "Cell Broadband Engine processor: Design and implementation." IBM Journal of Research and Development 51, no. 5 (September 2007): 545–57. http://dx.doi.org/10.1147/rd.515.0545.

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MURASE, Masana. "Eliminating Cell Broadband Engine™ DMA Buffer Overflows." IEICE Transactions on Information and Systems E93-D, no. 5 (2010): 1062–69. http://dx.doi.org/10.1587/transinf.e93.d.1062.

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Bader, David A., Virat Agarwal, and Seunghwa Kang. "Computing discrete transforms on the Cell Broadband Engine." Parallel Computing 35, no. 3 (March 2009): 119–37. http://dx.doi.org/10.1016/j.parco.2008.12.007.

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Sarje, A., and S. Aluru. "Parallel Genomic Alignments on the Cell Broadband Engine." IEEE Transactions on Parallel and Distributed Systems 20, no. 11 (November 2009): 1600–1610. http://dx.doi.org/10.1109/tpds.2008.254.

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Dissertations / Theses on the topic "CELL Broadband Engine"

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Ålind, Markus. "A Skeleton library for Cell Broadband Engine." Thesis, Linköping University, Department of Computer and Information Science, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-54476.

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The Cell Broadband Engine processor is a powerful processor capable of over 220 GFLOPS. It is highly specialized and can be controlled in detail by the programmer. The Cell is significantly more complicated to program than a standard homogeneous multi core processor such as the Intel Core2 Duo and Quad. This thesis explores the possibility to abstract some of the complexities of Cell programming while maintaining high performance. The abstraction is achieved through a library of parallel skeletons implemented in the bulk synchronous parallel programming environment NestStep. The library includes constructs for user defined SIMD optimized data parallel skeletons such as map, reduce and more. The evaluation of the library includes porting of a vector based scientific computation program from sequential C code to the Cell using the library and the NestStep environment. The ported program shows good performance when compared to the sequential original code run on a high-end x86 processor. The evaluation also shows that a dot product implemented with the skeleton library is faster than the dot product in the IBM BLAS library for the Cell processor with more than two slave processors.

 

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Lundberg, Marcus. "A Parallel Monte Carlo Implementation on the Cell Broadband Engine." Thesis, Uppsala University, Department of Information Technology, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-108035.

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The Cell Broadband Engine is a heterogeneous multi-core processor architecture thattrades ease-of-programming for high performance. While primarily featured in theSony PlayStation 3 (PS3) for high-end games, it is a promising technology for scientistsworking with computationally heavy numerical methods. This paper presents threeimplementations of a Monte Carlo simulation of a system of charged particles on thePS3. The first method, while easy to implement and use, did not yield anyperformance advantage over conventional x86 processors. The second method ranmore than twice as fast on the PS3 as a comparable code on a 1.86 GHz Intel Xeonmachine but could run only a limited problem size. The third program ran over sixtimes faster than the x86 reference system and could handle any problem up to thesaturation of the PS3 main memory. The final program is also suitable for a cluster ofPlayStations and is easily adaptable to work on a distributed computing framework.

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Rajamohan, Srijith Datta Suman Narayanan Vijaykrishnan. "A neural network based classifier on the cell broadband engine." [University Park, Pa.] : Pennsylvania State University, 2009. http://etda.libraries.psu.edu/theses/approved/WorldWideIndex/ETD-4512/index.html.

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Lopes, André Filipe da Rocha. "tlCell: a software transactional memory for the cell broadband engine architecture." Master's thesis, Faculdade de Cencias e Tecnologia, 2010. http://hdl.handle.net/10362/4110.

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Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do Grau de Mestre em Engenharia Informática
Os computadores evoluíram exponencialmente na ultima década. A performance tem sido o principal objectivo resultando no aumento do frequência dos processadores, situação que já não é fazível devido ao consumo de energia exagerado dos processadores actuais. A arquitectura Cell Broadband Engine começou com o objectivo de providenciar alta capacidade computacional com um baixo consumo energético. O resultado é uma arquitectura com multiprocessadores heterogéneos e uma distribuição de memória única com vista a alto desempenho e redução da complexidade do hardware para reduzir o custo de produção. Espera-se que as técnicas de concorrência e paralelismo aumentem a performance desta arquitectura, no entanto as soluções de alto desempenho apresentadas s˜ao sempre muito especificas e devido à sua arquitectura e distribuição de memória inovadora ´e ainda difícil apresentar ferramentas passíveis de explorar concorrência e paralelismo como um camada de abstracção. Memória Transaccional por Software é um modelo de programação que propõe este nível de abstracção e tem vindo a ganhar popularidade existindo já variadas implementações com performance perto de soluções específicas de grão fino. A possibilidade de usar Memória Transaccional por Software nesta arquitectura inovadora, desenvolvendo uma ferramenta capaz de abstrair o programador da consistência e gestão de memória é apelativo. Neste documento especifica-se uma plataforma deffered-update de Memória Transactional por Software para a arquitectura Cell Broadband Engine que tira partido da capacidade computacional dos Synergistic Processing Elements (SPEs) usando locks em commit-time. São propostos dois modelos diferentes, fully local e multi-buffered de forma a poder estudar as implicações das escolhas feitas no desenho da plataforma.
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Azuelos, Nathaniel. "An integrated functional solution for multi-core programming on the cell broadband engine." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=32276.

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Recent efforts in microprocessor development tend to the coexistence of several Central Processing Units (CPUs) on a single chip. The Cell Broadband Engine (CBE), the fruit of collaboration between Sony, Toshiba and IBM, integrates IBM's legacy PowerPC CPU with a new set of simple cores, all of which communicate through a high speed bus. The multiple cores on the CBE allow users to exploit the parallel nature of their programs. However, it is often difficult to effciently extract the parallelism from an application and to distribute tasks in a suitable fashion. We propose a dataflow approach to CBE computing where the compiler is in charge of task partitioning and of the infrastructure for runtime distribution of tasks. In this work, we present the NCC programming language, Squid compiler and runtime environment. NCC is a strict functional dataflow language that forces explicit variable dependencies, in order to exploit parallelism in the application. NCC code is thus written by the user without specifying parallelism explicitly. The Squid Compiler draws a virtual data flow graph from the NCC source. This graph is then partitionned according to implementation specific criteria into tasks and supertasks. The individual tasks are then translated to ANSI-C, and supertasks are analyzed and transformed into scheduling structures. All tasks are executed by the CBE's simple cores. The Squid Runtime Environment (SRE) interacts with the generated scheduler to order tasks' execution, running the supertasks' scheduling, and managing garbage collection. The SRE runs on the CBE's PowerPC core as a separate thread to implement a host-device paradigm, and as resident code on the s
Les récents efforts en développement de microprocesseurs tendent à une coexistence entre plusieurs Unités Centrales (UC) sur une seule puce. Le Cell Broadband Engine (CBE), le fruit d'une collaboration entre Sony, Toshiba et IBM, intègre le CU patrimonial d'IBM PowerPC, avec un nouvel ensemble d'unités simples, communiquant entre elles avec un bus de haute vitesse. Les nombreueses unités présentes dans le CBE permettent aux utilisateurs d'exploiter la nature parallèle de leurs programmes. Cependant, il est souvent difficile d'extraire le parallélisme d'une application et de distribuer des tâches de façon appropriée. Nous proposons donc d'approcher la programmation du CBE sous une perspective de flux de données où le compilateur est chargé de partitionner les tâches et de l'infrastructure de la distribution des tâches. Dans ce travail, nous présentons la langue de programmation NCC, le compilateur et l'environnement d'exécution Squid. NCC est un langage fonctionnel stricte de flux, qui force les entre variables à être explicites, afin d'exploiter le parallelisme d'une application. Le code NCC est donc rédigé par l'utilsateur sans spécifier le parallelisme explicitement. Le compilateur Squid dessine un graphe de flux de données virtuel issu du code NCC. Ce graphe est partitionné selon des critères particuliers à l'implémentation en tâches et supertâches. Chaque tâche est ensuite traduite en ANSI-C, et les supertâches sont analysées et transformées en structures d'ordonnançement. Toutes les tâches sont exécutées par les untiés simples du CBE. L'Environnement d'Exécution Squid (EES) interagit avec l'ordonnanceur pour ordonner$
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Aji, Ashwin Mandayam. "Exploiting Multigrain Parallelism in Pairwise Sequence Search on Emergent CMP Architectures." Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/33606.

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With the emerging hybrid multi-core and many-core compute platforms delivering unprecedented high performance within a single chip, and making rapid strides toward the commodity processor market, they are widely expected to replace the multi-core processors in the existing High-Performance Computing (HPC) infrastructures, such as large scale clusters, grids and supercomputers. On the other hand in the realm of bioinformatics, the size of genomic databases is doubling every 12 months, and hence the need for novel approaches to parallelize sequence search algorithms has become increasingly important. This thesis puts a significant step forward in bridging the gap between software and hardware by presenting an efficient and scalable model to accelerate one of the popular sequence alignment algorithms by exploiting multigrain parallelism that is exposed by the emerging multiprocessor architectures. Specifically, we parallelize a dynamic programming algorithm called Smith-Waterman both within and across multiple Cell Broadband Engines and within an nVIDIA GeForce General Purpose Graphics Processing Unit (GPGPU). Cell Broadband Engine: We parallelize the Smith-Waterman algorithm within a Cell node by performing a blocked data decomposition of the dynamic programming matrix followed by pipelined execution of the blocks across the synergistic processing elements (SPEs) of the Cell. We also introduce novel optimization methods that completely utilize the vector processing power of the SPE. As a result, we achieve near-linear scalability or near-constant efficiency for up to 16 SPEs on the dual-Cell QS20 blades, and our design is highly scalable to more cores, if available. We further extend this design to accelerate the Smith-Waterman algorithm across nodes on both the IBM QS20 and the PlayStation3 Cell cluster platforms and achieve a maximum speedup of 44, when compared to the execution times on a single Cell node. We then introduce an analytical model to accurately estimate the execution times of parallel sequence alignments and wavefront algorithms in general on the Cell cluster platforms. Lastly, we contribute and evaluate TOSS -- a Throughput-Oriented Sequence Scheduler, which leverages the performance prediction model and dynamically partitions the available processing elements to simultaneously align multiple sequences. This scheme succeeds in aligning more sequences per unit time with an improvement of 33.5% over the naive first-come, first-serve (FCFS) scheduler. nVIDIA GPGPU: We parallelize the Smith-Waterman algorithm on the GPGPU by optimizing the code in stages, which include optimal data layout strategies, coalesced memory accesses and blocked data decomposition techniques. Results show that our methods provide a maximum speedup of 3.6 on the nVIDIA GPGPU when compared to the performance of the naive implementation of Smith-Waterman.
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Cox, Guilherme Mota Cavalcanti de Albuquerque. "Implementação de Visualização de Dados Tridimensionais de Malhas Irregulares no Processador Cell Broadband Engine." Universidade do Estado do Rio de Janeiro, 2009. http://www.bdtd.uerj.br/tde_busca/arquivo.php?codArquivo=8269.

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Direct volume rendering has become a popular technique for visualizing volumetric data from sources such as scientific simulations, analytic functions, and medical scanners, among others. Volume rendering algorithms, such as raycasting, can produce high-quality images, however, the use of raycasting has been limited due to its high demands on computational power and memory bandwidth. In this paper, we propose a new implementation of the raycasting algorithm that takes advantage of the highly parallel architecture of the Cell Broadband Engine processor, with 9 heterogeneous cores, in order to allow interactive raycasting of irregular datasets. All the computational power of the Cell BE processor, though, comes at the cost of a different programming model. Applications need to be rewritten in order to explore the full potential of the Cell processor, which requires using multithreading and vectorized code. In our approach, we tackle this problem by distributing ray computations using the visible faces, and vectorizing the lighting integral operations inside each core. Our experimental results show that we can obtain good speedups reducing the overall rendering time significantly.
A renderização de volume direta tornou-se uma técnica popular para visualização volumétrica de dados extraídos de fontes como simulações científicas, funções analíticas, scanners médicos, entre outras. Algoritmos de renderização de volume, como o raycasting, produzem imagens de alta qualidade. O seu uso, contudo, é limitado devido à alta demanda de processamento computacional e o alto uso de memória. Nesse trabalho, propomos uma nova implementação do algoritmo de raycasting que aproveita a arquitetura altamente paralela do processador Cell Broadband Engine, com seus 9 núcleos heterogêneos, que permitem renderização eficiente em malhas irregulares de dados. O poder computacional do processador Cell BE demanda um modelo de programação diferente. Aplicações precisam ser reescritas para explorar o potencial completo do processador Cell, que requer o uso de multithreading e código vetorizado. Em nossa abordagem, enfrentamos esse problema distribuindo a computação de cada raio incidente nas faces visíveis do volume entre os núcleos do processador, e vetorizando as operações da integral de iluminação em cada um. Os resultados experimentais mostram que podemos obter bons speedups reduzindo o tempo total de renderização de forma significativa.
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Li, Yi-Hsien. "Real-Time Space-Time Adaptive Processing on the STI CELL Multiprocessor." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8933.

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Space-Time Adaptive Processing (STAP) has been widely used in modern radar systems such as Ground Moving Target Indication (GMTI) systems in order to suppress jamming and interference. However, the high performance comes at a price of higher computational complexity, which requires extensive powerful hardware.

The new STI Cell Broadband Engine (CBE) processor combines PowerPC core augmented with eight streamlined high-performance SIMD processing engine offers an opportunity to implement the STAP baseband signal processing without any full custom hardware. This paper presents the implementation of an STAP baseband signal processing flow on the state-of-the-art STI CELL multiprocessor, which enables the concept of Software-Defined Radar (SDR). The potential of the Cell BE processor is studied so that kernel subroutine such as QR decomposition, Fast Fourier Transform (FFT), and FIR filtering of STAP are mapped to the SPE co-processors of Cell BE processor with variety of architectural specific optimization techniques.

This report starts with an overview of airborne radar technique and then the standard, specifically the third-order Doppler-factored STAP are introduced. Next, it goes with the thorough description of Cell BE architecture, its programming tool chain and parallel programming methods for Cell BE. In later chapter, how the STAP is implemented on the Cell BE processor is discussed and the simulation results are presented. Furthermore, based on the result of earlier benchmarking, an optimized task partition and scheduling method is proposed to improve the overall performance.

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Schmuland, Todd E. "Exploiting Parallel Processing Techniques for Implementation of Wideband MUSIC Algorithm on the IBM Cell Broadband Engine Processor." University of Toledo / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1271273869.

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Jakobsson, Teodor. "Parallelization of Animation Blending on the PlayStation®3." Thesis, Linköpings universitet, Informationskodning, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79409.

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An animation system gives a dynamic and life-like feel to character motions, allowing motion behaviour that far transcends the mere spatial translations of classic computer games. This increase in behavioural complexity however does not come for free as animation systems often are haunted by considerable performance overhead, the extent of which reflecting the complexity of the desired system.  In game development performance optimization is key, the pursuit of which is aided by the static hardware configuration of modern gaming consoles. These allow extensive optimization through specializing the application, at whole or in part, to the underlying hardware architecture. In this master's theses a method, that efficiently utilizes the parallel architecture of the PlayStation®3, is proposed in order to migrate the process of animation evaluation and blending from a single-thread implementation on the main processor to a fully parallelized multi-thread solution on the associated coprocessors. This method is further complimented with an in-depth study of the underlying theoretical foundations, as well as a reflection on similar works and approaches as used by other contemporary game development companies.
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Books on the topic "CELL Broadband Engine"

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Koranne, Sandeep. Practical computing on the cell broadband engine. New York: Springer, 2009.

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Koranne, Sandeep. Practical Computing on the Cell Broadband Engine. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0308-2.

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Koranne, Sandeep. Practical Computing on the Cell Broadband Engine. Springer, 2015.

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Koranne, Sandeep. Practical Computing on the Cell Broadband Engine. Springer, 2010.

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Abraham, Arevalo, and International Business Machines Corporation. International Technical Support Organization., eds. Programming the cell broadband engine architecture: Examples and best practices. [Poughkeepsie, NY]: IBM International Technical Support Organization, 2008.

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Abraham, Arevalo, and International Business Machines Corporation. International Technical Support Organization., eds. Programming the cell broadband engine architecture: Examples and best practices. [Poughkeepsie, NY]: IBM International Technical Support Organization, 2008.

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Abraham, Arevalo, and International Business Machines Corporation. International Technical Support Organization., eds. Programming the cell broadband engine architecture: Examples and best practices. [Poughkeepsie, NY]: IBM International Technical Support Organization, 2008.

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Book chapters on the topic "CELL Broadband Engine"

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Scherl, Holger. "Cell Broadband Engine Architecture." In Evaluation of State-of-the-Art Hardware Architectures for Fast Cone-Beam CT Reconstruction, 53–69. Wiesbaden: Vieweg+Teubner, 2011. http://dx.doi.org/10.1007/978-3-8348-8259-2_4.

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Steele, Guy L., Xiaowei Shen, Josep Torrellas, Mark Tuckerman, Eric J. Bohm, Laxmikant V. Kalé, Glenn Martyna, et al. "Cell Broadband Engine Processor." In Encyclopedia of Parallel Computing, 234–41. Boston, MA: Springer US, 2011. http://dx.doi.org/10.1007/978-0-387-09766-4_121.

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Zhang, Huiliang, Bertil Schmidt, and Wolfgang Müller-Wittig. "Accelerating BLASTP on the Cell Broadband Engine." In Pattern Recognition in Bioinformatics, 460–70. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-88436-1_39.

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Koranne, Sandeep. "Introduction." In Practical Computing on the Cell Broadband Engine, 3–15. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0308-2_1.

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Koranne, Sandeep. "Basic Algorithms." In Practical Computing on the Cell Broadband Engine, 145–75. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0308-2_10.

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Koranne, Sandeep. "Graph Theory on the CBEA." In Practical Computing on the Cell Broadband Engine, 177–221. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0308-2_11.

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Koranne, Sandeep. "Alternative methods for parallel programming on SPE." In Practical Computing on the Cell Broadband Engine, 223–44. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0308-2_12.

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Koranne, Sandeep. "Computational Mathematics on the CBEA." In Practical Computing on the Cell Broadband Engine, 245–85. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0308-2_13.

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Koranne, Sandeep. "Vector Graphics on SPU." In Practical Computing on the Cell Broadband Engine, 287–99. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0308-2_14.

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Koranne, Sandeep. "Optimizing SPU Programs." In Practical Computing on the Cell Broadband Engine, 301–8. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0308-2_15.

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Conference papers on the topic "CELL Broadband Engine"

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Takahashi, O., E. Behnen, S. R. Cottier, P. Coulman S. H. Dhong, B. Flachs, P. Hofstee, C. J. Johnson, and S. Posluszny. "Cell Broadband Engine Processor Design Methodology." In 2007 IEEE Custom Integrated Circuits Conference. IEEE, 2007. http://dx.doi.org/10.1109/cicc.2007.4405830.

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Meyer, Nils, F. Belletti, G. Bilardi, M. Drochner, N. Eicker, Zoltan Fodor, Dieter Hierl, et al. "QCD on the Cell Broadband Engine." In The XXV International Symposium on Lattice Field Theory. Trieste, Italy: Sissa Medialab, 2008. http://dx.doi.org/10.22323/1.042.0039.

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Buehrer, Gregory, Srinivasan Parthasarathy, and Matthew Goyder. "Data mining on the cell broadband engine." In the 22nd annual international conference. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1375527.1375534.

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Gschwind, Michael. "Chip multiprocessing and the cell broadband engine." In the 3rd conference. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1128022.1128023.

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Bandyopadhyay, Shibdas, and Sartaj Sahni. "Sorting on a Cell Broadband Engine SPU." In 2009 IEEE Symposium on Computers and Communications (ISCC). IEEE, 2009. http://dx.doi.org/10.1109/iscc.2009.5202227.

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Riley, M., B. Flachs, S. Dhong, G. Gervais, S. Weitzel, M. Wang, D. Boerstler, et al. "Implementation of the 65nm Cell Broadband Engine." In 2007 IEEE Custom Integrated Circuits Conference. IEEE, 2007. http://dx.doi.org/10.1109/cicc.2007.4405831.

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Clark, Scott, Kent Haselhorst, Kerry Imming, John Irish, Dave Krolak, and Tolga Ozguner. "Cell broadband engine interconnect and memory interface." In 2005 IEEE Hot Chips XVII Symposium (HCS). IEEE, 2005. http://dx.doi.org/10.1109/hotchips.2005.7476577.

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Agarwal, Virat, Lurng-Kuo Liu, and David A. Bader. "Financial modeling on the cell broadband engine." In Distributed Processing Symposium (IPDPS). IEEE, 2008. http://dx.doi.org/10.1109/ipdps.2008.4536320.

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Servat, Harald, Cecilia Gonzalez, Xavier Aguilar, Daniel Cabrera, and Daniel Jimenez. "Drug Design on the Cell BroadBand Engine." In 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007). IEEE, 2007. http://dx.doi.org/10.1109/pact.2007.4336253.

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Bkagojevic, Filip, Dimitris S. Nikolopoulos, Alexandros Stamatakis, and Christos D. Antonopoulos. "Dynamic multigrain parallelization on the cell broadband engine." In the 12th ACM SIGPLAN symposium. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1229428.1229445.

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Reports on the topic "CELL Broadband Engine"

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Hauser, Jochem H., Jean-Luc Cambier, Surya Surampudi, and Torsten Gollnick. Cell-NPE (Numerical Performance Evaluation): Programming the IBM Cell Broadband Engine -- A General Parallelization Strategy. Fort Belvoir, VA: Defense Technical Information Center, April 2008. http://dx.doi.org/10.21236/ada525908.

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