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Relevant bibliographies by topics / Charge Pump Phase Locked Loop

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Academic literature on the topic 'Charge Pump Phase Locked Loop'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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Journal articles on the topic "Charge Pump Phase Locked Loop"

1

CHANG, ROBERT C., LUNG-CHIH KUO, and HOU-MING CHEN. "A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP." Journal of Circuits, Systems and Computers 14, no. 05 (October 2005): 997–1006. http://dx.doi.org/10.1142/s0218126605002738.

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A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.

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Charlamov, J., and R. Navickas. "Phase Locked Loop Integrated System." Solid State Phenomena 164 (June 2010): 221–26. http://dx.doi.org/10.4028/www.scientific.net/ssp.164.221.

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CMOS-MEMS integration is an indispensable technique for self-calibration of electromechanical performance to make MEMS devices independent on environmental drift or fabrication errors. The goal of single-chip integration (the “holy grail” for the semiconductor timing industry) would be to include the resonator, the oscillator, the PLL and a temperature compensation circuit (TCC) on a single silicon substrate. The current structure of silicon MEMS-based devices utilizes a stacked-die arrangement, housed in a multi-chip package [1]. MEMS-based timing circuits often use PLLs, which can succumb to phase jitter and noise at higher timing frequencies. The architecture of a charge pump phase locked loop (CPPLL) is proposed in this work. It is discussed how its functional blocks influence the overall system performance. We have performed voltage-controlled oscillator (VCO) phase noise analysis and have determined the relationship between CPPLL and VCO phase noises and have discussed the requirements and results of the accomplished design.

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Nanda, Umakanta, Jyotirmayee Sarangi, and Prakash Kumar Rout. "Study of Recent Charge Pump Circuits in Phase Locked Loop." International Journal of Modern Education and Computer Science 8, no. 8 (August 8, 2016): 59–65. http://dx.doi.org/10.5815/ijmecs.2016.08.08.

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Wang, San-Fu, Tsuen-Shiau Hwang, and Jhen-Ji Wang. "Phase-locked loop design with fast-digital-calibration charge pump." International Journal of Electronics 103, no. 2 (April 24, 2015): 342–54. http://dx.doi.org/10.1080/00207217.2015.1036371.

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Xiang, Qi, Hongxia Liu, and Yulun Zhou. "A Single-Event-Hardened Scheme of Phase-Locked Loop Microsystems for Aerospace Applications." Micromachines 13, no. 12 (November 28, 2022): 2102. http://dx.doi.org/10.3390/mi13122102.

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In order to improve the ability of the phase-locked loop (PLL) microsystem applied in the aerospace environment to suppress the irradiation effect, this study presents an efficient charge pump hardened scheme by using the radiation-hardened-by-design (RHBD) technology. In this study, the sensitivity analysis of the single-event transient (SET) at different nodes of charge pump and different bombardment energies is carried out. Without changing the original structure and loop parameters, a hardened scheme of phase-locked loop to suppress the single-event effect is proposed. A digital control circuit is added between the charge pump and low-pass filter, which greatly reduces the sensitivity of the charge pump to the SET. The classical double-exponential current pulse model is used to simulate the SET effect on the unreinforced and reinforced phase-locked loops, and the reliability of the proposed reinforcement scheme is verified. The simulation results based on the SMIC 130 nm standard complementary metal–oxide–semiconductor (CMOS) process show that the peak value of the transient response fluctuation of the phase-locked loop using the proposed single-event-hardened scheme decreased by 94.2%, the lock recovery time increased by 75.3%, and the maximum phase shift decreased by 90.8%. This shows that the hardened scheme can effectively reduce the sensitivity of the PLL microsystems to the SET effects.

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Hanumolu, P. K., M. Brownlee, K. Mayaram, and U. K. Moon. "Analysis of Charge-Pump Phase-Locked Loops." IEEE Transactions on Circuits and Systems I: Regular Papers 51, no. 9 (September 2004): 1665–74. http://dx.doi.org/10.1109/tcsi.2004.834516.

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Curran, Paul F., Chuang Bi, and Orla Feely. "Dynamics of charge-pump phase-locked loops." International Journal of Circuit Theory and Applications 41, no. 11 (April 19, 2012): 1109–35. http://dx.doi.org/10.1002/cta.1814.

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Kratyuk, Volodymyr, Pavan Kumar Hanumolu, Un-Ku Moon, and Kartikeya Mayaram. "A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 3 (March 2007): 247–51. http://dx.doi.org/10.1109/tcsii.2006.889443.

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Charlamov, Jevgenij. "PLL DESIGN AND INVESTIGATION IN CMOS." Mokslas - Lietuvos ateitis 2, no. 1 (February 28, 2010): 54–58. http://dx.doi.org/10.3846/mla.2010.012.

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In the article the architecture of a charge pump phase locked loop is shown. The influence on overall system performance of its functional blocks is discussed. Voltage controlled oscillator phase noise analysis is done and the relationship between a charge pump phase locked loop and voltage controlled oscillator phase noises are determined. The requirements and results of the accomplished design are discussed. Area of chip PLL – 150×250 μm2, power consumption – 10 mW and phase noise is –125 dBc/Hz with 1 MHz deviation from central 670 MHz frequency.

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Taheri, H. E. "A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop." Engineering, Technology & Applied Science Research 7, no. 2 (April 24, 2017): 1473–77. http://dx.doi.org/10.48084/etasr.1099.

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A low power, low phase noise adaptive bandwidth phase locked loop is presented in this paper. The proposed structure benefits from a novel lock status monitor unit (LSMU) that determines loop operation and loop bandwidth. The loop filter resistance and charge pump current are inversely proportional and bandwidth to reference frequency is maintained fixed. This structure is simulated in 0.18 μm CMOS technology and simulation results are presented.

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Dissertations / Theses on the topic "Charge Pump Phase Locked Loop"

1

Veillette, Benoît R. "On-chip characterization of charge-pump phase-locked loops." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0017/NQ44617.pdf.

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SINGH, GUNEET. "HIGH-FREQUENCY CHARGE-PUMP BASED PHASE-LOCKED LOOP DESIGN AND IT'S CHARACTERIZATION USING VERILOG-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155077793.

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Singh, Guneet. "High-frequency charge-pump based phase-locked loop design and it's characterization using verilog-ams." Cincinnati, Ohio : University of Cincinnati, 2006. http://www.ohiolink.edu/etd/view.cgi?acc%5Fnum=ucin1155077793.

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Thesis (M.S.)--University of Cincinnati, 2006.
Title from electronic thesis title page (viewed Nov. 29, 2006). Includes abstract. Keywords: Phase Locked Loops, PLLs, PLL, Verilog-AMS. Includes bibliographical references.

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Al, Sabbagh Mhd Zaher. "0.18um phase/frequency detector and charge pump design for digital video broadcasting for handheld's phase-locked-loop systems." Columbus, Ohio : Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1196281141.

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Al, Sabbagh Mhd Zaher. "0.18μm phase/frequency detector and charge pump design for digital video broadcasting for handheld’s phase-locked-loop systems." The Ohio State University, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=osu1196281141.

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Terlemez, Bortecene. "Oscillation Control in CMOS Phase-Locked Loops." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4841.

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Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.

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Cheng, Shanfeng. "Design of CMOS integrated phase-locked loops for multi-gigabits serial data links." Texas A&M University, 2006. http://hdl.handle.net/1969.1/4954.

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High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 ÃÂ¼m CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 ÃÂ¼m CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 ÃÂ¼m CMOS technology.

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Scheibe, Niko. "Entwicklung einer monolithisch integrierten 2,44 GHz Phasenregelschleife in der LFoundry 150nm-CMOS Technologie." Master's thesis, Universitätsbibliothek Chemnitz, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-61765.

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Die Spezifikationen und Toleranzbereiche heutiger Hochgeschwindigkeitsdatenübertragungstechnologien nehmen immer weiter an Komplexität, aufgrund der steigenden Informationsmenge, zu. Zur Verarbeitung von Daten in Frequenzbereichen oberhalb von einem Gigahertz sind Referenzsignale notwendig, welche ein äußerst geringes Phasenrauschen aufweisen um benachbarte Kanäle nicht zu beeinflussen. Diese Referenzsignale werden in Mischerschaltungen zur Modulation oder Demodulation zwischen radio frequency (RF)- und intermediate frequency (IF)-Signalen verwendet. Die benötigte Signalform ist eine Sinusschwingung, die nicht durch digitale Schaltungsblöcke erzeugt werden kann. Daher ist die Notwendigkeit von analogen LC-Oszillatoren gegeben. Die Erzeugung von höchst stabilen und hochfrequenten Signalen war lange Zeit teuren Silizium-Germanium-Technologien vorbehalten. Jedoch erfordert der steigende Integrationsgrad und der hart umkämpfte Markt, die Entwicklung von RF-Schaltungen in günstigen CMOS-Technologien. In Zusammenarbeit mit der Landshut Silicon Foundry soll dazu eine monolithisch integrierte Phase-Locked Loop (PLL) mit einer mittleren Ausgangsfrequenz von 2,44 GHz und einem Phasenrauschen kleiner -115 dBc/Hz bei einem Abstand von 1 MHz vom Träger entwickelt werden. Dabei wird das Hauptaugenmerk auf den Kern der PLL gelegt, welcher einen spannungsgesteuerten Oszillator, einen Phasen-/Frequenzdetektor, eine Ladungspumpe, einen Schleifenfilter und einen Frequenzteiler beinhaltet. Außerdem sollen Testszenarien vorgestellt werden, um die Eigenschaften der gefertigten PLL zu bestimmen und zu vergleichen.

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9

Lopes, Bruno Miguel. "Digitally programmable delay-locked-loop with adaptive charge pump current for UWB radar system." Master's thesis, Faculdade de Ciências e Tecnologia, 2010. http://hdl.handle.net/10362/4101.

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Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e Computadores
The objective of this thesis is to study and design a digitally programmable delay locked loop for a UWB radar sensor in 0.13 m CMOS technology.. Almost all logic systems have a main clock signal in order to provide a common timing reference for all of the components in the system. In certain cases it is necessary to have rising (or falling) edges at precise time instants, different from the ones in the main clock. To create those new timing edges at the appropriate time it is necessary to use delay circuits or delay lines. In the case of the radar system its necessary to generate a clock signal with a variable delay. This delay is relative to the transmit clock signal and is used to determine the target distance. Traditionally, delay lines are realized using a cascade of delay elements and are typically inserted into a delay-locked-loop (DLL) to guaranty that the delay is not affected by process and temperature variations. A DLL works in a similar way to a Phase Locked Loop (PLL). In order to facilitate the operation of the radar system, it is important that the delay value should be digitally programmable. To achieve a digitally programmable delay with a large linearity (independent from matching errors), the architecture of the system is constituted by a digital modulator that controls a 1-bit digital to time converter, whose output will be filtered by the DLL, thus producing the delayed clock signal. The electronic sub-blocks necessary to build this circuit are describe in detail as the proposed architectures. These circuits are implemented using differential clock signals in order to reduce the noise level in the radar system. Design and simulation results of the digitally programmable DLL shows a high output jitter noise for large delays. In order to improve this results a new architecture is proposed. Conventional DLL’s have a predefined charge pump current. The new architecture will make the charge pump current variable. Simulations results will show a improved jitter noise and delay error.

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Arnold, Benjamin. "Entwurf, Aufbau und Charakterisierung eines mikromechanischen Gleichspannungswandlers." Universitätsverlag Chemnitz, 2019. https://monarch.qucosa.de/id/qucosa%3A71744.

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Die mikromechanische Gleichspannungswandlung basierend auf verschiebungsabhängigen Kapazitäten stellt eine Alternative zu etablierten rein elektronischen Wandlern für den Spezialfall der kapazitiven oder piezoelektrischen Verbraucher dar. Durch ihre kleine Bauform und den Verzicht auf Induktivitäten bietet sie den Vorteil der On-Chip-MEMS- und CMOS-Integration und ermöglicht die Bereitstellung hoher elektrischer Gleichspannungen aus den verfügbaren Grundspannungen der Elektronik (z. B. 3, 5 bzw. 12 V). Von hohen Polarisationsspannungen profitieren nicht nur kapazitive Sensoren und Aktoren, sondern auch piezoelektrische Messverfahren. Diese Arbeit stellt eine umfangreiche Übersicht und Bewertung der möglichen Bauformen mikromechanischer Gleichspannungswandler sowie die konkrete Umsetzung, Charakterisierung und Modellbildung eines resonant arbeitenden Wandlers vor. Es wird auf Besonderheiten und Probleme im Entwurf eingegangen und ausgehend von den Ergebnissen ein Konzeptentwurf für einen optimierten resonanten Gleichspannungswandler erarbeitet.:1 Einleitung 2 Theoretische Grundlagen 3 Ausführungsvarianten von MEMS-DC/DC-Wandlern 4 Designstudie und Umsetzung des resonanten Funktionsprinzips 5 Zusammenfassung und Ausblick
Micromechanical DC/DC conversion based on variable capacitances is an alternative to established electronic voltage converters, which does not require bulky inductors and is suitable for capacitive and piezoelectric loads. The converters are capable of boosting up the polarization voltage from CMOS and electronic levels (3, 5, 12 V), which is beneficial not only for capacitive sensors and actuators but also for piezoelectric sensing. Advantages of this method are the on-chip- and CMOS-integrability. This thesis introduces a comprehensive overview and evaluation of possible designs as well as the practical application, characterization and modeling of a resonant micromechanical DC/DC converter. Innovative claims include a test board for the characterization of resonant DC/DC converters and a SPICE behavioral model of the device, considering parasitic effects. Characteristics and problems of the design are discussed and the results are used to demonstrate an optimized conceptual design of a resonant DC/DC converter.:1 Einleitung 2 Theoretische Grundlagen 3 Ausführungsvarianten von MEMS-DC/DC-Wandlern 4 Designstudie und Umsetzung des resonanten Funktionsprinzips 5 Zusammenfassung und Ausblick

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Book chapters on the topic "Charge Pump Phase Locked Loop"

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Gogoi, Mriganka, and P. K. Dutta. "Review and Analysis of Charge-Pump Phase-Locked Loop." In Lecture Notes in Electrical Engineering, 565–74. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7031-5_54.

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Rajeshwari, D. S., and P. V. Rao. "Architectures of Charge Pump for Digital Phase Locked Loops." In Lecture Notes in Networks and Systems, 29–38. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-3812-9_3.

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Ansari, Mohammad Amir, Syed Hasan Saeed, and Deepak Balodi. "Charge Pump-Phase Frequency Detector based Phase-Locked Loop for Modern Wireless Communication—A Review." In Proceedings of Trends in Electronics and Health Informatics, 491–97. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-8826-3_42.

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Kumar, Adesh, Anurag Kumar Paliwal, and Saurabh Sharma. "Blueprint of a CMOS Charge Pump for Phase-Locked Loop Synthesizers with High Efficiency." In Lecture Notes in Electrical Engineering, 249–57. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-2999-8_20.

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Prithiviraj, R., and J. Selvakumar. "A Preliminary Study of Oscillators, Phase and Frequency Detector, and Charge Pump for Phase-Locked Loop (PLL) Applications." In Lecture Notes in Electrical Engineering, 9–18. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7251-2_2.

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Divya, Marichamy, and Kumaravel Sundaram. "A Novel Blind Zone Free, Low Power Phase Frequency Detector for Fast Locking of Charge Pump Phase Locked Loops." In Communications in Computer and Information Science, 117–28. Cham: Springer Nature Switzerland, 2022. http://dx.doi.org/10.1007/978-3-031-23973-1_8.

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"Modeling and Simulation of an Analog Charge Pump PhaseLocked Loop." In Monolithic Phase-Locked Loops and Clock Recovery Circuits. IEEE, 2009. http://dx.doi.org/10.1109/9780470545331.ch32.

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Xiao, Jian, Yue Chen, and Yanzhang Qiu. "Improvements on frequency capture range and stability of multi-phase output charge pump Phase-Locked Loop: Improvements on frequency capture range and stability of multi-phase output charge pump Phase-Locked Loop." In Advances in Energy, Environment and Materials Science, 73–76. CRC Press, 2016. http://dx.doi.org/10.1201/b19635-18.

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"Time amplified charge pump PLL." In Phase-Locked Frequency Generation and Clocking: Architectures and circuits for modern wireless and wireline systems, 631–43. Institution of Engineering and Technology, 2020. http://dx.doi.org/10.1049/pbcs064e_ch23.

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"A Fully Integrated CMOS Frequency Synthesizer with ChargeAveraging Charge Pump and DualPath Loop Filter for PCS and CellularCDMA Wireless Systems." In Phase-Locking in High-Performance Systems. IEEE, 2009. http://dx.doi.org/10.1109/9780470545492.ch71.

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Conference papers on the topic "Charge Pump Phase Locked Loop"

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Liu, Huihua, Xian Zhang, Ping Li, and Xiaoliang Xu. "A Hardened Phase-Locked Loop Using Novel Charge Pump." In 2015 8th International Symposium on Computational Intelligence and Design (ISCID). IEEE, 2015. http://dx.doi.org/10.1109/iscid.2015.18.

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Lee, Min-Chin, Ming-Chia Hsieh, and Ya-Ciou Lin. "Design and implementation of charge-pump phase-locked loop." In 2011 IEEE International Workshop on Electromagnetics; Applications and Student Innovation (iWEM). IEEE, 2011. http://dx.doi.org/10.1109/iwem.2011.6021491.

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R G, Raghavendra, and Bharadwaj Amrutur. "Area efficient loop filter design for charge pump phase locked loop." In the 17th great lakes symposium. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1228784.1228823.

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Rajeshwari D S and P. V. Rao. "Precise current matching charge pump for digital phase locked loop." In 2016 Second International Conference on Cognitive Computing and Information Processing (CCIP). IEEE, 2016. http://dx.doi.org/10.1109/ccip.2016.7802854.

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Ye, Yunfei, Ming Zhang, and Junning Chen. "Analysis and Simulation Three Order Charge Pump Phase Locked Loop." In 2008 4th International Conference on Wireless Communications, Networking and Mobile Computing (WiCOM). IEEE, 2008. http://dx.doi.org/10.1109/wicom.2008.564.

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Deng, Honghui, Wei Zhang, and Jielei Bai. "A design of charge pump phase locked loop for DAC." In 2013 International Conference on Anti-Counterfeiting, Security and Identification (ASID). IEEE, 2013. http://dx.doi.org/10.1109/icasid.2013.6825294.

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Ali, M., H. Elsemary, H. Shawkey, and A. Zekry. "A fast locking digital phase-locked loop using programmable charge pump." In Systems (ICCES). IEEE, 2010. http://dx.doi.org/10.1109/icces.2010.5674840.

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Weiping, Chen, Fu Qiang, Yuan Yuan, Song Ran, Li Yaoguang, and Liu Xiaowei. "Design of charge-pump phase locked loop in micro-inertial sensor." In 2011 Academic International Symposium on Optoelectronics and Microelectronics Technology (AISOMT). IEEE, 2011. http://dx.doi.org/10.1109/aismot.2011.6159365.

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Yapeng, Zhang, Ye Tianxiang, and Qu Zhijuan. "Design and implementation of a CMOS charge pump phase-locked loop." In 2018 IEEE 4th Information Technology and Mechatronics Engineering Conference (ITOEC). IEEE, 2018. http://dx.doi.org/10.1109/itoec.2018.8740367.

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Hua, Siliang, Hua Yang, Yan Liu, Quanquan Li, and Donghui Wang. "A power and area efficient CMOS charge-pump phase-locked loop." In 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2012. http://dx.doi.org/10.1109/icsict.2012.6466694.

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