Dissertations / Theses on the topic 'Charge Pump Phase Locked Loop'

Thesis (M.S.)--University of Cincinnati, 2006.
Title from electronic thesis title page (viewed Nov. 29, 2006). Includes abstract. Keywords: Phase Locked Loops, PLLs, PLL, Verilog-AMS. Includes bibliographical references.

Recent advances in voltage-controlled oscillator (VCO) design and the trend of CMOS processing indicate that the oscillator control is quickly becoming one of the forefront problems in high-frequency and low-phase-noise phase-locked loop (PLL) design. This control centric study explores the limitations and challenges in high-performance analog charge-pump PLLs when they are extended to multiple gigahertz applications. Several problems with performance enhancement and precise oscillator control using analog circuits in low-voltage submicron CMOS processes, coupled with the fact that analog (or semi-digital) oscillators having various advantages over their digitally controlled counterparts, prompted the proposal of the digitally-controlled phase-locked loop. This research, then, investigates a class of otherwise analog PLLs that use a digital control path for driving a current-controlled oscillator. For this purpose, a novel method for control digitization is described where trains of pulses code the phase/frequency comparison information rather than the duration of the pulses: Pulse-Stream Coded Phase-Locked Loop (psc-PLL). This work addresses issues significant to the design of future PLLs through a comparative study of the proposed digital control path topology and improved cutting-edge charge-pump PLLs.

High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 μm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 μm CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 μm CMOS technology.

Die Spezifikationen und Toleranzbereiche heutiger Hochgeschwindigkeitsdatenübertragungstechnologien nehmen immer weiter an Komplexität, aufgrund der steigenden Informationsmenge, zu. Zur Verarbeitung von Daten in Frequenzbereichen oberhalb von einem Gigahertz sind Referenzsignale notwendig, welche ein äußerst geringes Phasenrauschen aufweisen um benachbarte Kanäle nicht zu beeinflussen. Diese Referenzsignale werden in Mischerschaltungen zur Modulation oder Demodulation zwischen radio frequency (RF)- und intermediate frequency (IF)-Signalen verwendet. Die benötigte Signalform ist eine Sinusschwingung, die nicht durch digitale Schaltungsblöcke erzeugt werden kann. Daher ist die Notwendigkeit von analogen LC-Oszillatoren gegeben. Die Erzeugung von höchst stabilen und hochfrequenten Signalen war lange Zeit teuren Silizium-Germanium-Technologien vorbehalten. Jedoch erfordert der steigende Integrationsgrad und der hart umkämpfte Markt, die Entwicklung von RF-Schaltungen in günstigen CMOS-Technologien. In Zusammenarbeit mit der Landshut Silicon Foundry soll dazu eine monolithisch integrierte Phase-Locked Loop (PLL) mit einer mittleren Ausgangsfrequenz von 2,44 GHz und einem Phasenrauschen kleiner -115 dBc/Hz bei einem Abstand von 1 MHz vom Träger entwickelt werden. Dabei wird das Hauptaugenmerk auf den Kern der PLL gelegt, welcher einen spannungsgesteuerten Oszillator, einen Phasen-/Frequenzdetektor, eine Ladungspumpe, einen Schleifenfilter und einen Frequenzteiler beinhaltet. Außerdem sollen Testszenarien vorgestellt werden, um die Eigenschaften der gefertigten PLL zu bestimmen und zu vergleichen.

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e Computadores
The objective of this thesis is to study and design a digitally programmable delay locked loop for a UWB radar sensor in 0.13 m CMOS technology.. Almost all logic systems have a main clock signal in order to provide a common timing reference for all of the components in the system. In certain cases it is necessary to have rising (or falling) edges at precise time instants, different from the ones in the main clock. To create those new timing edges at the appropriate time it is necessary to use delay circuits or delay lines. In the case of the radar system its necessary to generate a clock signal with a variable delay. This delay is relative to the transmit clock signal and is used to determine the target distance. Traditionally, delay lines are realized using a cascade of delay elements and are typically inserted into a delay-locked-loop (DLL) to guaranty that the delay is not affected by process and temperature variations. A DLL works in a similar way to a Phase Locked Loop (PLL). In order to facilitate the operation of the radar system, it is important that the delay value should be digitally programmable. To achieve a digitally programmable delay with a large linearity (independent from matching errors), the architecture of the system is constituted by a digital modulator that controls a 1-bit digital to time converter, whose output will be filtered by the DLL, thus producing the delayed clock signal. The electronic sub-blocks necessary to build this circuit are describe in detail as the proposed architectures. These circuits are implemented using differential clock signals in order to reduce the noise level in the radar system. Design and simulation results of the digitally programmable DLL shows a high output jitter noise for large delays. In order to improve this results a new architecture is proposed. Conventional DLL’s have a predefined charge pump current. The new architecture will make the charge pump current variable. Simulations results will show a improved jitter noise and delay error.

Die mikromechanische Gleichspannungswandlung basierend auf verschiebungsabhängigen Kapazitäten stellt eine Alternative zu etablierten rein elektronischen Wandlern für den Spezialfall der kapazitiven oder piezoelektrischen Verbraucher dar. Durch ihre kleine Bauform und den Verzicht auf Induktivitäten bietet sie den Vorteil der On-Chip-MEMS- und CMOS-Integration und ermöglicht die Bereitstellung hoher elektrischer Gleichspannungen aus den verfügbaren Grundspannungen der Elektronik (z. B. 3, 5 bzw. 12 V). Von hohen Polarisationsspannungen profitieren nicht nur kapazitive Sensoren und Aktoren, sondern auch piezoelektrische Messverfahren. Diese Arbeit stellt eine umfangreiche Übersicht und Bewertung der möglichen Bauformen mikromechanischer Gleichspannungswandler sowie die konkrete Umsetzung, Charakterisierung und Modellbildung eines resonant arbeitenden Wandlers vor. Es wird auf Besonderheiten und Probleme im Entwurf eingegangen und ausgehend von den Ergebnissen ein Konzeptentwurf für einen optimierten resonanten Gleichspannungswandler erarbeitet.:1 Einleitung 2 Theoretische Grundlagen 3 Ausführungsvarianten von MEMS-DC/DC-Wandlern 4 Designstudie und Umsetzung des resonanten Funktionsprinzips 5 Zusammenfassung und Ausblick
Micromechanical DC/DC conversion based on variable capacitances is an alternative to established electronic voltage converters, which does not require bulky inductors and is suitable for capacitive and piezoelectric loads. The converters are capable of boosting up the polarization voltage from CMOS and electronic levels (3, 5, 12 V), which is beneficial not only for capacitive sensors and actuators but also for piezoelectric sensing. Advantages of this method are the on-chip- and CMOS-integrability. This thesis introduces a comprehensive overview and evaluation of possible designs as well as the practical application, characterization and modeling of a resonant micromechanical DC/DC converter. Innovative claims include a test board for the characterization of resonant DC/DC converters and a SPICE behavioral model of the device, considering parasitic effects. Characteristics and problems of the design are discussed and the results are used to demonstrate an optimized conceptual design of a resonant DC/DC converter.:1 Einleitung 2 Theoretische Grundlagen 3 Ausführungsvarianten von MEMS-DC/DC-Wandlern 4 Designstudie und Umsetzung des resonanten Funktionsprinzips 5 Zusammenfassung und Ausblick

碩士
國立交通大學
控制工程系
85
A phase-locked loop (PLL) is used to control a voltage control oscillator (VCO) such that the frequency and phase of VCO output will follow the input signal quickly and stably. Hence it is important to reduce the pull-in and lock-in time in designing a PLL. In a charge-pump PLL, the bandwidth is proportional to the speed of system response. Obviously, we could increase the system bandwidth to reduce the pull-in time. However, as the system bandwidth increases, the noise bandwidth increases, resulting in large frequency and phase errors of the PLL system. A commonly used method to solve this problem is to increase the system bandwidth for fast response during pull-in state, and to decrease the system bandwidth for small noise bandwidth during lock-in state. This approach can be realized in many ways, but they may make large swing voltage of VCO input, resulting in VCO and charge-pump overload. In this thesis, a new charge-pump PLL is proposed. The proposed charge-pump PLL can reduce the pull-in time and has constant swing voltage of VCO input such that the VCO and charge-pump overload can be avoided. One realization of this new charge-pump PLL is also included. We also use the Lyaponuv stability method to prove the stability of the proposed charge-pump PLL. Finally, computer simulations are used to verify the performance of this new charge-pump PLL.

碩士
國立清華大學
電機工程學系
97
This thesis proposes a BIST architecture for measuring the period jitter which is represented in two types of peak-to-peak jitter and rms jitter in Charge-Pump PLLs. Comparing with previous BIST circuit, the proposed BIST circuit changes the counter position to increase the measurement resolution and modifies the Charge Pump circuit of TDC to reduce the measurement error. The proposed digital control unit can decrease the testing time that also improves the leakage current effect. Thus, the measurement error is therefore reduced. The simulation results shows that the measurement resolution is about 1ps and that the measurement error is smaller than 15%.

碩士
國立交通大學
電機與控制工程系
88
The charge-pump PLL is a nonlinear time-varying system which is important in many applications. It is desired to have a model which can describe the system as accurately as possible. A complete model for the charge-pump PLL with RC loop filter and linear VCO characteristic is proposed in the thesis. The model derives all difference equations associated with the conditions of lock-in mode, out-of-lock mode, and VCO overload, and combines them to establish a flow chart for the calculations of the exact responses of the system. Simulations are performed to show that the proposed model can more completely describe the system. Further, one phenomenon arises in the charge-pump PLL is the limit cycle of period two. In the thesis we also present the necessary and sufficient condition for the charge-pump PLL to have locally stable limit cycle of period two, and the equilibrium values of timing error and voltage are obtained.

碩士
中華技術學院
電子工程研究所碩士班
92
Based on the analysis of the effects of the charge pump on the phase-locked loops (PLL), this thesis presents a design to enhance the performance of the phase-locked loops by using the complementary metal-oxide semiconductor technology provided by Taiwan Semiconductor Manufacturing Company (TSMC). The functional blocks of the PLL considered in this thesis include a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider. The operating principles and the associated behavior models of these functional blocks will be analyzed. Moreover, the reliability of these behavior models will be verified through the simulation with the TSMC CMOS technology in order to consolidate the design of the PLL and finally enhance the performance of the PLL. The organization of the thesis is as follows: Chapter one provides an overview of the thesis; Chapter two discusses the behavior models of the charge-pump based PLL; Chapter three discusses the implementation of phase-locked loops and their measurement; Chapter four presents a modified architecture of PLL and the associated simulation results. The last chapter concludes this thesis.

碩士
中華大學
電機工程學系碩士班
94
Owing to the system on a chip (SOC), phase-locked loops (PLL) are more closer to our life. In this paper, a charge-pump PLL (CPLL) with high stability over temperature variation is proposed. The CPLL is composed of phase frequency detector (PFD), a charge pump (CP), a voltage control oscillator (VCO) and a divider (DIV). By adding extra small circuits and improving every parts circuits. The whole phase offset and the lock time are reduced. In the beginning of the design, we use Hspice and Quartus II to simulate and verify the accuracy of the circuits. After simulating, we use the TSMC 0.18μm 1P6M technology and 1.8V power supply to realize the circuits on a chip through CIC. The CPLL operates at 1.2GHz with four kinds of different divisors in usable control signal. The lock time is only 16.5 μS, that improves 50% by comparing with conventional CPLL. The output frequency is steadily at 1.2 GHz ± 12 KHz. The variation on temperature is only 16mV from 0° to 80°. The chip area including PAD of CPLL is 910μm × 603μm.

Modern wireless communication systems employ Phase Locked Loop (PLL) mostly for synchronization, clock synthesis, skew and jitter reduction. The performance of PLL affects significantly the signal recovery and system functionality in these systems. Charge pump being one of the important components, decides the functional parameters of PLL. This thesis simulates and analyses some of the major reported charge pump architectures. The present work also proposes an efficient architecture of CMOS charge pump and analyses the design considerations for the proposed circuit. The novel charge pump is designed in Cadence Virtuoso environment and implemented using GPDK090 library of 0.1µm technology and a supply voltage of 1.8V. The performance parameters are compared with other standard and latest charge pump based architectures of PLL. The PLL implemented using proposed charge pump is found to exhibit very low acquisition time of 850ns and consume substantially low power of 0.6041mW.

Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture due to its zero steady state phase error. A monolithic implementation of such a CPPLL presents numerous challenges to PLL designers, the number of such challenges vary depending on the process technology employed and the end application. One such challenge that is worth mentioning is the on-chip integration of the second order passive loop filter. The area occupied by the second order passive loop filter is mainly determined by the zero determining capacitance (CZ). A low loop bandwidth CPPLL has a higher CZ value, and hence consumes a larger die area than a large loop bandwidth CPPLL. Literature survey shows that the problem of higher CZ value in low loop bandwidth CPPLL is addressed by using some form of emulation techniques. A relatively simpler emulation technique is the use of dual charge pump based loop filter. Existing dual charge pump based loop filter consume extra elements (such as summer that need opamps to realize the summer function) for achieving low CZ value. These extra elements consume extra area and additional power. We present two types of Summer-Less Dual Charge Pump (SDCP) based loop filter designs that do not need extra elements and still achieves low CZ value and this is achieved by using a second charge pump in an appropriate way. A test chip was implemented in 0.13µm UMC MMRFCMOS process to verify the presented circuits. The presented SDCP based loop filter circuits are particularly useful in designs employing multiple CPPLL’s and design employing low loop bandwidth CPPLL’s. Another challenge worth-mentioning is the frequency ranges over which the PLL can be locked. The Voltage Controlled Oscillator (VCO) of PLL mainly determines the frequency locking range of a PLL. A typical VCO has a frequency locking range of usually 1:2 to 1:3. The VCO frequency tuning range reduces with reduction in supply voltage. This poses a serious problem in low supply voltage applications that demand a wide frequency locking range, sometimes greater than 1:3. We have addressed this problem of wide PLL lock range, by using an Analog Frequency Detector. A wide frequency lock range is achieved, either by dynamically modifying the VCO or the feedback divider of PLL. Both the approaches are equally feasible. The frequency detector is used for dynamically modifying the VCO or the feedback divider of PLL. Two test chips were implemented to verify the presented Analog Frequency Detector scheme. A testchip implemented in 0.25µm CSM analog process achieves wide frequency lock range by dynamically modifying the feedback divider of PLL. Another testchip implemented in 0.13µm UMC MMRFCMOS process achieves wide frequency lock range by dynamically modifying the center frequency of the VCO. Presented analog frequency detection scheme is particularly useful in applications that demand wide PLL lock range from a single die.

Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture due to its zero steady state phase error. A monolithic implementation of such a CPPLL presents numerous challenges to PLL designers, the number of such challenges vary depending on the process technology employed and the end application. One such challenge that is worth mentioning is the on-chip integration of the second order passive loop filter. The area occupied by the second order passive loop filter is mainly determined by the zero determining capacitance (CZ). A low loop bandwidth CPPLL has a higher CZ value, and hence consumes a larger die area than a large loop bandwidth CPPLL. Literature survey shows that the problem of higher CZ value in low loop bandwidth CPPLL is addressed by using some form of emulation techniques. A relatively simpler emulation technique is the use of dual charge pump based loop filter. Existing dual charge pump based loop filter consume extra elements (such as summer that need opamps to realize the summer function) for achieving low CZ value. These extra elements consume extra area and additional power. We present two types of Summer-Less Dual Charge Pump (SDCP) based loop filter designs that do not need extra elements and still achieves low CZ value and this is achieved by using a second charge pump in an appropriate way. A test chip was implemented in 0.13µm UMC MMRFCMOS process to verify the presented circuits. The presented SDCP based loop filter circuits are particularly useful in designs employing multiple CPPLL’s and design employing low loop bandwidth CPPLL’s. Another challenge worth-mentioning is the frequency ranges over which the PLL can be locked. The Voltage Controlled Oscillator (VCO) of PLL mainly determines the frequency locking range of a PLL. A typical VCO has a frequency locking range of usually 1:2 to 1:3. The VCO frequency tuning range reduces with reduction in supply voltage. This poses a serious problem in low supply voltage applications that demand a wide frequency locking range, sometimes greater than 1:3. We have addressed this problem of wide PLL lock range, by using an Analog Frequency Detector. A wide frequency lock range is achieved, either by dynamically modifying the VCO or the feedback divider of PLL. Both the approaches are equally feasible. The frequency detector is used for dynamically modifying the VCO or the feedback divider of PLL. Two test chips were implemented to verify the presented Analog Frequency Detector scheme. A testchip implemented in 0.25µm CSM analog process achieves wide frequency lock range by dynamically modifying the feedback divider of PLL. Another testchip implemented in 0.13µm UMC MMRFCMOS process achieves wide frequency lock range by dynamically modifying the center frequency of the VCO. Presented analog frequency detection scheme is particularly useful in applications that demand wide PLL lock range from a single die.

碩士
國立臺北科技大學
電腦與通訊研究所
98
Phase-Locked Loops (PLLs) have been widely used in modern wireline and wireless communication systems. The performance of PLLs has been strictly specified in phase noise, timing jitter, and reference spur level. In a PLL, the Voltage Controlled Oscillator (VCO) is sensitive to process variations, Charge Pump (CP) current mismatch. Generally, reducing the loop bandwidth will decrease spur, but it will increase settling time. Besides, spurious tone power can be reduced by increasing the linearity of key circuit blocks such as the CP and divider. In order to overcome these problems, a PLL with fast-digital-calibration technique is proposed. This thesis introduces a fast-digital-calibration technique to reduce current mismatch of CP in PLL. This current mismatch of CP in PLLs generates fluctuations on the input of VCO. Therefore, output of VCO will increase reference spur in PLL. Improving current match of CP not only reduces reference spur but also decreases the static phase offset in PLLs. Therefore, the constant current supports the PLL dynamics precisely. In this brief, a 2.12-to-2.7GHz frequency synthesizer has been verified in TSMC 0.18μm CMOS 1.8V process. In this thesis, it exhibits phase noise 124.5dBc/Hz at 1MHz offset, and VCO tuning range is 27%. By using the fast-digital-calibration technique demonstrates current mismatch of less than 0.97% and the operation range of proposed CP is between 0.2V and 1.6V. Total power consumption is 22.57mW and the settling time takes no more than 25μs in the proposed PLL.

With decreasing feature sizes, lowered supply voltages and increasing operating frequencies, the radiation tolerance of digital circuits is becoming an increasingly important problem. Many radiation hardening techniques have been presented in the literature for combinational as well as sequential logic. However, the radiation tolerance of clock generation circuitry has received scant attention to date. Recently, it has been shown that in the deep submicron regime, the clock network contributes significantly to the chip level Soft Error Rate (SER). The on-chip Phase Locked Loop (PLL) is particularly vulnerable to radiation strikes. In this thesis, we present a radiation hardened PLL design. Each of the components of this design-the voltage controlled oscillator (VCO), the phase frequency detector (PFD) and the charge pump/loop filter-are designed in a radiation tolerant manner. Whenever possible, the circuit elements used in our PLL exploit the fact that if a gate is implemented using only PMOS (NMOS) transistors then a radiation particle strike can result only in a logic 0 to 1 (1 to 0) flip. By separating the PMOS and NMOS devices, and splitting the gate output into two signals, extreme high levels of radiation tolerance are obtained. Our design uses two VCOs (with cross-coupled inverters) and charge pumps, so that a strike on any one is compensated by the other. Our PLL is tested for radiation immunity for critical charge values up to 250fC. Our SPICE-based results demonstrate that after exhaustively striking all circuit nodes, the worst case jitter of our hardened PLL is just 37.4 percent. In the worst case, our PLL returns to the locked state in 2 cycles of the VCO clock, after a radiation strike. These numbers are significant improvements over those of the best previously reported approaches.

碩士
國立臺灣科技大學
電子工程系
89
ABSTRACT In this paper, we report the design of a PLL-based clock generator. The phase locked loop (PLL) components include the phase frequency detector (PFD), the charge pump loop filter (CPF), the current control oscillator (CCO), and the divider. And the phase frequency detector has quickly reset time for high speed PLL, and the differential current control oscillator has good linear range. Besides, we will study noise effect. The components of PLL may contribute noise, and the phase noise of the voltage-controlled oscillator is much more significant than the others. We will compare the immunity to the noise in different path of voltage-controlled oscillator (VCO) and current-controlled oscillator (CCO). The chip of the PLL-based clock generator is fabricated by TSMC 0.6mm single-poly triple-metal n-well CMOS technology. The measurement of the frequency range of CCO is from 93MHzto 410MHz, the input reference frequency range of PLL is from 4MHz to 21MHz, and the output range of PLL is from 8MHz to 336MHz, the maximum power dissipation is 29.12mW at supply voltage 5V, and the chip area is about 980mm╳730mm.

碩士
國立臺灣科技大學
電子工程系
87
In this paper, we make some modifications in the original model of the charge-pump phase locked loop (PLL) and apply this modified model into the clock generator circuit. We also present the result of the practical circuit designed in this manner to verify this modified model. The parameters of this PLL circuit include : the charge pump current (Ip), resistor (R) & capacitor (C) values of the loop filter, the gain (Kv) of the current-controlled oscillator (CCO) and the N-number of the divider. All of the parameters mentioned previously can be implemented by the derived stability and overload figure of our PLL system. This PLL chip is fabricated by 0.6um SPTM process, and it can generate 64MHz clock signal with 25us of locked time. The oscillating frequency range of the CCO is from 120MHz to 320MHz. In this chip, the maximum power dissipation is about 40mW, and the area is about 520um650um.

Phase Synthesis is a fundamental operation in Smart Antennas and other Phased Array systems based on beamforming. There are increasing commercial applications for Integrated Phased Arrays due to their low cost, size and power and also because the RF and digital signal processing can be performed on the same chip. These low cost beamforming applications have augmented interest in Coupled Phase Locked Loop (CPLL) systems for Phase Synthesis. Previous work on the implementation of Phase Synthesis systems using Coupled PLLs for low cost beamforming had the constraint of a limited phase range of ±90°. The idea behind the thesis is that this phase synthesis range can be increased to ±180° through the use of PLLs employing Phase Frequency Detectors(PFDs), which is a significant improvement over conventional coupled-PLL systems. This work presents the detailed design and measurement results for a phase synthesizer using Coupled PLLs for achieving phase shift in the range of ±180°. Several Coupled PLL architectures are investigated and their advantages and limitations are evaluated in terms of frequency controllability, phase difference synthesis control and phase noise of the systems. A two-PLL system implementation using off the shelf components is presented, which generates a steady-state phase difference in the range ±180° using an adjustable DC control current. This is the proof of concept for doing an IC design for a Coupled Phase Locked Loop system. Commercial applications in the Wireless Medical Telemetry Service (WMTS) band motivate the design of a CPLL system in the 608-614 MHz band. The design methodology is presented which shows the flowchart of the IC design process from the system design specifications to the transistor level design. MATLAB simulations are presented to model the system performance quickly. VerilogA modeling of the CPLL system is performed followed by the IC design of the system and each block is simulated under different process and temperature corners. The transistor level design is then evaluated for its performance in terms of phase difference synthesis and phase noise and compared with the initial MATLAB analysis and improved iteratively. The CPLL system is implemented in IBM 130nm CMOS process and consumes 40mW of power from a 1.2V supply with a phase noise performance of -88 dBc/Hz for 177° phase generation.

The Phase-Locked Loop (PLL) is commonly used for frequency synthesis in RF transceivers. It can be implemented in two architectures, namely, fractional-N and integer- N. In this thesis, the integer-N architecture is chosen due to its suitability for frequency planning. Here, a PLL with a low noise output is important to ensure signal purity. There are two dominant noise sources in a PLL, namely, phase noise and periodic noise. In the integer-N PLL, periodic noise is also referred to as a reference spur, where the noise gives rise to multiple reference frequency offsets at the PLL output. Of these two noise sources, this thesis is focused on the analysis and suppression of reference spurs. It is because less work has been carried in the literature regarding spurs, and phase noise is better studied. The main factors underlying reference spurs are discussed. These factors are mainly from the charge pump and phase/frequency detector (PFD) circuit non-idealities, namely, PFD delay, charge pump current leakage, charge pump current mismatch, and rise and fall times characteristic of the charge pump current. Reference spur magnitude can be predicted via a transient analysis. The simulation is time consuming, as the reference spur magnitude can only be captured after the PLL in its locked state. Therefore, the simulation period has to be set long enough to ensure enough data can be obtained to read that state. In this thesis, a reference spur mathematical analysis is presented to accurately estimate the reference spur magnitude. In the analysis, all the circuit non-idealities that contribute to the reference spur are considered. Circuit parameters required in the mathematical analysis can be obtained from transistor level simulation for each circuit. As the simulation for each circuit can be carried out separately, a large amount of simulation time can be saved. The proposed mathematical analysis also can be used to determine the major contributing factor to the problem of reference spurs. The reference spur also can be estimated via behavioural modelling simulation. Behavioural modelling of the PLL using Simulink is presented in this thesis. Each PLL component is modelled separately, and circuit non-idealities contributing to the reference spur are included in the behavioural model. In addition to reference spur estimation, the PLL behavioural model also can be used to visualise the dynamic behaviour of the system. Results from the spur analysis show that a slight mismatch current in the charge pump helps to improve the reference spur performance. This thesis presents an analysis to determine an optimum charge pump current ratio for reference spur suppression, which is caused by the charge pump current mismatch and the switching delay. Further, a ratioed current charge pump circuit is proposed to replace the conventional charge pump circuit for a reference spur performance improvement. This spur suppression technique is implemented using a 180 nm SiGe BiCMOS technology for performance evaluation.
Thesis (Ph.D. )-- University of Adelaide, School of Electrical and Electronic Engineering, 2013

碩士
國立交通大學
電信工程系所
94
This thesis, based on tsmc 0.18um CMOS 1P6M process , PLL, is designed to apply to Local oscillator. PLL includes phase frequency detector、charge pump、loop filter、voltage control oscillator and frequency divider. In the design of DVB-T tuner , we have chosen the input 1MHz of reference frequency, with the system supply voltage at 1.8V. What phase frequency detector adopts is operational high-frequency. Charge pump possesses fast-switching speed, adding feedback amplifier to improve the problem of mismatched current . In terms of loop filter , we adopt two order loop filter to filter the high-frequency ingredient. Besides well-phase noise LC-tank VCO, its adaptability ranges from 2.486 GHz to 3.333 GHz .

碩士
國立臺北科技大學
電機工程系
106
This thesis presents a successive approximation register analog-to-digital converter (SAR ADC), which is fabricated in TSMC 0.25μm 1P3M CMOS high-voltage process for electric car. There are two chips were designed, in this thesis, the first chip(chip1) is a 10-bit 5MS/s SAR ADC; and the second chip(chip2) is the modified one, which is combined a charge-pump phase-locked loop and improved the chip1 sample and hold circuit and dynamic comparator. Two chips used a monotonic capacitor switching procedure to reduce power consumption. A high-speed SAR ADC is hard to implement due to the TSMC 0.25μm CMOS is a high-voltage process, especially for integrating with motor control circuit. The TSMC 0.25μm CMOS high-voltage process lays the NBL (N-type buried layer) in the end for the withstand voltage. This layer leads to all of PMOS bodies to be shorted together. It is necessary to avoid from this negative impact, that the body is connected to source. The measurements of chip1 show that, the SFDR, SNDR, ENOB, power consumption, and chip area are 62.2 dB, 53.82 dB, 8.65 bits, 855 μW, and 0.974×0.975 mm^2, respectively; and that the post simulation of chip2 show that, the SFDR, SNDR, ENOB, power consumption, and chip area are 75.92 dB, 58.23 dB, 9.38 bits, 1256 μW, and 1.261×0.975 mm^2, respectively.

碩士
中原大學
電子工程研究所
91
The aim of this thesis is to design a low voltage charge pump phase locked loop ( CP-PLL ) for clock generator applications. The core circuit blocks of the system consist of a phase frequency detector, charge pump, voltage controlled oscillator, loop filter, divider and crystal oscillator. PLLs contain several circuits: First, the frame of nc-PFD is used to eliminate the dead-zone in the PLL. With an added modified circuit, the proposed PFD overcomes the disadvantage of nc-PFD. The outputs UP and down ( DN ) will never rise at the same time. Second, the VCO is based on a four stages ring oscillator where each stage is a voltage controlled differential delay cell with dual delay paths. The VCO prevents the jitter noise from the power line and substrate. Finally, we use the second order loop filter to decrease the influence of voltage step and filter out the higher frequency noise from phase frequency detector and charge pump. A Pierce crystal oscillator is implemented in the system, which providing a stable 16.62MHz signal to the PLL. The chip has been implemented in the TSMC 0.35μm 1P4M CMOS technology and the layout area of the crystal oscillator is 370x430μm2. The crystal oscillator can be used at resonating frequencies of 16~25MHz. The layout area of the PLL is 400 x 650μm2. For 3V power supply, the input frequency is 16.62MHz that provides by crystal oscillator, and the output frequencies are 16.62MHz, 33.24MHz, and 66.48MHz. The jitter of the output was approximate 270ps at 16.62MHz. The proposed PLL can be used in clock generator and frequency synthesizer applications.

碩士
逢甲大學
電子工程所
98
The goal of this research is to use a standard CMOS process to implement a modified charge pump (CP) with better current-matching property for phase-locked loop (PLL) system. This technique uses differential amplifiers to improve current mismatch for charge pump circuit. This thesis is divided into five parts. Chapter 1 is introducing the background information and applications of phase-locked loops and motivation. The second part is chapter 2, in which the operation mechanisms and related analysis of the phase-locked loops (PLLs) are presented. The current-matching property of charge pump is the most important performance-assessment. Both the dead zone of phase frequency detector (PFD) and the glitch problems make clock- synchronization mistakes in phase-locked loop system and also affect current-matching in charge pump. In addition, the low-pass filter converts current from charge pump output to a proportioned control-voltage for the voltage-controlled oscillator (VCO). Thus, the preceding part of chapter 3 will discuss phase frequency detector (PFD), glitch, and low-pass filter (LPF). And then we review references and introduce several charge pump circuits. The chapter 4, first of all is to analyze and to design the charge pumps discussed in chapter 3 and then we propose a method to modify the current mismatch. After all, the verification of this circuit by simulation, its physical chip layout and the results of measurement are presented in chapter 5. Finally, the conclusion is given in chapter 6. The chip of proposed circuit is implemented with the TSMC 0.18-μm CMOS process and a 2.4GHz frequency synthesizer is used to evaluate the proposed technique. The experimental results show that techniques we used reduce the static phase error and charge sharing significantly. The effect of mismatch is reduced to 1% that is about 8-times better than that of previous works within a range from 0.4V to 1.4 V even if without using negative feedback. Index terms: phase-locked loop (PLL)、charge pump(CP)、 Current mismatch、frequency synthesizer

There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the advent of many new applications over the last few decades. The number of sensor nodes in these applications has also increased tremendously in the order of few hundreds in recent years. A typical sensor node in a WSN consists of circuits like RF transceivers, micro-controllers or DSP, ADCs, sensors, and power supply circuits. The RF transmitter and receiver circuits mainly the frequency synthesizers(synthesis of RF carrier and local oscillator signals in transceivers) consume a significant percentage of its total power due to its high frequency of operation. A charge-pump phase locked loop (CP-PLL) is the most commonly used frequency synthesizer architecture in these applications. The growing demands of WSN applications, such as low power consumption larger number of sensor nodes, single chip solution, and longer duration operation presents several design challenges for these transmitter and frequency synthesizer circuits in these applications and a few are listed below, Low power frequency synthesizer and transmitter designs with better spectral performance is essential for an energy efficient operation of these applications. The spurious tones in the frequency synthesizer output will mix the interference signals from nearby sensor nodes and from other interference sources present nearby ,to degrade the wireless transmitter and receiver performance[1]. With the increased density of sensor nodes (more number of in-band interference sources) and degraded performance of analog circuits in the nano-meter CMOS process technologies, the spur reduction techniques are essential to improve the performance of frequency synthesizers in these applications. A single chip solution of sensor nodes with its analog and digital circuits integrated on the same die is preferred for its low power, low cost, and reduced size implementation. However, the parasitic interactions between these analog and digital sub-systems integrated on a common substrate, degrade the spectral performance of frequency synthesizers in these implementations[2]. Therefore, techniques to improve the mixed signal integration performance of these circuits are in great demand. In this thesis, we present a custom designed energy efficient 2.4 GHz BFSK/ASK transmitter architecture using a low power frequency synthesizer design technique taking advantage of the CMOS technology scaling benefits. Furthermore, a few design guidelinesandsolutionstoimprovethespectralperformanceoffrequency synthesizer circuits and in-turn the performance of transmitters are also presented. The target application being short distance, low power, and battery operated wireless communication applications. The contributions in this thesis are, Spectral performance improvement techniques The CP mismatch current is a dominant source of reference spurs in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect [3]. In this work, we present a CP mismatch current calibration technique using an adaptive body bias tuning of its PMOS transistors. Chip prototype of 2.4 GHzCP-PLLwith the proposed CP calibration technique was fabricated in UMC 0.13 µm CMOS process. Measurements show a CP mismatch current of less than 0.3 µA(0.55 %) using the proposed calibration technique over the VCO control voltage range 0.3 to 1 V. The closed loop PLL measurements using the proposed technique exhibited a 9dB reduction in the reference spur levels across the PLL output frequency range 2.4 -2.5 GHz. The parasitic interactions between analog and digital circuits through the common substrate severely affects the performance of CP-PLLs. In this work, we experimentally demonstrate the effect of periodic switching noise generated from the digital buffers on the performance of charge-pump PLLs. The sensitivity of PLL performance metrics such as output spur level, phase noise, and output jitter are monitored against the variations in the properties of a noise injector digital signal. Measurements from a 500 MHz CP-PLL shows that the pulsed noise injection with the duty cycle of noise injector signal reduced from 50% to 20%, resulted in a 12.53 dB reduction in its output spur level and a 107 ps reduction in its Pk-Pk deterministic period jitter performance. Low power circuit techniques A low power frequency synthesizer design using a digital frequency multiplication technique is presented. The proposed frequency multiply by 3 digital edge combiner design having a very few logic gates, demonstrated a significant reduction in the power consumption of frequency synthesizer circuits, with an acceptable spectral performance suitable for these relaxed performance applications. A few design guidelines and techniques to further improve its spectral performance are also discussed and validated through simulations. Chip prototypes of 2.4 GHz CP-PLLs with and without digital frequency multiplier circuits are fabricated in UMC 0.13 µm CMOS process. The 2.4 GHz CP-PLL using the proposed digital frequency multiplication technique (10.7 mW) consumed a much reduced power compared to a conventional implementation(20.3 mW). A custom designed, energy efficient 2.4 GHz BFSK/ASK transmitter architecture using the proposed low power frequency synthesizer design technique is presented. The transmitter uses a class-D power amplifier to drive the 50Ω antenna load. Spur reduction techniques in frequency synthesizers are also used to improve the spectral performance of the transmitter. A chip prototype of the proposed transmitter architecture was implemented in UMC0.13 µm CMOS process. The transmitter consume14 mA current from a 1.3V supply voltage and achieve improved energy efficiencies of 0.91 nJ/bit and 6.1 nJ/bit for ASK and BFSK modulations with data rates 20Mb/s & 3Mb/s respectively.

There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the advent of many new applications over the last few decades. The number of sensor nodes in these applications has also increased tremendously in the order of few hundreds in recent years. A typical sensor node in a WSN consists of circuits like RF transceivers, micro-controllers or DSP, ADCs, sensors, and power supply circuits. The RF transmitter and receiver circuits mainly the frequency synthesizers(synthesis of RF carrier and local oscillator signals in transceivers) consume a significant percentage of its total power due to its high frequency of operation. A charge-pump phase locked loop (CP-PLL) is the most commonly used frequency synthesizer architecture in these applications. The growing demands of WSN applications, such as low power consumption larger number of sensor nodes, single chip solution, and longer duration operation presents several design challenges for these transmitter and frequency synthesizer circuits in these applications and a few are listed below, Low power frequency synthesizer and transmitter designs with better spectral performance is essential for an energy efficient operation of these applications. The spurious tones in the frequency synthesizer output will mix the interference signals from nearby sensor nodes and from other interference sources present nearby ,to degrade the wireless transmitter and receiver performance[1]. With the increased density of sensor nodes (more number of in-band interference sources) and degraded performance of analog circuits in the nano-meter CMOS process technologies, the spur reduction techniques are essential to improve the performance of frequency synthesizers in these applications. A single chip solution of sensor nodes with its analog and digital circuits integrated on the same die is preferred for its low power, low cost, and reduced size implementation. However, the parasitic interactions between these analog and digital sub-systems integrated on a common substrate, degrade the spectral performance of frequency synthesizers in these implementations[2]. Therefore, techniques to improve the mixed signal integration performance of these circuits are in great demand. In this thesis, we present a custom designed energy efficient 2.4 GHz BFSK/ASK transmitter architecture using a low power frequency synthesizer design technique taking advantage of the CMOS technology scaling benefits. Furthermore, a few design guidelinesandsolutionstoimprovethespectralperformanceoffrequency synthesizer circuits and in-turn the performance of transmitters are also presented. The target application being short distance, low power, and battery operated wireless communication applications. The contributions in this thesis are, Spectral performance improvement techniques The CP mismatch current is a dominant source of reference spurs in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect [3]. In this work, we present a CP mismatch current calibration technique using an adaptive body bias tuning of its PMOS transistors. Chip prototype of 2.4 GHzCP-PLLwith the proposed CP calibration technique was fabricated in UMC 0.13 µm CMOS process. Measurements show a CP mismatch current of less than 0.3 µA(0.55 %) using the proposed calibration technique over the VCO control voltage range 0.3 to 1 V. The closed loop PLL measurements using the proposed technique exhibited a 9dB reduction in the reference spur levels across the PLL output frequency range 2.4 -2.5 GHz. The parasitic interactions between analog and digital circuits through the common substrate severely affects the performance of CP-PLLs. In this work, we experimentally demonstrate the effect of periodic switching noise generated from the digital buffers on the performance of charge-pump PLLs. The sensitivity of PLL performance metrics such as output spur level, phase noise, and output jitter are monitored against the variations in the properties of a noise injector digital signal. Measurements from a 500 MHz CP-PLL shows that the pulsed noise injection with the duty cycle of noise injector signal reduced from 50% to 20%, resulted in a 12.53 dB reduction in its output spur level and a 107 ps reduction in its Pk-Pk deterministic period jitter performance. Low power circuit techniques A low power frequency synthesizer design using a digital frequency multiplication technique is presented. The proposed frequency multiply by 3 digital edge combiner design having a very few logic gates, demonstrated a significant reduction in the power consumption of frequency synthesizer circuits, with an acceptable spectral performance suitable for these relaxed performance applications. A few design guidelines and techniques to further improve its spectral performance are also discussed and validated through simulations. Chip prototypes of 2.4 GHz CP-PLLs with and without digital frequency multiplier circuits are fabricated in UMC 0.13 µm CMOS process. The 2.4 GHz CP-PLL using the proposed digital frequency multiplication technique (10.7 mW) consumed a much reduced power compared to a conventional implementation(20.3 mW). A custom designed, energy efficient 2.4 GHz BFSK/ASK transmitter architecture using the proposed low power frequency synthesizer design technique is presented. The transmitter uses a class-D power amplifier to drive the 50Ω antenna load. Spur reduction techniques in frequency synthesizers are also used to improve the spectral performance of the transmitter. A chip prototype of the proposed transmitter architecture was implemented in UMC0.13 µm CMOS process. The transmitter consume14 mA current from a 1.3V supply voltage and achieve improved energy efficiencies of 0.91 nJ/bit and 6.1 nJ/bit for ASK and BFSK modulations with data rates 20Mb/s & 3Mb/s respectively.